JPS6211252A - Semiconductor device - Google Patents

Abstract

PURPOSE:To relax the effects of heat and stress while maintaining the degree of integration by connecting a bump and a wiring layer through a rectangular region having width wider than the wiring layer and predetermined length on an insulating film in a semiconductor substrate. CONSTITUTION:A Pt layer 23 is formed in width wider than an Au wiring layer 25 on an insulating film 22 in a semiconductor substrate and used as a stress relaxing region 320, a value larger than 5 and smaller than 50 is selected as length mum, and a bump 120 is shaped onto the region 320. According to the constitution, connecting sections resisting a high temperature and high pressure are acquired, thus allowing simultaneous joining with high quality in a device with a large number of leads.

Description

【発明の詳細な説明】 本発明は半導体装置にかかり、特に電極端子と基板上法
線の接続構造、好ましくは、半導体素子に多数の外部導
出用リード端子を取付ける電接端子と、基板上配線の接
続の構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly relates to a connection structure between an electrode terminal and a normal line on a substrate, preferably an electric contact terminal for attaching a large number of lead terminals for external extraction to a semiconductor element, and wiring on a substrate. It concerns the structure of connections.

半導体装置の電極と容器の外側へのリード線との間を電
気的に接続する方法が種々提案されている中で、細い導
線を使用して、相互に接続すべき点に接着する従来のワ
イヤボンディング方式に代って容器の内側のリード線を
延長し、又は可撓性の電気絶縁材料で作られたテープ面
に金属材料の連続箔のリボンを付着し、金属箔から、多
数のリードを形成し、かつ、その端部を先細として半導
体装置の電極端子に突起を設け（バンプ）直接接着する
に充分な接着端を形成し、電極端子（バンプ）に同時に
接続する方法がたとえば特公昭４７−３２０６号公報に
提案されている。While various methods have been proposed for electrically connecting the electrodes of semiconductor devices and the lead wires to the outside of the container, conventional wires that use thin conductive wires and adhere to the points to be connected to each other have been proposed. Instead of the bonding method, extend the lead wire inside the container, or attach a continuous foil ribbon of metal material to the tape surface made of flexible electrically insulating material, and make a large number of leads from the metal foil. For example, in Japanese Patent Publication No. 47, there is a method in which the ends of the protrusions are tapered to form a protrusion (bump) on the electrode terminal of the semiconductor device to form an adhesive end sufficient for direct adhesion, and the end is simultaneously connected to the electrode terminal (bump). This method is proposed in Publication No.-3206.

上記接続方法には、銅を基体とするリードに錫を被せ、
表面が金で覆われたバンプとの間で熱により金／錫の共
晶合金を作り接続する方法と、銅を基体とするリードに
金を被せ、金のバンプとの間で、熱を゛圧力により接続
する熱圧着接続法とがある。熱圧着を行なう、金属構成
として高信頼性を要求される半導体装置には金／金が用
いられ。The above connection method involves covering a copper-based lead with tin,
One method involves creating a gold/tin eutectic alloy using heat between the bumps whose surface is covered with gold, and the other involves covering a copper-based lead with gold and applying heat between it and the gold bumps. There is a thermocompression connection method that connects by pressure. Gold/gold is used in semiconductor devices that are bonded by thermocompression and require high reliability as a metal structure.

一方経済性を要求される半導体装置には銅／銅が用いら
れる傾向にある。On the other hand, copper/copper tends to be used in semiconductor devices that require economic efficiency.

熱圧着を利用して接続する方法は、熱と同時に圧力もか
かることから１機械的強度の強いバンプが要求され１機
械的強度を改善したバンプ構造が特開昭５１−１４７２
５３号公報で提案されている。Since the method of connecting using thermocompression bonding applies both heat and pressure, 1. bumps with strong mechanical strength are required; 1. A bump structure with improved mechanical strength was developed in Japanese Patent Application Laid-Open No. 51-1472.
This is proposed in Publication No. 53.

これは階段状にバンプを構成し、ボンディング時におけ
る応力集中の緩和を断面形状的に考察し、それなりの効
果を有するものである。しかしながら、応力集中による
基板あるいは基板上の絶縁膜の破壊を十分に防止するに
は、基板に対して平面的に視た応力分布をも考慮するこ
とが、バンプには必ず内部配線が接続されているから重
要さなる。This is a method in which bumps are configured in a stepwise manner, and the relaxation of stress concentration during bonding is considered from a cross-sectional perspective, and has a certain effect. However, in order to sufficiently prevent the destruction of the substrate or the insulating film on the substrate due to stress concentration, it is necessary to consider the stress distribution viewed from the plane of the substrate. It is important because it exists.

このことは応力分布すなわち応力集中の形態が機械的の
みならず熱的な要因にも関係することを考えれば、十分
念頭に置かなければならない。This must be kept in mind since the stress distribution, that is, the form of stress concentration, is related not only to mechanical factors but also to thermal factors.

幅が定まり、一定幅の配線と接続すべきバンプとの間を
出来るだけ短かい距離で、又、接続部分についても細い
配線層の巾のまま、バンプ部に接続されていた。このた
め従来の配線層とバンプの接続構造を持った半導体装置
を実際に、熱圧着により、リードとバンプを接続し、接
続強度の確認の為引張り破壊強度試験を行なうと、破壊
モードととして、バンプと内部配線層との接続部分の底
部のシリコン基板、絶縁膜から破壊するものが発生した
。これは、この接続部分に応力が集中するためであり、
その接合部は、熱ストレスなどに起因する経時変化によ
り機械的劣弱による可能性をもっていることとなり、信
頼性見地から望ましくない１ 本発明の目的は、高い集積度を維持し、かつ２２７パダ
ーンの設計を容易にしつつ、上記の欠点を除いて、リー
ドの熱圧着の際かえられる熱と。The width is determined, and the distance between the wiring of a constant width and the bump to be connected is as short as possible, and the connection portion is connected to the bump portion while maintaining the width of the thin wiring layer. For this reason, when a semiconductor device with a conventional wiring layer and bump connection structure is actually connected to the leads and bumps by thermocompression bonding and a tensile fracture strength test is performed to confirm the connection strength, it is determined that the failure mode is Breakage occurred in the silicon substrate and insulating film at the bottom of the connection between the bump and the internal wiring layer. This is because stress is concentrated at this connection,
The joints may be mechanically weakened due to changes over time due to thermal stress, etc., which is undesirable from a reliability standpoint. While simplifying the design and eliminating the above drawbacks, the heat can be replaced during thermocompression bonding of leads.

圧力に充分耐える新規なるバンプと配線の接続構造を提
供することにある。The object of the present invention is to provide a new bump-to-wiring connection structure that can sufficiently withstand pressure.

本発明の特徴は半導体基板の絶縁膜上に設けられたバン
プ（電極端子突起）部と該絶縁膜上を延在する配線層部
とを、該絶縁膜上に設けられ、平面形状が直方形でその
巾が該配線層部の巾よりも広くその長さが５μｍ以上で
５０μｍ以内の応力緩和領域を介して接続されている半
導体装置である。A feature of the present invention is that a bump (electrode terminal protrusion) portion provided on an insulating film of a semiconductor substrate and a wiring layer portion extending on the insulating film are provided on the insulating film and have a rectangular planar shape. The semiconductor device is connected through a stress relaxation region whose width is wider than the width of the wiring layer portion and whose length is 5 μm or more and 50 μm or less.

前記応力緩和領域は巾の広い最下層と、その上に設けら
れた前記配線層部と同じ巾をもって延在せる巾の狭い最
上層とから構成され、これにより段部を形成しているこ
とを好ましい。The stress relaxation region is composed of a wide bottom layer and a narrow top layer extending with the same width as the wiring layer provided thereon, thereby forming a stepped portion. preferable.

上記応力緩和領域の存在により上記熱と応力との影響を
緩和できる。又、同領域は平面形状で直方形状であるか
ら該領域を設けても全体の集積度が実質的に低下するこ
とはなく、かつその設計するマスク設計も標準の基準に
もとづいて行なうことができる。The presence of the stress relaxation region allows the effects of heat and stress to be alleviated. Furthermore, since the region is rectangular in plan view, the provision of the region does not substantially reduce the overall degree of integration, and the mask design can be performed based on standard criteria. .

以下図面に基すいて本発明を説明する。The present invention will be explained below based on the drawings.

第１図（４）、田）は従来技術による半導体装置を示す
もので、１はシリコン基板を示し、２はシリコン酸化膜
、窒化膜等の絶縁膜、３はチタン層、４は白金層、５以
配線用、およびバンプの中間層の金薄膜、６は厚膜金層
を示す。又ここで１００がバンプの部分であり、２００
が内部配線層の部分となる。このバンプの厚膜金属６の
上部に鋼を基体とし表面に金メッキを施したリード（図
示せず）を乗せ、熱と圧力をかけると、リード表面の金
と、厚膜金６が熱圧着により接合される。この接合され
た半導体装置からリードをテンシロンゲージで。Figure 1 (4) shows a semiconductor device according to the prior art, in which 1 is a silicon substrate, 2 is an insulating film such as a silicon oxide film or nitride film, 3 is a titanium layer, 4 is a platinum layer, 5 and above are thin gold films for interconnects and intermediate layers of bumps, and 6 is a thick gold layer. Also, here 100 is the bump part, and 200
is the internal wiring layer. A lead (not shown) with a steel base and gold plating on the surface is placed on top of the thick film metal 6 of this bump, and when heat and pressure are applied, the gold on the lead surface and the thick film gold 6 are bonded by thermocompression. Joined. Lead from this bonded semiconductor device with a tensilon gauge.

半導体装置主面に対し垂直方向に引張り、破壊試験を行
ない、５ｆ４度、及び破壊モードを調べた。A destructive test was performed by pulling in a direction perpendicular to the main surface of the semiconductor device, and the 5f4 degree and failure mode were investigated.

本実験に使用した基板には、リファレンスとして、全く
配線を持たない第１図と同一形状のバンプを同一半導体
装置内に設置し、同一接合条件でバンプ底部のシリコン
基板の破壊発生の割合を調べた。その結果破壊モードで
は、バンプ底部のシリコン基板から破壊するものが２．
５倍発生した。As a reference for the substrate used in this experiment, a bump with the same shape as in Figure 1 without any wiring was installed in the same semiconductor device, and the rate of destruction of the silicon substrate at the bottom of the bump was investigated under the same bonding conditions. Ta. As a result, in the destruction mode, 2.
It occurred 5 times more.

本欠陥の発生はリファレンスバンプとの比較から配線及
び、その接続部による影響は明らかである。From comparison with reference bumps, it is clear that the occurrence of this defect is influenced by the wiring and its connections.

引張り破壊試験で、バンプ底部のシリコン基板が破壊し
ているものを詳細に観察すると、バンプ外周と配線の両
端−の交点、７，８から破壊が発生していることが判っ
た。A detailed observation of the fractured silicon substrate at the bottom of the bump in the tensile fracture test revealed that the fracture occurred at the intersections 7 and 8 between the outer periphery of the bump and both ends of the wiring.

ここで接合の際加えられる熱と圧力に関しバンプ郡部に
印加される圧力により発生する。集中応力及び熱による
歪により、バンプと配線層の接続部の底部のシリコン基
板を破壊するという事実、およびバンプに配線が接続さ
れた構造では、熱圧着に際し加えられる熱と圧力に関し
、配線部には、熱による歪が加わることが考えられる。The heat and pressure applied during bonding are generated by the pressure applied to the bump area. The fact is that concentrated stress and heat-induced strain can destroy the silicon substrate at the bottom of the connection between the bump and the wiring layer, and in a structure where the wiring is connected to the bump, the heat and pressure applied during thermocompression bonding may cause damage to the wiring. It is thought that distortion due to heat is added.

すなわち配線層は導電体であることから、熱伝導率も良
く。In other words, since the wiring layer is a conductor, it has good thermal conductivity.

接合の際加えられる熱が配線部を伝わり、配線部と配線
層の下層の絶縁膜、さらに下層のシリコン基板との間に
大きな温度勾配が発生し、この温度勾配により、配線の
下層の基板に歪（熱歪）が、配線の長手方向に特に大き
く発生する。又、熱は。The heat applied during bonding is transmitted through the wiring, creating a large temperature gradient between the wiring, the insulation film below the wiring layer, and the underlying silicon substrate. Strain (thermal strain) is particularly large in the longitudinal direction of the wiring. Also, the heat.

バンプを通して、配線に加えられることから、バンプ近
傍の配線特にバンプと配線の接続部で、最大となる、と
の認識に基ずいて本発明が達成された。すなわちバンプ
と配線の接続部では、バンプからの圧力による歪、熱に
よる歪に配線部からの熱による歪が、複合されて基板に
クラックが発生し、破壊強度試験で、このクラックが核
となり、基板破壊が発生するものと考えられる。The present invention was achieved based on the recognition that since the damage is added to the wiring through the bump, the maximum amount of damage occurs in the wiring near the bump, particularly at the connection between the bump and the wiring. In other words, at the connection between the bump and the wiring, the strain caused by the pressure from the bump, the strain caused by the heat, and the strain caused by the heat from the wiring part are combined to cause a crack in the board, and in a destructive strength test, this crack becomes the core. It is thought that substrate destruction will occur.

以上の論理に基づき、さらに配線、バンプ形成プロセス
を変えることなく、応力集中、熱歪による基板の破壊を
解決したのが本発明によるバンプと配線の接続部の構造
である。Based on the above logic, the structure of the bump-to-wiring connection portion according to the present invention solves the problem of substrate destruction caused by stress concentration and thermal strain without changing the wiring or bump formation process.

第２図は本発明の第１の実施例を示すものでバンプ部１
２０と配線部２Ｕ−〇−との間に応力緩和領域１孟」が
設けである。すなわち半導体基板の−主面上の絶縁膜２
２上に形成したチタン、白金層２３を薄膜金層２５の配
線部の巾より広い巾に形成して応力緩和領域３２０とし
、その長さｍは。FIG. 2 shows a first embodiment of the present invention.
A stress relaxation region 1" is provided between the wiring section 20 and the wiring section 2U. In other words, the insulating film 2 on the main surface of the semiconductor substrate
The titanium and platinum layer 23 formed on the thin film gold layer 25 is formed to have a width wider than the width of the wiring part of the thin film gold layer 25 to form a stress relaxation region 320, and its length m is.

効果を発揮させるために５μｍ以上とし、又、その効果
が飽和される長さである５０μｍ以下とする。The length is set to 5 μm or more to exhibit the effect, and the length is set to 50 μm or less, which is the length at which the effect is saturated.

これを従来技術の構造と前記した実験方法と同様の比較
実験を行った結果バンプ底部のシリコン基板破壊の割合
が従来技術の１．５件に対して、この実施例では１件で
あり、このように直線状に、平面的に階段状に応□゛力
緩和領域を設けても熱歪に対し効果が大であることが判
明した。この実施例で配線層部２２０の金層２５の下に
は同じ巾のチタン層および白金層が第１図のように設け
られている。又、バンプ部Ｌｌｌはチタン、白金層２３
上に金層２５を設け、その上に厚い金バンプ２６を設け
である。同図から明らかのようにバンプ部は２段形状と
なっている。A comparison experiment was conducted using the structure of the prior art and the experimental method described above, and the result was that the rate of silicon substrate breakage at the bottom of the bump was 1.5 in the prior art, but 1 in this example. It has been found that even if the stress relaxation region is provided in a straight line or in a planar step-like manner, it is highly effective against thermal strain. In this embodiment, a titanium layer and a platinum layer of the same width are provided under the gold layer 25 of the wiring layer section 220, as shown in FIG. In addition, the bump portion Lll is made of titanium and platinum layer 23.
A gold layer 25 is provided thereon, and thick gold bumps 26 are provided thereon. As is clear from the figure, the bump portion has a two-step shape.

第４図は本発明の第２の実施例であり、半導体基板の一
主面上の絶縁膜５２の上のｖＸｌの層５３および第２の
層５５の応力緩和領ＬＬＬＱにおける平面形状は同一の
形状すなわち領域Ｌｌｌは階段状となっていない例であ
り、許容応力によってはこのような構造でもよい。すな
わち、この実施例ではバンプ部１５０は千タン、白金の
第１の層５３、その上のうすい金の第２の層５５．その
上の厚い金バンプの第３の層５６から２段形状となって
いるが、応力緩和領域１五１および配線層部２５０は同
一平面形状の第１の層と第２の層とから構成されている
。FIG. 4 shows a second embodiment of the present invention, in which the vXl layer 53 on the insulating film 52 on one main surface of the semiconductor substrate and the stress relaxation region LLLQ of the second layer 55 have the same planar shape. This is an example in which the shape, that is, the region Lll is not step-like, and such a structure may be used depending on the allowable stress. That is, in this embodiment, the bump portion 150 is made of a first layer 53 of titanium, platinum, and a thin second layer 55 of gold thereon. The third layer 56 of thick gold bumps thereon has a two-step shape, but the stress relaxation region 151 and the wiring layer section 250 are composed of the first layer and second layer having the same planar shape. has been done.

本発明により、従来の配線製造プロセスを変えることな
く、高温、高圧力に耐える電極端子と配線の接続部構造
が実現出来、リードとバンプの接合金属の選択がより広
範囲なものななり、高品質、信頼性の接合が可能となっ
た。又、大規模集積化されたリード数の多い半導体装置
の高品質で、安価な、同時接合が可能となり、その工業
的意義は極めて大きい。又、実施例ではバンプ部は全て
２階段状であったが、本発明はこれに限定されることで
は勿論なく、１段又は無段あるいは３段以上の多段でも
よい。又、応力緩和領域は無段、１段状に限定されず、
２段以上の多段でもよい。さらにバンプ部、応力緩和領
域部、配線層部の電気伝導層は実施例に限定されること
はなし、又、場合によっては各々の部分の対応する層を
異なる材料で作りそれぞれを連続的に形成してもよい。The present invention makes it possible to realize a connection structure between electrode terminals and wiring that can withstand high temperatures and high pressure without changing the conventional wiring manufacturing process, and allows for a wider selection of bonding metals for leads and bumps, resulting in high quality. , reliable joining is now possible. In addition, it becomes possible to simultaneously bond high-quality, inexpensive, large-scale integrated semiconductor devices with a large number of leads, which is of extremely great industrial significance. Further, in the embodiment, all the bump portions have a two-step shape, but the present invention is of course not limited to this, and may have one step, no steps, or multiple steps of three or more steps. Moreover, the stress relaxation region is not limited to stepless or single step shape,
It may be multistage with two or more stages. Furthermore, the electrically conductive layers of the bump portion, stress relaxation region portion, and wiring layer portion are not limited to the examples, and in some cases, the corresponding layers of each portion may be made of different materials and formed successively. It's okay.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図囚および第１図（Ｂ）は従来技術による半導体装
置を示す平面図および側面図である。第２図は本発明の
第１の実施例を示す平面図である。第３図は本発明の第
２の実施例を示す平面図である。 尚、図において、１はシリコン基板、２，２２゜５２は
絶縁膜、３はチタン層、４は白金属、７゜８はバンプ外
周と配線の両端部との交点、２３゜５３は最下層、２５
はバンプ部の中間層および配線部の最上層、２６．５６
はバンプ部の最上層、し立０，１２麿はバンプ部、２０
０　、η４立。 礼Σ立は配線層部、３２０，３５０は応力緩和領第　／
　図 乙FIG. 1 and FIG. 1(B) are a plan view and a side view showing a semiconductor device according to the prior art. FIG. 2 is a plan view showing the first embodiment of the present invention. FIG. 3 is a plan view showing a second embodiment of the invention. In the figure, 1 is a silicon substrate, 2, 22° 52 is an insulating film, 3 is a titanium layer, 4 is a white metal, 7° 8 is the intersection of the bump outer periphery and both ends of the wiring, and 23° 53 is the bottom layer. , 25
is the middle layer of the bump part and the top layer of the wiring part, 26.56
is the top layer of the bump part, Shidachi 0, 12 is the bump part, 20
0, η4 standing. 320 and 350 are stress relaxation regions /
Figure Otsu

Claims (2)

【特許請求の範囲】[Claims] （１）半導体基板の絶縁膜上に設けられたバンプ部と該
絶縁膜上を延在する配線層部とを、該絶縁膜上に設けら
れ、平面形状が直方形でその巾が該配線層部の巾よりも
広くその長さが５μｍ以上で５０μｍ以内の応力緩和領
域を介して接続されていることを特徴とする半導体装置
。(1) A bump part provided on an insulating film of a semiconductor substrate and a wiring layer part extending on the insulating film are provided on the insulating film, and have a rectangular planar shape and a width of the wiring layer part. A semiconductor device characterized in that the semiconductor device is connected through a stress relaxation region whose length is wider than the width of the portion and whose length is 5 μm or more and 50 μm or less. （２）前記応緩和領域は巾の広い最下層と、その上に設
けられた前記配線層部と同じ巾をもって延在せる巾の狭
い最上層とから構成され、これにより段部を形成してい
ることを特徴とする特許請求の範囲第（１）項記載の半
導体装置。(2) The relaxation region is composed of a wide lowermost layer and a narrower uppermost layer extending with the same width as the wiring layer provided thereon, thereby forming a stepped portion. A semiconductor device according to claim (1), characterized in that: