JPS62109544U - - Google Patents

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Publication number
JPS62109544U
JPS62109544U JP20035585U JP20035585U JPS62109544U JP S62109544 U JPS62109544 U JP S62109544U JP 20035585 U JP20035585 U JP 20035585U JP 20035585 U JP20035585 U JP 20035585U JP S62109544 U JPS62109544 U JP S62109544U
Authority
JP
Japan
Prior art keywords
circuit
output
voltage controlled
pass filter
mark
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20035585U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP20035585U priority Critical patent/JPS62109544U/ja
Publication of JPS62109544U publication Critical patent/JPS62109544U/ja
Pending legal-status Critical Current

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  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例に係るFSK変調回
路の系統図、第2図は従来のFSK変調回路の系
統図である。 1:電圧制御発振回路、2:可変分周回路、3
:位相比較回路、4:低域ろ波回路、5:レベル
変換回路、6:加算回路、7:発振回路、8:デ
ータ入力、9:変調出力。
FIG. 1 is a system diagram of an FSK modulation circuit according to an embodiment of the present invention, and FIG. 2 is a system diagram of a conventional FSK modulation circuit. 1: Voltage controlled oscillation circuit, 2: Variable frequency divider circuit, 3
: Phase comparison circuit, 4: Low-pass filter circuit, 5: Level conversion circuit, 6: Addition circuit, 7: Oscillator circuit, 8: Data input, 9: Modulation output.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入力電圧によつて周波数の変化する電圧制御発
振回路と、電圧制御発振回路の出力を入力データ
のマークおよびスペースにより異なつた分周比で
分周する可変分周回路と、可変分周回路の出力と
基準信号との位相差を検出する位相比較回路と、
位相比較回路の出力を直流化する低域ろ波回路と
、入力データのマークおよびスペースのレベルを
変換するレベル変換回路と、低域ろ波回路の出力
と、レベル変換回路の出力とを加算し電圧制御発
振回路を制御する加算回路と、基準信号を発生さ
せる発振回路とを有することを特徴とするFSK
変調回路。
A voltage controlled oscillator circuit whose frequency changes depending on the input voltage, a variable frequency divider circuit which divides the output of the voltage controlled oscillator circuit with a frequency division ratio that differs depending on the mark and space of input data, and an output of the variable frequency divider circuit. a phase comparison circuit that detects a phase difference between the signal and the reference signal;
A low-pass filter circuit converts the output of the phase comparison circuit into DC, a level conversion circuit converts the mark and space levels of the input data, and the output of the low-pass filter circuit and the output of the level conversion circuit are added together. FSK characterized by having an addition circuit that controls a voltage controlled oscillation circuit and an oscillation circuit that generates a reference signal.
Modulation circuit.
JP20035585U 1985-12-25 1985-12-25 Pending JPS62109544U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20035585U JPS62109544U (en) 1985-12-25 1985-12-25

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20035585U JPS62109544U (en) 1985-12-25 1985-12-25

Publications (1)

Publication Number Publication Date
JPS62109544U true JPS62109544U (en) 1987-07-13

Family

ID=31162786

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20035585U Pending JPS62109544U (en) 1985-12-25 1985-12-25

Country Status (1)

Country Link
JP (1) JPS62109544U (en)

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