JPS6210039B2 - - Google Patents
Info
- Publication number
- JPS6210039B2 JPS6210039B2 JP322679A JP322679A JPS6210039B2 JP S6210039 B2 JPS6210039 B2 JP S6210039B2 JP 322679 A JP322679 A JP 322679A JP 322679 A JP322679 A JP 322679A JP S6210039 B2 JPS6210039 B2 JP S6210039B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- gold paste
- solder
- plating
- patterns
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000010931 gold Substances 0.000 claims description 49
- 229910052737 gold Inorganic materials 0.000 claims description 49
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 47
- 238000007747 plating Methods 0.000 claims description 32
- 229910000679 solder Inorganic materials 0.000 claims description 28
- 238000000034 method Methods 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 9
- 238000009713 electroplating Methods 0.000 claims description 3
- 150000002343 gold Chemical class 0.000 claims description 2
- 239000010949 copper Substances 0.000 description 9
- 229910052802 copper Inorganic materials 0.000 description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 7
- 239000002390 adhesive tape Substances 0.000 description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 239000000919 ceramic Substances 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 238000005019 vapor deposition process Methods 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000002241 glass-ceramic Substances 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
Landscapes
- Manufacturing Of Printed Wiring (AREA)
Description
【発明の詳細な説明】
本発明はパターン形成方法に関し、詳しくは厚
膜回路基板の回路パターン形成等に適用される方
法に係る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pattern forming method, and more particularly to a method applied to forming circuit patterns on thick film circuit boards.
周知の如く、IC、LSI等を実装する厚膜回路基
板においては、主として金ペーストを導体（回路
パターン）とし、ガラスセラミツクを絶縁基板と
して構成している。しかしながら、金ペーストは
容易に半田に拡散するため、半田付された導体の
形成に適さない。 As is well known, thick film circuit boards on which ICs, LSIs, etc. are mounted are mainly constructed using gold paste as a conductor (circuit pattern) and glass ceramic as an insulating substrate. However, gold paste easily diffuses into the solder, making it unsuitable for forming soldered conductors.
このようなことから、本発明者は先に金ペース
ト上に銅、ニツケル等のメツキ膜を付着して、金
ペーストの拡散バリアとする方法（特願昭53―
4291号）を提案した。この方法は絶縁基板に互に
独立した金ペーストパターンを形成した後、基板
全面にTi又はCrを蒸着し、さらにCu又はNiを蒸
着して前記各金ペーストパターンの共通接続とす
る二層構造の金属蒸着膜を造る。次いで、この金
属蒸着膜全面に電気メツキ処理してメツキ膜を付
着した後、レジスト塗布、露光、現像処理して金
ペーストパターン上の領域を除く部分が露出した
レジストパターンを造り、ひきつづき該レジスト
パターンをマスクとしてエツチングし、二層構造
の金属蒸着膜及びメツキ膜で拡散が防止された金
パターンを形成する。 For these reasons, the present inventor proposed a method of first depositing a plating film of copper, nickel, etc. on the gold paste to serve as a diffusion barrier for the gold paste (Japanese Patent Application No.
No. 4291) was proposed. This method has a two-layer structure in which mutually independent gold paste patterns are formed on an insulating substrate, then Ti or Cr is vapor-deposited on the entire surface of the substrate, and then Cu or Ni is vapor-deposited to provide a common connection between the gold paste patterns. Create a metal vapor deposition film. Next, after applying electroplating to the entire surface of this metal vapor deposited film to adhere a plating film, resist coating, exposure, and development are performed to create a resist pattern in which the portion excluding the area on the gold paste pattern is exposed, and then the resist pattern is Using this as a mask, etching is performed to form a gold pattern in which diffusion is prevented by a two-layer metal vapor deposition film and plating film.
しかしながら、上記方法にあつては２回の蒸着
処理やエツチング処理を必要とするため高価な蒸
着設備を要するばかりか、工数が多大となり歩留
り低下や作業能率の低下を招く。 However, the above method requires two vapor deposition processes and an etching process, which not only requires expensive vapor deposition equipment but also requires a large number of man-hours, resulting in a decrease in yield and work efficiency.
これに対し、本発明者は上記先願発明の欠陥を
解消するために鋭意研究を重ねた結果、金ペース
ト膜はその表面の凹凸による楔効果により密着性
の良好なメツキ膜形成が可能で、しかも半田に拡
散することに着目し、夫々独立した金ペーストパ
ターンを同様な金ペーストで共通接続し、該共通
接続部をマスクして電気メツキ処理し、ひきつづ
きマスク除去、半田処理を施すことによつて、共
通接続部の金ペーストが半田に拡散すると同時に
メツキ膜上に半田が付着し、金ペースト膜、メツ
キ膜及び半田膜の三層構造からなる互に電気的に
絶縁されたパターンを蒸着工程、エツチング工程
を必要とせずに形成し得る法を見い出した。 On the other hand, the inventor of the present invention has conducted extensive research in order to eliminate the defects of the prior invention, and has found that the gold paste film can form a plating film with good adhesion due to the wedge effect caused by the unevenness of the surface. Moreover, focusing on diffusion into the solder, we commonly connected separate gold paste patterns with similar gold paste, masked the common connection part, electroplated it, and then removed the mask and soldered it. As the gold paste in the common connection area diffuses into the solder, the solder adheres to the plating film at the same time, forming an electrically insulated pattern consisting of a three-layer structure of the gold paste film, the plating film, and the solder film. discovered a method that can be formed without the need for an etching process.
即ち、本発明は絶縁基板上に金ペースト膜、半
田に対して拡散し難いメツキ膜及び半田膜の三層
構造から成る互いに独立した複数のパターンを形
成するにあたり、上記絶縁基板上に互いに独立し
た複数の金ペーストパターンを形成すると共に、
それらのパターンを線状の金ペースト膜で共通接
続する工程と、この線状金ペースト膜にメツキマ
スクを選択的に被覆した後、各々の金ペーストパ
ターンのいずれかを陰極として電解メツキを施
し、各金ペーストパターン上に半田に対して拡散
し難いメツキ膜を被着する工程と、メツキマスク
の除去後、半田浴に浸漬せしめて前記メツキ膜上
に半田膜を付着させると共に、露出した前記線状
金ペースト膜を半田浴中に拡散除去して金ペース
トパターン、メツキ膜及び半田膜からなる三層構
造の複数のパターンを電気的に分離する工程とを
具備したことを特徴とするものである。 That is, in forming a plurality of mutually independent patterns consisting of a three-layer structure of a gold paste film, a plating film that does not easily diffuse to solder, and a solder film on an insulating substrate, Along with forming multiple gold paste patterns,
After the process of commonly connecting these patterns with a linear gold paste film and selectively covering this linear gold paste film with a plating mask, electrolytic plating is performed using one of each gold paste pattern as a cathode. A process of depositing a plating film on the gold paste pattern that is difficult for solder to diffuse, and after removing the plating mask, immersing it in a solder bath to adhere a solder film on the plating film, and removing the exposed linear gold. This method is characterized by comprising the step of diffusing and removing the paste film into a solder bath to electrically isolate a plurality of patterns having a three-layer structure consisting of a gold paste pattern, a plating film, and a solder film.
本発明における金ペーストパターン、線状金ペ
ースト膜の形成手段としては、例えばシルク印刷
法等が採用し得る。この線状金ペースト膜の幅は
小さすぎると、各金ペーストパターン間の電気接
続を充分達成できなくなり、かといつて大きすぎ
ると、半田浴浸漬等の拡散が遅くなつたり、半田
劣化が早まるため、通常50〜300μｍ程度にする
ことが望ましい。 As a method for forming the gold paste pattern and the linear gold paste film in the present invention, for example, silk printing can be employed. If the width of this linear gold paste film is too small, it will not be possible to achieve sufficient electrical connection between each gold paste pattern, and if it is too large, diffusion during solder bath immersion will be slow, and solder deterioration will be accelerated. , usually desirably about 50 to 300 μm.
本発明におけるメツキマスクとしては、例えば
フオトレジスト、接着テープ等を挙げることがで
き、特に接着テープはマスクの取付作業、除去作
業が簡便なため有益である。 Examples of the plating mask in the present invention include photoresists, adhesive tapes, etc. Adhesive tapes are particularly useful because they are easy to attach and remove the mask.
本発明における半田に拡散し難いメツキ膜とし
ては、例えばCuメツキ膜、Niメツキ膜等を挙げ
ることができる。なお、必要に応じて、このメツ
キ膜に対する半田の濡れ性を向上するために、該
メツキ膜に薄い金メツキ膜を被覆してもよい。 Examples of the plating film that is difficult to diffuse into solder in the present invention include a Cu plating film and a Ni plating film. Note that, if necessary, the plating film may be coated with a thin gold plating film in order to improve the wettability of the solder to the plating film.
次に、本発明を厚膜回路基板の端子部の形成に
適用した例について第１図ａ，ｂ〜第４図ａ，ｂ
を参照して説明する。 Next, examples in which the present invention is applied to the formation of terminal portions of thick film circuit boards are shown in FIGS. 1a and b to 4a and b.
Explain with reference to.
実施例
まず、第１図ａ，ｂに示す如くセラミツク基板
１上にシルク印刷法により夫々独立した厚さ15μ
ｍの金ペーストパターン２…２を形成すると同
時、各パターン２…２を電気的に接続する幅150
μｍ、厚さ15μｍの線状金ペースト膜３…３を形
成した。その後、線状金ペースト膜３…３を接着
テープ４…４で被覆した（第２図ａ，ｂ図示）。
ひきつづき、金ペーストパターン２…２の最左端
のパターンを陰極とし、電気銅メツキ処理を施し
て金ペーストパターン２…２上に厚さ20μｍの銅
メツキ膜５…５を選択的に被着した後、接着テー
プ４…４を剥離除去して共通接続部としての線状
金ペースト膜３…３を露出させた（第３図ａ，ｂ
図示）。この時、銅メツキ膜５…５は金ペースト
パターン２…２上に密着性よく形成されていた。Embodiment First, as shown in FIG.
At the same time, a width of 150 m is formed to electrically connect each pattern 2...2.
A linear gold paste film 3 was formed with a thickness of 15 μm and a thickness of 15 μm. Thereafter, the linear gold paste films 3...3 were covered with adhesive tapes 4...4 (as shown in FIGS. 2a and 2b).
Subsequently, using the leftmost pattern of the gold paste patterns 2...2 as a cathode, electrolytic copper plating is performed to selectively deposit a copper plating film 5...5 with a thickness of 20 μm on the gold paste patterns 2...2. , the adhesive tapes 4...4 were peeled off to expose the linear gold paste films 3...3 as common connection parts (Fig. 3 a, b).
(Illustrated). At this time, the copper plating films 5...5 were formed on the gold paste patterns 2...2 with good adhesion.
次いで、銅メツキ膜５…５が形成されたセラミ
ツク基板１をpb／snの半田浴中に浸漬したとこ
ろ、露出した線状金ペースト膜３…３が半田浴中
に拡散して除去されると共に、銅メツキ膜５…５
上に半田が付着され、第４図ａ，ｂに示す如きセ
ラミツク基板１上に金ペースト膜２…２、銅メツ
キ膜５…５及びPb／Sn半田膜６…６からなる三
層構造の互に電気的に絶縁された端子部７…７を
形成できた。 Next, when the ceramic substrate 1 on which the copper plating films 5...5 were formed was immersed in a PB/SN solder bath, the exposed linear gold paste films 3...3 were diffused into the solder bath and removed. , copper plating film 5...5
Solder is deposited on top of the ceramic substrate 1 as shown in FIGS. It was possible to form electrically insulated terminal portions 7...7.
なお、本発明のパターン形成方法における共通
接続部としての線状金ペースト膜は上記実施例の
如く金ペーストパターン相互を独立した複数のも
ので接続する形態に限定されず、例えば第５図に
示す如く、メインの線状ペースト膜３１とこのペ
ースト膜３１に接続し、かつ各金ペーストパター
ン２…２と接続する分枝線状ペースト膜３２…３
２で形成してもよい。このような形態の線状ペー
スト膜を用いれば、そのペースト膜へのマスクが
一つで済み、特にマスクとして接着テープを用い
る場合、マスク作業が著しく簡便となる。 Note that the linear gold paste film as a common connection part in the pattern forming method of the present invention is not limited to the form in which the gold paste patterns are connected to each other by a plurality of independent parts as in the above embodiment; for example, as shown in FIG. As shown, a main linear paste film 3 1 and branch linear paste films 3 2 . . . 3 connected to this paste film 3 1 and connected to each gold paste pattern 2 .
2 may be formed. If a linear paste film of this type is used, only one mask is required for the paste film, and especially when adhesive tape is used as the mask, the masking operation becomes extremely simple.
以上詳述した如く、本発明によれば装置コスト
が高く、煩雑な蒸着工程、エツチング工程を施す
ことなく、極めて簡単かつ生産性よく金ペースト
膜、メツキ膜及び半田膜の三層構造からなる互に
電気的に絶縁された複数のパターンを形成でき、
もつて厚膜回路基板の回路パターン形成などに有
効に利用できる等顕著な効果を有する。 As described in detail above, according to the present invention, a three-layer structure consisting of a gold paste film, a plating film, and a solder film can be formed extremely simply and with high productivity without requiring a high equipment cost or complicated vapor deposition process or etching process. can form multiple electrically isolated patterns,
It has remarkable effects such as being able to be effectively used for forming circuit patterns on thick film circuit boards.
第１図ａ，ｂ〜第４図ａ，ｂは本発明の実施例
における端子部形成工程を示すもので、第１図ａ
〜第４図ａは平面図、第１図ｂは第１図ａの―
断面図、第２図ｂは第２図ａの―断面図、
第３図ｂは第３図ａの―断面図、第４図ｂは
第４図ａの―断面図である。第５図は本発明
の他の実施例を示す金ペーストパターン、線状金
ペースト膜形成後の状態の平面図である。
１…セラミツク基板、２…金ペーストパター
ン、３，３１，３２…線状金ペースト膜、４…接
着テープ、５…銅メツキ膜、６…半田膜、７…端
子部。
1a, b to 4 a, b show the terminal part forming process in an embodiment of the present invention.
~Figure 4a is a plan view, Figure 1b is a plan view of Figure 1a.
A cross-sectional view, FIG. 2b is a cross-sectional view of FIG. 2a,
FIG. 3b is a cross-sectional view of FIG. 3a, and FIG. 4b is a cross-sectional view of FIG. 4a. FIG. 5 is a plan view showing another embodiment of the present invention after forming a gold paste pattern and a linear gold paste film. DESCRIPTION OF SYMBOLS 1... Ceramic substrate, 2... Gold paste pattern, 3, 3 1 , 3 2 ... Linear gold paste film, 4... Adhesive tape, 5... Copper plating film, 6... Solder film, 7... Terminal portion.
Claims (1)
散し難いメツキ膜及び半田膜の三層構造から成る
互いに独立した複数のパターンを形成するにあた
り、上記絶縁基板上に互いに独立した複数の金ペ
ーストパターンを形成すると共に、それらのパタ
ーンを線状の金ペースト膜で共通接続する工程
と、この線状金ペースト膜にメツキマスクを選択
的に被覆した後、各々の金ペーストパターンのい
ずれかを陰極として電解メツキを施し、各金ペー
ストパターン上に半田に対して拡散し難いメツキ
膜を被着する工程と、メツキマスクの除去後、半
田浴に浸漬せしめて前記メツキ膜上に半田膜を付
着させると共に、露出した前記線状金ペースト膜
を半田浴中に拡散除去して金ペーストパターン、
メツキ膜及び半田膜からなる三層構造の複数のパ
ターンを電気的に分離する工程とを具備したこと
を特徴とするパターン形成方法。1. When forming a plurality of mutually independent patterns consisting of a three-layer structure of a gold paste film, a plating film that is difficult to diffuse into solder, and a solder film on an insulating substrate, a plurality of mutually independent gold pastes are formed on the insulating substrate. A process of forming patterns and commonly connecting these patterns with a linear gold paste film, and selectively covering the linear gold paste film with a plating mask, and then using one of each gold paste pattern as a cathode. A step of applying electrolytic plating to deposit a plating film that does not easily diffuse to solder on each gold paste pattern, and after removing the plating mask, immersing it in a solder bath to deposit a solder film on the plating film, The exposed linear gold paste film is diffused and removed in a solder bath to form a gold paste pattern,
A pattern forming method comprising the step of electrically separating a plurality of patterns having a three-layer structure consisting of a plating film and a solder film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP322679A JPS5595392A (en) | 1979-01-13 | 1979-01-13 | Method of forming pattern |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP322679A JPS5595392A (en) | 1979-01-13 | 1979-01-13 | Method of forming pattern |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5595392A JPS5595392A (en) | 1980-07-19 |
| JPS6210039B2 true JPS6210039B2 (en) | 1987-03-04 |
Family
ID=11551523
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP322679A Granted JPS5595392A (en) | 1979-01-13 | 1979-01-13 | Method of forming pattern |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5595392A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61123193A (en) * | 1984-11-20 | 1986-06-11 | アルプス電気株式会社 | Printed wiring board |
| JP2007234889A (en) * | 2006-03-01 | 2007-09-13 | Shinko Electric Ind Co Ltd | Method of forming wiring |
-
1979
- 1979-01-13 JP JP322679A patent/JPS5595392A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5595392A (en) | 1980-07-19 |
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