JPS6199360A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6199360A JPS6199360A JP59221029A JP22102984A JPS6199360A JP S6199360 A JPS6199360 A JP S6199360A JP 59221029 A JP59221029 A JP 59221029A JP 22102984 A JP22102984 A JP 22102984A JP S6199360 A JPS6199360 A JP S6199360A
- Authority
- JP
- Japan
- Prior art keywords
- stage
- package
- lead
- moisture
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Physics & Mathematics (AREA)
- Geometry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置のステージリード又はリードフレ
ームの構造に関するものであり、特に半導体装置のパッ
ケージ内のステージリード、又はリードフレームの断線
とか接触不良が、パンケージのモールド自体に含まれる
湿気によることも無視できないが、その大部分の原因が
、パッケージの外側に露出しているステージリードやリ
ードフレームの引出し部と、モールドされたパッケージ
との間の僅かな間隙を伝わって、外部の湿度がパッケー
ジ内に浸入し、パッケージ内のチップとステージリード
及びリードフレームとのボンデング部分を腐食すること
によるものであり、半導体装置の信頼性を高めるために
こ屁の改善が要望されている。Detailed Description of the Invention [Field of Industrial Application] The present invention relates to the structure of a stage lead or lead frame of a semiconductor device, and particularly to the structure of a stage lead or lead frame in a package of a semiconductor device. Although it cannot be ignored that failures are caused by moisture contained in the pancage mold itself, the majority of failures are caused by moisture between the molded package and the stage lead or lead frame drawer that is exposed outside the package. This is due to external humidity penetrating into the package through the small gap between them and corroding the bonding parts between the chip inside the package and the stage leads and lead frame. Improvements in this fart are requested.
半導体装置のパッケージの種類には、多くの形式があり
、気密性については金属ケースを使用したパンケージや
、セラミックパッケージの方が気密性が良好であって、
パッケージの外部からの湿度による３７６ｙ１３をあま
り受けないが、プラスチック樹脂等でモールドするパッ
ケージでは、完全な耐湿性が期待出来ず、屡々湿度によ
る断線などの不具合が発生ずる。There are many types of packages for semiconductor devices, and in terms of airtightness, pan cages using metal cases and ceramic packages have better airtightness.
Although the package does not receive much 376y13 due to humidity from the outside, packages molded with plastic resin or the like cannot be expected to have complete moisture resistance, and problems such as wire breakage due to humidity often occur.
従って、本発明で通用される半導体装置は、主としてプ
ラスチック樹脂を使用したモールド用パッケージの場合
について湿度の防止を提案するものである。Therefore, the semiconductor device applicable to the present invention proposes prevention of humidity mainly in the case of a mold package using plastic resin.
第３図（ａ）は従来の半導体装置のパッケージの内部に
あるステージリード及びリードフレームの構造を説明す
るための側断面図であり、第３図（′ｂ）は同じく正面
の断面図である。FIG. 3(a) is a side sectional view for explaining the structure of a stage lead and lead frame inside a conventional semiconductor device package, and FIG. 3('b) is a front sectional view. .
プラスチック材料で形成されたパッケージ１があって、
その内部にステージ２があり、その上にチップ３がボン
デングされているが、ボンデングはステージ表面に形成
された金又は銀のメッキ層と、チップ基板であるシリコ
ン材料とで共晶合金４が形成され、それによってチップ
はステージに固定されている。There is a package 1 made of plastic material,
There is a stage 2 inside it, and a chip 3 is bonded onto it. During bonding, a eutectic alloy 4 is formed between a gold or silver plating layer formed on the stage surface and the silicon material that is the chip substrate. The chip is thereby fixed to the stage.
ステージと接続されているリード５は、一方はパッケー
ジの外部に取り出され、他方はパンケージの縁で切断さ
ているが、いずれもパッケージを貫通してパッケージの
外部に取り出されているものであり、又リードフレーム
６も同様にパッケージ１の外部に引き出されているもの
で、この場合にリード５やリードフレーム６とパッケー
ジとの間には接合面に僅かな間隙ができる。One of the leads 5 connected to the stage is taken out to the outside of the package, and the other is cut at the edge of the pan cage, but both lead through the package and taken out to the outside of the package. The lead frame 6 is also drawn out to the outside of the package 1, and in this case, a small gap is created between the leads 5 and the lead frame 6 and the package at the joint surface.
この場合に、チップに接続されるリードフレームや、ス
テージに接続されるリードがパッケージ内で直線状であ
ると、パフケージの外部の湿気が間隙を伝わって、チッ
プの内部に短距離で浸入するため、湿気が最も短時間で
チップとり−ドフレーム又はリードとのボンデング部に
到達することになり、そのためにボンデングの部分が腐
食されて接続不良とか断線の原因になる。In this case, if the lead frame connected to the chip or the leads connected to the stage are straight inside the package, moisture from outside the puff cage will travel through the gap and enter the inside of the chip over a short distance. In the shortest possible time, moisture reaches the bonding portion between the chip frame or the lead, which corrodes the bonding portion and causes a connection failure or disconnection.
上記の構成の半導体装置では、半導体装置のパッケージ
の内部でチップにボンデングされたステージリード又は
リードフレームが直線状であるために、ステージリード
又はリードフレームとパフケージ間の間隙を伝わってく
る湿気が距離的に最短距離であることが問題点であり、
そのために、湿気がパンケージ内に浸入しボンデング部
分を腐食して断線になる等の不具合を生ずる。In the semiconductor device with the above configuration, the stage lead or lead frame bonded to the chip inside the semiconductor device package is linear, so moisture that travels through the gap between the stage lead or lead frame and the puff cage can spread over a distance. The problem is that it is the shortest distance,
Therefore, moisture infiltrates into the pan cage and corrodes the bonding portion, causing problems such as wire breakage.
本発明は、上記問題点を解消した半導体装置を提供する
もので、その手段は、パッケージ内に配置されたステー
ジのリード又は半導体チップから １のリ
ードフレームを、該パッケージ内で複数段の折り曲げを
行い、リードフレームの全体の長さを長くするようにし
たことを特徴とする半導体装置によって達成できる。The present invention provides a semiconductor device that solves the above-mentioned problems, and its means include bending one lead frame from a stage lead or a semiconductor chip disposed within a package in multiple stages within the package. This can be achieved by a semiconductor device characterized in that the overall length of the lead frame is increased.
本発明は半導体装置のパッケージ内に、ステージリード
又はリードフレームとパッケージとの間隙を伝わって、
湿気が浸入してチップとステージリード又はリードうレ
ーム部のボンデング部が断線することの原因であること
から、リードフレームを複数回の折り曲がりを有する段
を形成し、実効的にリードフレームの長さを長くするこ
とによりパンケージ外部からの湿気の浸入を阻止するよ
うに考慮したものである。The present invention provides a method for transmitting a signal into a package of a semiconductor device through a gap between a stage lead or a lead frame and the package.
Since moisture infiltration can cause disconnection between the chip and the stage lead or the bonding part of the lead frame, the lead frame is formed into steps with multiple bends to effectively shorten the length of the lead frame. This design is designed to prevent moisture from entering from outside the pan cage by increasing the length.
半導体装置のパンケージの外部から浸入する湿度の影響
は、ステージリード又はリードフレームとモールドとの
間にある僅かな間隙に沿って水分が浸入するものである
からステージリード又はリードフレームの設計に改善が
加える必要があり、そのための一方法として、ステージ
リード又はリードフレームの長さを実効的に長くするこ
とば極めて有効である。The influence of moisture that enters from the outside of the semiconductor device pancage is caused by moisture entering along the small gap between the stage lead or lead frame and the mold, so improvements can be made in the design of the stage lead or lead frame. One method for this purpose is to effectively increase the length of the stage lead or lead frame.
第１図は本発明の実施例である半導体装置の断面図であ
るが、本実施例ではステージリードの場合について説明
する。FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention, and in this embodiment, a case of a stage lead will be explained.
第１図において、半導体装置のパッケージ１１があり、
その内部にステージ１２があって、その上にチップ１３
がボンデングされていて、ステージリード１４がある。In FIG. 1, there is a package 11 for a semiconductor device,
There is a stage 12 inside, and a chip 13 on top of it.
is bonded and there is a stage lead 14.
ステージリード１４とパッケージ１１との間には僅かな
間隙があり、この間隙を伝わってパフケージの外部から
湿気が浸入する。There is a slight gap between the stage lead 14 and the package 11, and moisture infiltrates from outside the puff cage through this gap.
従って、ステージリードの長さを長くすれば、その分だ
け浸入する湿度に対し、浸入径路に阻止の抵抗が付与さ
れることになり、パッケージ内で可能な限り瓜い距離と
することにより効果が大きいので、ステージリード１４
に、複数の折り曲げ部をつけて蛇行するように複数の段
差１５を設けである。Therefore, if the length of the stage lead is increased, resistance will be added to the infiltration path to prevent moisture from entering. Because it is large, stage lead 14
A plurality of steps 15 are provided in a meandering manner with a plurality of bent portions.
段差の構成はパンケージの内部の体積やリードフレーム
の位置関係で一律には規定できないが、０．５ｍｍ程度
のピッチで段差をつけるのが比較的容易であると共に効
果が顕著である。。Although the structure of the step cannot be uniformly defined depending on the internal volume of the pan cage and the positional relationship of the lead frame, it is relatively easy to form the step at a pitch of about 0.5 mm, and the effect is remarkable. .
第２図は他の実施例の半導体装置の断面図であるが、ス
テージリード２０を直線方向に下方、又は上方向に折り
曲げて、段差２１を設けたもので、この構造にしてもス
テージリードの実効長さが長くなり効果は同一である。FIG. 2 is a cross-sectional view of a semiconductor device according to another embodiment, in which a stage lead 20 is bent downward or upward in a straight line to provide a step 21. The effective length becomes longer, but the effect is the same.
以上はステージリードの場合について説明したが、チッ
プに接続されるリードフレームの場合でも全く同様であ
り、湿気に対する抵抗性を有する手段として段付きのリ
ードフレームを形成することができる。Although the case of a stage lead has been described above, the same applies to a lead frame connected to a chip, and a stepped lead frame can be formed as a means for providing resistance to moisture.
以上詳細に説明したように、本発明の半導体装置のステ
ージリード又はリードフレームの構造を採用することに
より耐湿性が優れ、そのためにチップ上のボンデング部
分が腐食されて断線するというおそれがなく、高信頼性
の半導体装置が供し得るという効果大なるものがある。As explained in detail above, by adopting the structure of the stage lead or lead frame of the semiconductor device of the present invention, it has excellent moisture resistance, and therefore there is no fear that the bonding part on the chip will be corroded and disconnected, and the structure is high. There is a great effect that a reliable semiconductor device can provide.
第１図、第２図は本発明の半導体装置のパッケージの内
部におけるステージリードを説明するための断面図、
第３図は従来の半導体装置のパンケージの内部における
リードフレームの形状を説明するための断面図である。
図において、１１はパッケージ、１２はステージ、１３
はチップ、１４はステージリード、１５は段差、２゜は
ステージリード、２１は段差をそれぞれ示している。1 and 2 are cross-sectional views for explaining the stage lead inside the package of the semiconductor device of the present invention, and FIG. 3 is a cross-sectional view for explaining the shape of the lead frame inside the conventional semiconductor device package. FIG. In the figure, 11 is a package, 12 is a stage, and 13
14 is a chip, 14 is a stage lead, 15 is a step, 2° is a stage lead, and 21 is a step.
Claims (1)
チップからのリードフレームを、該パッケージ内で複数
段の折り曲げを行い、リードフレームの全体の長さを長
くするようにしたことを特徴とする半導体装置。1. A semiconductor device, characterized in that a lead frame from a stage lead or a semiconductor chip arranged in a package is bent in multiple stages within the package to increase the overall length of the lead frame.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59221029A JPS6199360A (en) | 1984-10-19 | 1984-10-19 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59221029A JPS6199360A (en) | 1984-10-19 | 1984-10-19 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6199360A true JPS6199360A (en) | 1986-05-17 |
Family
ID=16760367
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59221029A Pending JPS6199360A (en) | 1984-10-19 | 1984-10-19 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6199360A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5264730A (en) * | 1990-01-06 | 1993-11-23 | Fujitsu Limited | Resin mold package structure of integrated circuit |
| US5288698A (en) * | 1990-02-01 | 1994-02-22 | Mitsubishi Denki Kabushiki Kaisha | Method of positioning lead frame on molding die to seal semiconductor element with resin |
| US5703396A (en) * | 1995-10-31 | 1997-12-30 | Nec Corporation | Plastic encapsulated semiconductor device having wing leads |
| CN111668107A (en) * | 2012-12-06 | 2020-09-15 | 美格纳半导体有限公司 | Multi-chip package and method of manufacturing the same |
-
1984
- 1984-10-19 JP JP59221029A patent/JPS6199360A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5264730A (en) * | 1990-01-06 | 1993-11-23 | Fujitsu Limited | Resin mold package structure of integrated circuit |
| US5288698A (en) * | 1990-02-01 | 1994-02-22 | Mitsubishi Denki Kabushiki Kaisha | Method of positioning lead frame on molding die to seal semiconductor element with resin |
| US5703396A (en) * | 1995-10-31 | 1997-12-30 | Nec Corporation | Plastic encapsulated semiconductor device having wing leads |
| CN111668107A (en) * | 2012-12-06 | 2020-09-15 | 美格纳半导体有限公司 | Multi-chip package and method of manufacturing the same |
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