JPS6195555A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6195555A JPS6195555A JP21700784A JP21700784A JPS6195555A JP S6195555 A JPS6195555 A JP S6195555A JP 21700784 A JP21700784 A JP 21700784A JP 21700784 A JP21700784 A JP 21700784A JP S6195555 A JPS6195555 A JP S6195555A
- Authority
- JP
- Japan
- Prior art keywords
- wiring pattern
- interlayer insulating
- insulating film
- contact hole
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明は半導体装置の製造方法に関し、配線パターンの
稠密化と断線事故の低減に寄与するものである。DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Field The present invention relates to a method for manufacturing a semiconductor device, and contributes to making wiring patterns denser and reducing disconnection accidents.
（口１ 従来の技術
半導体基板上の第１配線パターンと、該第１配線パター
ン上の肋間配線円上の第２配線）くターンとを、眉間配
線層に付設のコンタクトホールを通じて接続する場合、
従来の技術（例えば「電子材料４１９８２年別冊第２７
頁の図６に示されているもの）では第１配線パターンは
その第２配線パターンとの接続部分を巾広に形成してお
きこの巾広部分内にコンタクトホールの開口部が収まる
ようにしていた（第２図参照）。図中（１）は第１配線
パターン、（２）は巾広部分、（３）はコンタクトホー
ルの位置である。この巾広部分を配備しない場合、コン
タクトホールの成形精度を十分に良くしない、とコンタ
クトホールの開口部が第１配線ノくターンのパターン外
にずれて配設されるおそれがらり、このようになると第
３図に示す如く基板（４）上の第１配線パターン（５）
と層間絶縁膜（６１上の第２配線）くターン（７１との
接続において、上記ずれに対応して出来たすきま（８）
によって第２配線パターン（７）に断線（９）を生じて
しまうおそれがあった。(1) Prior art When connecting a first wiring pattern on a semiconductor substrate and a second wiring on an intercostal wiring circle on the first wiring pattern through a contact hole provided in the glabella wiring layer,
Conventional technology (for example, "Electronic Materials 41982 Special Issue No. 27")
In the case of the first wiring pattern (shown in Figure 6 on page 1), the connection part of the first wiring pattern with the second wiring pattern is formed wide so that the opening of the contact hole can fit within this wide part. (See Figure 2). In the figure, (1) is the first wiring pattern, (2) is the wide portion, and (3) is the position of the contact hole. If this wide portion is not provided, the forming precision of the contact hole will not be sufficiently improved, and there is a risk that the opening of the contact hole will be placed outside the pattern of the first wiring turn. The first wiring pattern (5) on the board (4) as shown in Figure 3
and the interlayer insulating film (second wiring on 61) and the gap (8) created in response to the above deviation in connection with 71.
Therefore, there was a risk that a disconnection (9) would occur in the second wiring pattern (7).
ビーｌ 発明が：葬決しようとする問題点第１配線パタ
ーンに巾広部分を設けて第２配線パターンの断線を防止
しようとすると第１配線ハターンをり１・４成する隣接
パターン間のピッチカ大きくなり配諜パターンのく、を
密化ひい工は半導体装なの高集貨化に適合しない。一方
、このＰ４密化を達成するため上記巾広部分を設けない
場合コンタクトネールの位置合わせがプ１しく上述の如
く第２配線パターンが；υ１ｆＪｌシてしまうおそれが
ある。Problems that the invention attempts to solve When trying to prevent disconnection of the second wiring pattern by providing a wide part in the first wiring pattern, the pitch difference between adjacent patterns forming 1 and 4 of the first wiring pattern increases. As the espionage distribution pattern grows larger, the denser processing technology is not suitable for the high concentration of semiconductor equipment. On the other hand, if the wide portion is not provided in order to achieve this P4 density, the alignment of the contact nails will be poor and there is a risk that the second wiring pattern will be distorted as described above.
本発明；１第１配課パターンの配線ピッチを・ｊＸさく
し″Ｃ高果偵１ヒを図ると共に第２配線パターンの１折
腺を防止する半導体装置の製造方法を堤供しようとげる
ものでちる。The present invention aims to provide a method for manufacturing a semiconductor device that reduces the wiring pitch of the first wiring pattern by reducing the wiring pitch of the first wiring pattern, and also prevents the second wiring pattern from folding. .
に）問題点を解決するための手段
本発明：」半４本基板上の第１配准パターンと該基板表
面上に層間絶縁色を設けこの１５間絶縁層にコンタクト
ホールを開設した後、このコンタクトネール内に膜厚が
層間絶縁層の厚さより小さい補助金Ｉ＆膜を月設し、そ
の後この補助金属膜上な含め層間絶縁膜上・て第２配線
パターンを設けるものて必る。2) Means for Solving the Problems The present invention: After providing a first alignment pattern on a half-four board and an interlayer insulating color on the surface of the board, and opening a contact hole in this 15-way insulating layer, It is necessary to provide an auxiliary I& film whose film thickness is smaller than that of the interlayer insulating layer in the contact nail, and then to provide a second wiring pattern on the interlayer insulating film including the auxiliary metal film.
（ホ）作用
層間絶縁膜のコンタクトホールが第１配線バメーンの領
域外にずＪｌてもこのずれによるすきまの中に補助金属
膜が補充さハるので１層間絶縁膜上に配設する第２配線
パターンが上６ｃすさま内に陥没して断線することがな
い。(e) Even if the contact hole of the working interlayer insulating film is not outside the area of the first wiring board, the auxiliary metal film is filled in the gap caused by this deviation, so the second contact hole is disposed on the first interlayer insulating film. The wiring pattern does not sink into the top 6c and break.
（へ）実施例
第１図（ａｌ〜ｔｅｌに２ｇ−発明方法の工程説明図で
ある。各１に５いて［＋１は半導体基板、−は第１配４
パターン、３０は層間絶縁膜、菊はレジスト膜、蜘に補
助金属膜、山は第２配線パターンである。(f) Example Fig. 1 (al to tel 2g- is an explanatory diagram of the process of the invention method. 5 for each 1 [+1 is the semiconductor substrate, - is the first
The pattern 30 is an interlayer insulating film, the chrysanthemum is a resist film, the spider is an auxiliary metal film, and the mountain is a second wiring pattern.
半導体基板（１０１はその表層部分にトランジスタ等の
素子（−示省略）が設けらルており、該素子に接ネ元さ
れる八ｇよりなる第１配線パターン■が基板表面（１）
）に設けられている。そしてこの第１配線パターン囚の
上に第２配線パターンｔＵｔ形成するために第１配線パ
ターン■上を含む基板表面ｕｌｌ上ＶｃＯＶＤ法にて層
間絶縁膜ωを設置する。次いで、この層間絶縁膜Ｑ上に
レジスト膜間を配置してコンタクトホールＣ刊ヲ形成す
べき位置のレジスト膜明に穴＋４１）を形成する。しか
しこの穴！４】１はマスクアライメントの精度上の問題
からＶ示の如く所望値ｉｉｔからずれて形成されるおそ
れがある（第１図ａ診藺）。上記穴ＡＩＩを利用して、
層間絶縁膜■にコンタクトホール（ｓｌ１４形成する（
第１図ｂ）。このとき上記ずれによっ″Ｃ第１配線パタ
ーンＣＯに隣接する部分のん板表面が１５出される。こ
の状態でし・ジス） ｊ、ｊ、ｐを・除去し、層間絶縁
膜上に第２配線パターン金役けると第３図に示す如く第
２配線パターンがｊＪｊｌばするおそれがあるが本発明
ではこれ２次の処理を、￥行することで防止することを
特徴とするものでちる。A semiconductor substrate (101) has an element (- not shown) such as a transistor on its surface layer, and a first wiring pattern (1) consisting of 8g connected to the element is on the surface of the substrate (101).
). Then, in order to form a second wiring pattern tUt on this first wiring pattern, an interlayer insulating film ω is placed on the substrate surface ull including the first wiring pattern ① by the VcOVD method. Next, a hole +41) is formed in the resist film at a position where a contact hole C is to be formed by arranging a gap between the resist films on this interlayer insulating film Q. But this hole! 4) Due to problems with the accuracy of mask alignment, there is a possibility that the mask 1 may be formed deviating from the desired value iit as shown in V (diagnosis in FIG. 1a). Using the hole AII above,
A contact hole (sl14) is formed in the interlayer insulating film (
Figure 1 b). At this time, due to the above-mentioned deviation, 15 parts of the surface of the board adjacent to the first wiring pattern CO are exposed. If the wiring pattern is damaged, there is a possibility that the second wiring pattern will be damaged as shown in FIG.
±７、ごコンタクトホールＣ３ｕ’ｉｕ設した後、この
コンタクトホールを含め又レジスト、ｉｔ、、’ｓ−〇
上に補助余輩（汐１）．え；よｐ、ｌ’）膜艶を付設す
る。この補助金底膜υじ、はその膜厚が；ｒ・ｊ間絶縁
股Ｃ３０＋の膜厚の半分程度になる迄デボジノ言ンする
（第１図Ｃ）。次いでレジス）ｊｌＱＨＵ上の補助金属
膜■及びレジスト膜（社）を１ぺ去する（第１図ｄ）。±7, After forming the contact hole C3u'iu, add the auxiliary extra (shio 1) on the resist, it,,'s-〇, including this contact hole. E; yo p, l') Add a film gloss. This auxiliary bottom film υ is debossed until its film thickness becomes about half the film thickness of the insulating leg C30+ between r and j (FIG. 1C). Next, the auxiliary metal film (1) and the resist film (1) on the resist (resist) jlQHU are removed (FIG. 1d).
その後、コンタクトホールｃｎ＋ｆ−含み層間絶縁膜ω
上にＡＩ！よりなる第２配腺パターン句を付設し、第１
、第２配線パターン＋２ＣＩ川をコンタクトホール６Ｄ
ヲ介して接続するようにしている（第１図ｅ）。コンタ
クトホールは第１配線パターンから若干ずれて開設され
工いるがこのコンタクトホール内に補助金属膜を付設し
ているのでこの補助金属膜と層間絶縁膜の段差が小さく
なり、そのためこれらの上に配設される第２配線パター
ンが断線してしまうおれれがない。After that, the interlayer insulating film ω including the contact hole cn+f−
AI on top! The second gland pattern phrase consisting of
, 2nd wiring pattern + 2CI river to contact hole 6D
(Fig. 1e). The contact hole is formed with a slight deviation from the first wiring pattern, but since the auxiliary metal film is provided inside this contact hole, the difference in level between the auxiliary metal film and the interlayer insulating film is small, so that There is no risk of disconnection of the second wiring pattern provided.
（ト）発明の効果
本発明は半導体基板上の第１配線パターンと、層間絶縁
膜に設ける第２配線パターンとの接続を、該層間絶縁膜
のコンタクトホール内に付設した補助金属膜を中継して
行なうようにしているので、層間絶縁膜と補助金属膜と
の段差を小さくすることができ第２配線パターンの断線
を防止することができる。又、この断線を防止するため
に第１砲乙線パターンに巾広部分を設ける必要がないの
で第１配線パターンの配線ピッチを小さくしておくこと
ができ高集積化に都合が良い。(G) Effects of the Invention The present invention connects a first wiring pattern on a semiconductor substrate and a second wiring pattern provided in an interlayer insulating film by relaying an auxiliary metal film provided in a contact hole of the interlayer insulating film. This makes it possible to reduce the difference in level between the interlayer insulating film and the auxiliary metal film, thereby preventing disconnection of the second wiring pattern. Further, since it is not necessary to provide a wide portion in the first wiring pattern to prevent this disconnection, the wiring pitch of the first wiring pattern can be kept small, which is convenient for high integration.
第１図ａ、ｂ、ｃ、ｄ、ｅに本発明方法の工程説明図、
第２図は従来装置の第１配線パターンの平面図、第６図
は従来装置の部分断面因である。Fig. 1 a, b, c, d, e are process explanatory diagrams of the method of the present invention,
FIG. 2 is a plan view of the first wiring pattern of the conventional device, and FIG. 6 is a partial cross-sectional view of the conventional device.
Claims (1)
第１配線パターンを含め前記表面上に層間絶縁膜を設け
る工程と、前記層間絶縁膜上にレジスト膜を形成しこの
レジスト膜の前記第１配線パターンの一部上に選択的に
コンタクトホールを形成するための穴を形成する工程と
、この穴を用いて前記層間絶縁膜上に選択的にコンタク
トホールを形成する工程と、前記コンタクトホール内に
膜厚が前記層間絶縁膜の膜厚より小さい補助金属膜を付
設する工程と、この補助金属膜上を含め前記層間絶縁膜
上に第２配線パターンを形成する工程とを備える半導体
装置の製造方法。(1) A step of providing a first wiring pattern on the surface of a semiconductor substrate and providing an interlayer insulating film on the surface including the first wiring pattern, forming a resist film on the interlayer insulating film, and forming the first wiring pattern on the surface of the semiconductor substrate. a step of forming a hole for selectively forming a contact hole on a part of one wiring pattern; a step of using the hole to selectively form a contact hole on the interlayer insulating film; and a step of forming a contact hole selectively on the interlayer insulating film. A semiconductor device comprising the steps of providing an auxiliary metal film having a thickness smaller than the interlayer insulating film within the semiconductor device, and forming a second wiring pattern on the interlayer insulating film including on the auxiliary metal film. Production method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21700784A JPS6195555A (en) | 1984-10-16 | 1984-10-16 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21700784A JPS6195555A (en) | 1984-10-16 | 1984-10-16 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6195555A true JPS6195555A (en) | 1986-05-14 |
Family
ID=16697358
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21700784A Pending JPS6195555A (en) | 1984-10-16 | 1984-10-16 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6195555A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005277418A (en) * | 2004-03-19 | 2005-10-06 | Samsung Electronics Co Ltd | Thin film transistor indicating panel and manufacturing method of same |
| JP2006069144A (en) * | 2004-09-06 | 2006-03-16 | Riso Kagaku Corp | Stencil printing apparatus |
-
1984
- 1984-10-16 JP JP21700784A patent/JPS6195555A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005277418A (en) * | 2004-03-19 | 2005-10-06 | Samsung Electronics Co Ltd | Thin film transistor indicating panel and manufacturing method of same |
| JP2006069144A (en) * | 2004-09-06 | 2006-03-16 | Riso Kagaku Corp | Stencil printing apparatus |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS62502646A (en) | How to create tapered via holes in polyimide | |
| JPS6195555A (en) | Manufacture of semiconductor device | |
| JPS62118543A (en) | Semiconductor integrated circuit device | |
| JPS5886746A (en) | Semiconductor device | |
| JPS62247549A (en) | Manufacture of semiconductor device | |
| JPH01241117A (en) | Alignment-mark | |
| JPS60192348A (en) | Method for forming multilayer wiring of semiconductor integrated circuit | |
| JPS62155537A (en) | Manufacture of semiconductor device | |
| JPH0254563A (en) | Semiconductor device | |
| JPH0340449A (en) | Semiconductor device provided with integrated circuit | |
| JPS5921043A (en) | Manufacture of semiconductor device | |
| JPH02113566A (en) | Semiconductor integrated circuit | |
| JPS58122750A (en) | Preparation of semiconductor device | |
| JPS559415A (en) | Semiconductor manufacturing method | |
| TW202142517A (en) | Substrate combining structure, substrate combining system and substrate combining method | |
| JPH04101447A (en) | Manufacture of multilayer interconnection semiconductor integrated circuit | |
| JPH0222844A (en) | Semiconductor integrated circuit | |
| JPS6057648A (en) | Formation of metallic wiring pattern | |
| JPS54158183A (en) | Manufacture of semiconductor device | |
| JPH079933B2 (en) | Method for manufacturing semiconductor device | |
| JPS60261132A (en) | Manufacture of semiconductor device | |
| JPS58168241A (en) | Manufacture of integrated circuit device of thin film structure | |
| JPS61208851A (en) | Manufacture of semiconductor device | |
| JPS5955038A (en) | Formation of multilayer wiring | |
| JPS62150853A (en) | Formation of wiring pattern |