JPS6190259U - - Google Patents

Info

Publication number
JPS6190259U
JPS6190259U JP17436184U JP17436184U JPS6190259U JP S6190259 U JPS6190259 U JP S6190259U JP 17436184 U JP17436184 U JP 17436184U JP 17436184 U JP17436184 U JP 17436184U JP S6190259 U JPS6190259 U JP S6190259U
Authority
JP
Japan
Prior art keywords
field effect
effect transistor
gate electrode
gaas
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17436184U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP17436184U priority Critical patent/JPS6190259U/ja
Publication of JPS6190259U publication Critical patent/JPS6190259U/ja
Pending legal-status Critical Current

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  • Junction Field-Effect Transistors (AREA)
  • Logic Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の1実施例を説明するための回
路図、第2図は第1図に示した回路の等価回路図
、第3図は従来の半導体装置の回路図、第4図は
第3図に示した回路の等価回路図である。 1,2,5…ダイオード、3,4…FET、C
in…入力容量、11,12,15…シヨツトキ
ダイオード、13,14,16…MESFET。
Fig. 1 is a circuit diagram for explaining one embodiment of the present invention, Fig. 2 is an equivalent circuit diagram of the circuit shown in Fig. 1, Fig. 3 is a circuit diagram of a conventional semiconductor device, and Fig. 4 is a circuit diagram for explaining an embodiment of the present invention. 4 is an equivalent circuit diagram of the circuit shown in FIG. 3. FIG. 1, 2, 5...Diode, 3, 4...FET, C
in ...Input capacitance, 11, 12, 15...Shotki diode, 13, 14, 16...MESFET.

Claims (1)

【実用新案登録請求の範囲】 (1) 信号入力端子と、GaAs基板に形成された電
界効果トランジスタを含む論理回路と、前記信号
入力端子と前記電界効果トランジスタのゲート電
極との間に接続された1個若しくは複数個の順方
向整流特性素子と、前記ゲート電極と接地部との
間に接続された抵抗Rの素子とを備えてなるGaAs
半導体装置において、 前記素子の抵抗Rは、前記電界効果トランジス
タの必要動作速度及び容量をそれぞれf,Cとす
るとき、 R<1f・C を満足してなることを特徴とするGaAs半導体装置
。 (2) 前記抵抗Rの素子がゲート電極をソース電
極に接続したデプレツシヨン型の電界効果トラン
ジスタであることを特徴とする実用新案登録請求
の範囲第1項記載のGaAs半導体装置。
[Claims for Utility Model Registration] (1) A signal input terminal, a logic circuit including a field effect transistor formed on a GaAs substrate, and a logic circuit connected between the signal input terminal and the gate electrode of the field effect transistor. GaAs comprising one or more forward rectifying elements and an element having a resistance R connected between the gate electrode and the grounding part.
A GaAs semiconductor device, wherein the resistance R of the element satisfies R<1f·C, where f and C are the required operating speed and capacity of the field effect transistor, respectively. (2) The GaAs semiconductor device according to claim 1, wherein the element of the resistor R is a depletion type field effect transistor having a gate electrode connected to a source electrode.
JP17436184U 1984-11-19 1984-11-19 Pending JPS6190259U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17436184U JPS6190259U (en) 1984-11-19 1984-11-19

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17436184U JPS6190259U (en) 1984-11-19 1984-11-19

Publications (1)

Publication Number Publication Date
JPS6190259U true JPS6190259U (en) 1986-06-12

Family

ID=30731983

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17436184U Pending JPS6190259U (en) 1984-11-19 1984-11-19

Country Status (1)

Country Link
JP (1) JPS6190259U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5646340A (en) * 1979-09-22 1981-04-27 Nippon Telegr & Teleph Corp <Ntt> Logic circuit using schottky or p-n junction gate type field effect transistor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5646340A (en) * 1979-09-22 1981-04-27 Nippon Telegr & Teleph Corp <Ntt> Logic circuit using schottky or p-n junction gate type field effect transistor

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