JPS6188557A - Thin-film transistor matrix array - Google Patents
Thin-film transistor matrix arrayInfo
- Publication number
- JPS6188557A JPS6188557A JP20999584A JP20999584A JPS6188557A JP S6188557 A JPS6188557 A JP S6188557A JP 20999584 A JP20999584 A JP 20999584A JP 20999584 A JP20999584 A JP 20999584A JP S6188557 A JPS6188557 A JP S6188557A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- patterns
- lines
- film transistor
- matrix array
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 15
- 239000011159 matrix material Substances 0.000 title claims abstract description 14
- 239000010408 film Substances 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 2
- 239000000758 substrate Substances 0.000 abstract description 9
- 230000015556 catabolic process Effects 0.000 abstract description 6
- 239000011521 glass Substances 0.000 abstract description 6
- 238000005520 cutting process Methods 0.000 abstract description 5
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 238000000034 method Methods 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 230000003068 static effect Effects 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229910018487 Ni—Cr Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136204—Arrangements to prevent high voltage or static electricity failures
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Nonlinear Science (AREA)
- Liquid Crystal (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、例えばパネル状の液晶表示装置を薄膜トラン
ジスタを用いて制御できる薄膜トランジスタマトリック
スアレイに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a thin film transistor matrix array that can control, for example, a panel-shaped liquid crystal display device using thin film transistors.
第７図は液晶表示用薄膜トランジスタマトリックスアレ
イの構成である（例えば特開昭５８−１７８５５３号公
報参照）。１はケートハス、２はデータバス、３は薄膜
トランジスタ、４は画素電極、５及び６は外部駆動回路
と接続される電極であり、これらは透明ガラス基板上に
形成されている。FIG. 7 shows the structure of a thin film transistor matrix array for liquid crystal display (see, for example, Japanese Patent Laid-Open No. 178553/1983). Reference numeral 1 indicates a cell phone, 2 a data bus, 3 a thin film transistor, 4 a pixel electrode, and 5 and 6 electrodes connected to an external drive circuit, which are formed on a transparent glass substrate.
このマトリックスアレイを液晶パネルにするため配向膜
（ポリイミド等）を塗布して配向処理（ラビング）を行
なわなければならないが、この処理に発生する静電気や
、人体からの静電気等により薄膜トランジスタのゲート
絶縁膜やゲートハスとデータバス間の絶縁膜間にかかる
高電圧に対する対策が望まれていた。In order to turn this matrix array into a liquid crystal panel, it is necessary to apply an alignment film (polyimide, etc.) and perform an alignment process (rubbing), but the static electricity generated during this process and from the human body can damage the gate insulating film of the thin film transistor. Countermeasures against the high voltage applied between the gate bus and the insulating film between the gate bus and the data bus have been desired.
本発明の目的は、上記の点に鑑み、マトリックスアレイ
の高電圧による絶縁破壊を防止することにある。In view of the above points, an object of the present invention is to prevent dielectric breakdown of a matrix array due to high voltage.
本発明は薄膜トランジスタマトリックスアレ１′におい
て、ゲートバス及びデータバスをあらかし７め接続して
同電位にしておき、所望のパネル完成後ゲートハス及び
データバスを電気的に分％ｉｉｌすることを特徴とする
。The present invention is characterized in that in the thin film transistor matrix array 1', the gate bus and the data bus are connected in advance and kept at the same potential, and after the desired panel is completed, the gate bus and the data bus are electrically separated. shall be.
本発明によれば、パネル完成まではすべてのゲートライ
ン及びデータラインが同電位であるため、電圧による絶
縁破壊に対する信頼性を向上させることができる。According to the present invention, since all gate lines and data lines are at the same potential until the panel is completed, reliability against dielectric breakdown due to voltage can be improved.
以下、本発明の実施例を図面を用いて説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第１．２．３図は第１実施例を示すもので、第１図は要
部概略模式図である。第１図において１−１．１−２、
・・・はゲートパターン、２−１．２−２、・・・デー
タパターン、３は薄膜トランジスタ、４は画素電極、５
−１．５−２、・・・及び６−１．６−２、・・・は外
部駆動回路と接続される重視、７は透明ガラス基板、８
．９は本発明の特徴部で各電極５−１．５−２、・・・
、及び６−１．６−２、・・・の間を接続して同電位と
するための相互接続ラインである。それによってすべて
のゲートパターン１−１．１＝２、・・・及びデータパ
ターン２−１．２−２、・・・が同電位となるため、電
圧による絶縁破壊に対する信頼性を向上させられる。1.2.3 shows the first embodiment, and FIG. 1 is a schematic diagram of the main parts. In Figure 1, 1-1.1-2,
... is a gate pattern, 2-1.2-2, ... data pattern, 3 is a thin film transistor, 4 is a pixel electrode, 5
-1.5-2, ... and 6-1.6-2, ... are important to be connected to an external drive circuit, 7 is a transparent glass substrate, 8
．． 9 is a characteristic part of the present invention, each electrode 5-1, 5-2,...
, and 6-1, 6-2, . . . to have the same potential. As a result, all the gate patterns 1-1.1=2, . . . and the data patterns 2-1.2-2, .
次に、上記構造の形成方法を第２．３図を用いて次に説
明する。Next, a method for forming the above structure will be explained below using FIG. 2.3.
まずガラス基板７上にＮｉ−Ｃｒ等の金属により第２図
のようなゲートパターン１−１．１−２、・・・を形成
する。各ゲートライン１−１．１−２、・・・は外部回
路との接続を行うための電極５−１．５−２、・・・で
もってすべてつながれているため、はぼ同電位である。First, gate patterns 1-1, 1-2, . . . as shown in FIG. 2 are formed on the glass substrate 7 using metal such as Ni-Cr. Each gate line 1-1, 1-2, . . . is connected by an electrode 5-1, 5-2, . . . for connection with an external circuit, so they are at approximately the same potential. .
次にゲート絶縁膜である窒化シリコン、続いて半導体層
である非晶質シリコンを基板全面にプラズマＣＶＤ法に
より連続的に成膜し、非晶質シリコンを符号１２の如く
所定の形状にエツチングする。次に符号１１の部分をコ
ンタクトホールとするため窒化シリコンをエツチングす
る。次にソース３Ｓ、ドレイン３ＤとなるＡｌやＮｉ−
Ｃｒ等の金属を蒸着し、第３図に示すような形状にエツ
チングする。Next, silicon nitride, which is a gate insulating film, and then amorphous silicon, which is a semiconductor layer, are successively formed on the entire surface of the substrate by plasma CVD, and the amorphous silicon is etched into a predetermined shape as shown in 12. . Next, the silicon nitride is etched to form a contact hole at a portion 11. Next, Al or Ni- becomes the source 3S and drain 3D.
A metal such as Cr is deposited and etched into the shape shown in FIG.
この状態においてゲートライン１−１．１−２、・・・
及びソースライン２−１．２−２、・・・は同様に、電
極５−１．５−２、・・・及び６−１．６−２、・・・
は全て相互接続ライン８．９によってつながれているた
め、はぼ同電位であり、またゲートライン１−１．１−
２、・・・とソースライン２−１．２−２、・・・は各
電極を介してコンタクトホール１１で接続されているた
め、結局すべてのゲートライン及びソースラインはほぼ
同電位となる。In this state, gate lines 1-1, 1-2,...
Similarly, the source lines 2-1.2-2, . . . have electrodes 5-1.5-2, . . . and 6-1.6-2, .
are all connected by the interconnection line 8.9, so they are at approximately the same potential, and the gate lines 1-1.1-
2, . . . and the source lines 2-1, 2-2, .
次に画素電極４となる透明電極（例えばＩＴＯ）をドレ
イン３Ｄに接続するような形状に形成する（図中にはな
い）。Next, a transparent electrode (for example, ITO) that will become the pixel electrode 4 is formed in a shape so as to be connected to the drain 3D (not shown in the figure).
このようなマトリックス基板を液晶ディスプレイとする
為に、配向膜（ポリイミド等）を塗布して配向処理（ラ
ビング）を行なわなければならないが、この処理時に発
生する静電気や、人体からの静電気により絶縁破壊を起
こすという問題があったが、本発明によれば、すべての
ゲート及びソースが同電位であるため絶縁破壊に対する
信頼性か向上する。In order to use such a matrix substrate as a liquid crystal display, it is necessary to apply an alignment film (polyimide, etc.) and perform an alignment process (rubbing), but the static electricity generated during this process and the static electricity from the human body can cause dielectric breakdown. However, according to the present invention, since all gates and sources are at the same potential, reliability against dielectric breakdown is improved.
配向処理及び液晶の注入後、切断線１０で切断すれば液
晶パネルが完成する。もちろん機械的に切断しなくても
、それぞれのゲート、ソースが分離するように選択的に
エツチングしてもよい。After alignment treatment and injection of liquid crystal, cutting along cutting lines 10 completes the liquid crystal panel. Of course, instead of mechanical cutting, selective etching may be performed so that the respective gates and sources are separated.
次に第２の実施例について説明する。第１の実施例では
ゲートおよびソースを接続するため、あらかじめ電極５
−１．５−２、・・・および電極６−１．６−２、・・
・の部分で接続したパターンを用いていたが、本実施例
では通常の製作方法によりアクティブマトリックス基板
を完成した後、配向処理をする前にソース、ドレイン部
に金属１２を被着形成するものである。Next, a second embodiment will be described. In the first embodiment, in order to connect the gate and source, the electrode 5
-1.5-2,... and electrode 6-1.6-2,...
In this example, after completing the active matrix substrate using a normal manufacturing method, the metal 12 was deposited on the source and drain portions before alignment treatment. be.
第４図のようにガラス基板上にマトリックスアレイが完
成した後、へβ等の金属１２を選択的に蒸着後、配向処
理をして液晶注入後、第１の実施例と同様に切断すれば
よい。After the matrix array is completed on the glass substrate as shown in FIG. 4, metal 12 such as β is selectively vapor-deposited, aligned, liquid crystal is injected, and then cut in the same manner as in the first embodiment. good.
次に第３の実施例について第５．６図を用いて説明する
。第１の実施例ではコンタクトホール１１をあける、第
２の実施例では金属１２を蒸着するというようにそれぞ
れ１工程増えるが、本実施例は従来と同じ工程数ででき
るものである。Next, a third embodiment will be described using FIG. 5.6. In the first embodiment, the contact hole 11 is formed, and in the second embodiment, the metal 12 is deposited, each of which requires one additional step, but this embodiment can be completed with the same number of steps as the conventional method.
第１の実施例と同様にゲートパターン形成（支、窒化シ
リコン、続いて非晶質シリコンを連続的に成膜し、非晶
質シリコンを選択的にエツチングした後、ソーストレイ
ン電極蒸着前に、ゲート電極のコンタクトホールとして
１３のように窒化シリコンをエソチンクスル。As in the first embodiment, after gate pattern formation (silicon nitride and then amorphous silicon are sequentially formed, and the amorphous silicon is selectively etched, before source train electrode deposition, As shown in 13, make silicon nitride a contact hole for the gate electrode.
次にソース、ドレイン電極となる金属を蒸着し第６図の
斜線の部分が残るようにエツチングする。Next, metal that will become the source and drain electrodes is deposited and etched so that the shaded areas in FIG. 6 remain.
このパターンならば、電極５−１．５−２、・・・は、
この金属で覆われている為エツチング液に腐食される心
配はない。その後は同様にパネル完成後切断すればよい
。With this pattern, the electrodes 5-1, 5-2,...
Since it is covered with this metal, there is no need to worry about it being corroded by the etching solution. After that, just cut it in the same way after the panel is completed.
以上述べたように本発明によれば、薄膜トランジスタマ
トリックスアレイにおいて、所望のパネル完成まではす
べてのゲートライン及びデータラインが同電位に設定さ
れるため、電圧ノイズ等による絶縁破壊に対する信頼性
を向上させることができる。As described above, according to the present invention, in a thin film transistor matrix array, all gate lines and data lines are set to the same potential until the desired panel is completed, thereby improving reliability against dielectric breakdown caused by voltage noise, etc. be able to.
第１図〜第３図は本発明の第１の実施例を示すもので、
第１図は概略模式図、第２．３図は形成過程を示す要部
平面図、第４図は第２の実施例を示す要部平面図、第５
．６図は第３の実施例を示す要部平面図、第７図は従来
より用いられてきた薄膜トランジスタのマトリックスア
レイを示す回路図である。
１−１．１−２・・・ゲートパターン、２−１．２−２
・・・データパターン、３・・・薄膜トランジスタ、４
・・・画素電極、５−１．５−２．及び６−Ｌ ６−
２・・・電極、７・・・ガラス基板、８，９・・・相互
接続ライン、１０・・−切断線。1 to 3 show a first embodiment of the present invention,
Fig. 1 is a schematic diagram, Fig. 2.3 is a plan view of the main part showing the forming process, Fig. 4 is a plan view of the main part showing the second embodiment, Fig. 5
．． FIG. 6 is a plan view of a main part showing the third embodiment, and FIG. 7 is a circuit diagram showing a matrix array of thin film transistors that has been conventionally used. 1-1.1-2...Gate pattern, 2-1.2-2
...Data pattern, 3...Thin film transistor, 4
... Pixel electrode, 5-1.5-2. and 6-L 6-
2... Electrode, 7... Glass substrate, 8, 9... Interconnection line, 10... - Cutting line.
Claims (1)
タバス、ソース、ドレイン、素子駆動電極よりなる薄膜
トランジスタマトリックスアレイにおいて、ゲートバス
及びデータバスをあらかじめ接続して同電位にしておき
、パネル完成後ゲートバス及びデータバスを電気的に分
離することを特徴とする薄膜トランジスタマトリックス
アレイ。In a thin film transistor matrix array consisting of a gate bus, a gate, a gate insulating film, a semiconductor layer, a data bus, a source, a drain, and an element drive electrode, the gate bus and data bus are connected in advance to the same potential, and the gate bus is connected after the panel is completed. A thin film transistor matrix array characterized by electrically separating a data bus and a data bus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20999584A JPS6188557A (en) | 1984-10-05 | 1984-10-05 | Thin-film transistor matrix array |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20999584A JPS6188557A (en) | 1984-10-05 | 1984-10-05 | Thin-film transistor matrix array |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6188557A true JPS6188557A (en) | 1986-05-06 |
Family
ID=16582112
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20999584A Pending JPS6188557A (en) | 1984-10-05 | 1984-10-05 | Thin-film transistor matrix array |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6188557A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4803536A (en) * | 1986-10-24 | 1989-02-07 | Xerox Corporation | Electrostatic discharge protection network for large area transducer arrays |
| EP0376165A2 (en) * | 1988-12-21 | 1990-07-04 | Kabushiki Kaisha Toshiba | Method for manufacturing a liquid crystal display device |
| EP0423824A2 (en) * | 1989-10-20 | 1991-04-24 | Hosiden Corporation | Active matrix liquid crystal display element |
| US7183147B2 (en) | 2004-03-25 | 2007-02-27 | Semiconductor Energy Laboratory Co., Ltd. | Light emitting device, method for manufacturing thereof and electronic appliance |
-
1984
- 1984-10-05 JP JP20999584A patent/JPS6188557A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4803536A (en) * | 1986-10-24 | 1989-02-07 | Xerox Corporation | Electrostatic discharge protection network for large area transducer arrays |
| EP0376165A2 (en) * | 1988-12-21 | 1990-07-04 | Kabushiki Kaisha Toshiba | Method for manufacturing a liquid crystal display device |
| EP0423824A2 (en) * | 1989-10-20 | 1991-04-24 | Hosiden Corporation | Active matrix liquid crystal display element |
| US7183147B2 (en) | 2004-03-25 | 2007-02-27 | Semiconductor Energy Laboratory Co., Ltd. | Light emitting device, method for manufacturing thereof and electronic appliance |
| US7829894B2 (en) | 2004-03-25 | 2010-11-09 | Semiconductor Energy Laboratory Co., Ltd. | Light emitting device, method for manufacturing thereof and electronic appliance |
| US8198635B2 (en) | 2004-03-25 | 2012-06-12 | Semiconductor Energy Laboratory Co., Ltd. | Light emitting device, method for manufacturing thereof and electronic appliance |
| US8674369B2 (en) | 2004-03-25 | 2014-03-18 | Semiconductor Energy Laboratory Co., Ltd. | Light emitting device, method for manufacturing thereof and electronic appliance |
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