JPS6188551A - Detecting circuit for abnormal voltage - Google Patents

Detecting circuit for abnormal voltage

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Publication number
JPS6188551A
JPS6188551A JP21071884A JP21071884A JPS6188551A JP S6188551 A JPS6188551 A JP S6188551A JP 21071884 A JP21071884 A JP 21071884A JP 21071884 A JP21071884 A JP 21071884A JP S6188551 A JPS6188551 A JP S6188551A
Authority
JP
Japan
Prior art keywords
voltage
section
circuit
input
detecting circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21071884A
Other languages
Japanese (ja)
Inventor
Seiji Takano
高野 精治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP21071884A priority Critical patent/JPS6188551A/en
Publication of JPS6188551A publication Critical patent/JPS6188551A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To obtain an IC having high reliability by constituting an abnormal-voltage detecting circuit by a voltage comparison section, a reference voltage generating section for referring tolerance limits and a select circuit section and incorporating the detecting circuit into an IC with a plurality of power supplies. CONSTITUTION:An abnormal-voltage detecting circuit is constituted by a voltage comparison section 1 consisting of N voltage comparison circuits 1-1-1-N, a reference voltage generating section 2 for referring tolerance limits and a select circuit section 3, and the detecting circuit is incorporated into an IC. The detecting circuit is constituted in this manner, and internal generating voltage, abnormality thereof must be detected, is inputted to the voltage comparison circuits 1-1-1-N through an input section 40 to the circuits. N reference voltage V1-Vn for reference equally divided into (N-1) is generated between the VLR and VHR of a region containing previously determined tolerance minimum limit voltage VL and tolerance maximum limit voltage VH in the generating section 2, and the reference voltage is inputted to the comparison section 1. Where VLR and VHR represent set values determined in consideration of the dispersion of products. Outputs from the circuits 1-1-1-N are inputted to the circuit section 3 to which select control signals 50 are inputted, and alarms are generated according to the levels of outputs 60 from the circuit section 3.

Description

【発明の詳細な説明】 (技術分野) 本発明は異常電圧検出回路、とくに複数の電源を有する
集積回路中に組込まれた異常電圧検出回路に関する。
DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to an abnormal voltage detection circuit, and particularly to an abnormal voltage detection circuit incorporated in an integrated circuit having a plurality of power supplies.

(従来技術) 集積回路の中には、例えば5vおよび3.3Vといった
ような複数の電源電圧を内部で使用するものも数多く存
在する。このような場合、例えば5■電源の方は外部の
安定化回路をもつ電源が用いられ、これにともない、異
常電圧の検出もそこで確実に行なわれるのでとくに問題
はないが、3.3■の電源の方は、一般に集積回路の内
部に設けられた電源回路によって発生され、必要な部分
に直接分配されていて適切な監視を受けていない場合が
多い。
(Prior Art) Many integrated circuits use multiple power supply voltages, such as 5V and 3.3V, internally. In such a case, for example, a power supply with an external stabilization circuit is used for the 5.■ power supply, and abnormal voltage detection is also reliably performed there, so there is no particular problem, but 3.3. Power is generally generated by a power supply circuit located inside the integrated circuit, distributed directly to the parts where it is needed, and often without proper monitoring.

このため、この電圧が規格値を割り回路が非常にクリイ
ティカルな状態で動作していても、従来例においてはこ
れが検出されず、原因不明の誤動作等を生じ信頼性の低
下つながるという欠点がある。
For this reason, even if this voltage exceeds the standard value and the circuit is operating in a very critical state, this is not detected in the conventional example, resulting in unexplained malfunctions and the like, leading to a decrease in reliability.

(発明の目的) 本発明の目的は、複数の電源を有する集積回路中に、適
切な異常電圧検出回路を設けることによシ、上述の従来
の欠点を除去することにある。
OBJECTS OF THE INVENTION It is an object of the present invention to eliminate the above-mentioned conventional drawbacks by providing a suitable abnormal voltage detection circuit in an integrated circuit having multiple power supplies.

(発明の構成) 本発明の回路は、仮数の電源を有する集積回路において
、異常を検出すべき電源の許容限界電圧を包含する領域
を複数の出力電圧で分割して出力する複数の出力を有す
る許容限界参照用基準電圧発生手段と、第1の入力を前
記異常を検出すべき電源に接続し第2の入力を前記基準
電圧発生手段の前記仮数の出力の中の一つの出力に接続
し前記第1の入力のは王と前記第2の入力の電圧とを比
較して差を2値信号として出力する電圧比較回路を前記
基準電圧発生手段の前記出力に対応する数だけ具備した
電圧比較手段と、前記電圧比較手段の具備する複数の前
記電圧比較回路の出力から任意の出力を選択して出力す
る選択手段とを含む。
(Structure of the Invention) The circuit of the present invention is an integrated circuit having a mantissa power supply, and has a plurality of outputs that divide a region including the permissible limit voltage of the power supply in which an abnormality is to be detected into a plurality of output voltages. a reference voltage generating means for permissible limit reference; a first input connected to the power supply for which the abnormality is to be detected; a second input connected to one of the outputs of the mantissa of the reference voltage generating means; Voltage comparison means comprising a number of voltage comparison circuits that compare the voltage of the first input and the voltage of the second input and output the difference as a binary signal, the number of which corresponds to the output of the reference voltage generation means. and selection means for selecting and outputting an arbitrary output from the outputs of the plurality of voltage comparison circuits included in the voltage comparison means.

(実施例) 次に図面を参照して本発明の詳細な説明する。(Example) Next, the present invention will be described in detail with reference to the drawings.

第1図は本発明の一実施例を示すブロック図である。FIG. 1 is a block diagram showing one embodiment of the present invention.

本実施例は、N個の電圧比較回路1−1〜1−Nを具備
する電圧比較部1、許容限界参照用基準電圧発生部2お
よび選択回路部3を含んでいる。
The present embodiment includes a voltage comparison section 1 having N voltage comparison circuits 1-1 to 1-N, a reference voltage generation section 2 for permissible limit reference, and a selection circuit section 3.

上述の各部は、集積回路の中に組込まれた異常電圧検出
回路を構成するものであシ、異常を検出すべき、内部で
発生された電源電圧は、この検出回路の入力40に供給
される。
Each of the above-mentioned parts constitutes an abnormal voltage detection circuit built into an integrated circuit, and the internally generated power supply voltage to detect an abnormality is supplied to the input 40 of this detection circuit. .

異常を検出すべき電圧は入力40から、前記N個の各電
圧比較回路1−1〜1−Nの一方の入力に導かれる。
The voltage at which an abnormality should be detected is led from the input 40 to one input of each of the N voltage comparison circuits 1-1 to 1-N.

一方、許容限界参照用基準電圧発生部2は、第2図に示
すように、予め定められている許容最低限界電圧’VL
および許容最高限界電圧VHを含む領域の、VLRおよ
びVHRO間をほぼ(N−1)等分したN個の参照用基
準電圧V1.V2・・・VNを発生する。このVLRお
よびVHRt″ll:#品のバラつきを考慮して定めら
れた設計値である。実際の出力基準電圧!/1.  V
2.・・・YNの電圧値は、それぞれの製品によシ異な
るが、少くも必らずVl < ML  (VH(vNが
成立するように選定された値である。
On the other hand, as shown in FIG.
and N reference standard voltages V1. and N reference voltages V1., which are approximately (N-1) equally divided between VLR and VHRO in the region including the maximum allowable limit voltage VH. V2...Generates VN. This VLR and VHRt''ll: #These are design values determined in consideration of product variations.Actual output reference voltage!/1.V
2. ...The voltage value of YN varies depending on each product, but it is a value selected so that Vl < ML (VH(vN) holds true.

このN個の各基準電圧Vl、  V2・・・VNはそれ
ぞれ、前述の電圧比較回路1−1.〜1−Hの他方の入
力に供給される。さて、各電圧比較回路1−1〜1−N
は、一方の入力から供給された異常を検出すべき電源電
圧(これを以後Vとする)と。
These N reference voltages Vl, V2...VN are respectively applied to the voltage comparison circuits 1-1. ~1-H is supplied to the other input. Now, each voltage comparison circuit 1-1 to 1-N
is the power supply voltage (hereinafter referred to as V) at which an abnormality should be detected, which is supplied from one input.

他方の入力から供給された基準電圧とを比較する。Compare with the reference voltage supplied from the other input.

例えば第2番目の電圧比・改回路1−2は、供給されだ
Vとv2とを比較して、V)Y2の場合には論理レベル
”IIIを出力し、vくv2の場合には論理レベルIf
 OI+を出力する。
For example, the second voltage ratio/change circuit 1-2 compares the supplied V and v2, and outputs a logic level "III" if V)Y2, and a logic level "III" if V<v2. Level If
Output OI+.

電圧比較回路1−1〜1−Hの各出力は、N個の入力を
有する選択回路部3の各入力に導かれる。
Each output of the voltage comparison circuits 1-1 to 1-H is guided to each input of the selection circuit section 3 having N inputs.

選択回路部3は、外部から供給される選択制御信号入力
50からの選択制御信号によって、前述のN個の電圧比
較回路1−1〜1−Hの中の一つの出力を選択して出力
60に出力する。
The selection circuit unit 3 selects one output from the aforementioned N voltage comparison circuits 1-1 to 1-H according to a selection control signal from a selection control signal input 50 supplied from the outside, and outputs the selected output 60. Output to.

さて、異常を検出すべき入力型EEvが、予め定めた許
容最低限界電圧MLを下まわった場合に、出力60にア
ラームを出すようにするために、本実施例は以下のよう
に動作させる。
Now, in order to output an alarm to the output 60 when the input type EEv for which an abnormality is to be detected falls below the predetermined minimum allowable limit voltage ML, the present embodiment operates as follows.

今ある特定の製品について、 V+−1< ’/L< Vl の関係が成立していたとする。すなわち、第1番目の基
準電圧vIは許容最低限界電圧MLよシも高いが、それ
よりも一つ低い第i−1番目の基準電圧v+−IV′L
許容最低限界電圧MLよシも低くなるような第1番目の
基準電圧v1 を見出し、選択回路部3がこの第1番目
の電圧比較回路1− iの出力を選ぶように前述の選択
制御信号入力5oからの選択制御信号を設定する。
Assume that for a specific product, the following relationship holds: V+-1<'/L<Vl. In other words, the first reference voltage vI is higher than the minimum allowable limit voltage ML, but the i-1st reference voltage v+-IV′L is one level lower than the minimum allowable limit voltage ML.
A first reference voltage v1 that is also lower than the allowable minimum limit voltage ML is found, and the aforementioned selection control signal is input so that the selection circuit section 3 selects the output of this first voltage comparison circuit 1-i. Set the selection control signal from 5o.

この結果、出力60が′11を出力していると、入力電
圧Vは確実に最低限界電圧MLを上まわっていることが
保証されることになる。すなわち、出力60からの論理
レベルll0nをもって、入力電圧Vが許容最低限界電
圧vLを下まわる可能性のあるアラームとして用いるこ
とができることになる。
As a result, when the output 60 outputs '11', it is guaranteed that the input voltage V reliably exceeds the lowest limit voltage ML. That is, the logic level ll0n from the output 60 can be used as an alarm indicating that the input voltage V may fall below the allowable minimum limit voltage vL.

なお、以上の説明においては、入力電圧Vが許容最低限
界電圧”/Lを下まわる点を問題としたが、入力電圧V
が許容最高限界電圧VHを上まわる点を問題にする場合
には以下のようにすればよい。
In the above explanation, the problem was that the input voltage V was lower than the allowable minimum limit voltage "/L," but the input voltage V
If the problem is that VH exceeds the maximum allowable limit voltage VH, the following can be done.

すなわち、ある特定の製品について、 V 1+1.> VH>V j になるような、第1番目の基準出力を見出し、選択回路
部3がこの第j番目の電圧比較回路1−jの出力を選ぶ
ように、前述の選択制御信号入力50からの選択制御信
号を設定する。
That is, for a particular product, V 1+1. > VH > V j , and selects the output from the selection control signal input 50 so that the selection circuit section 3 selects the output of the j-th voltage comparison circuit 1-j. Set the selection control signal.

こうすると、出力60がII Onを出力していると、
入力電圧Vは確実に許容最高限界電圧VHを下まわって
いることが保証される。すなわち出力60からの論理レ
ベルII I IIをもって、入力電圧Vが許容最高限
界電圧VHを上まわる可能性のあるアラームとして用い
ることができることになる。
In this way, if output 60 is outputting II On,
It is ensured that the input voltage V is below the maximum allowable limit voltage VH. That is, the logic level II II II from the output 60 can be used as an alarm that the input voltage V may exceed the maximum allowable limit voltage VH.

また、入力電圧Vが許容最低限界電圧ML と許容最高
限界電圧VHとの間にあることを保証するような検出回
路とするためには、第3図に示すようにすればよい。
Further, in order to provide a detection circuit that guarantees that the input voltage V is between the minimum allowable limit voltage ML and the maximum allowable limit voltage VH, the arrangement shown in FIG. 3 may be used.

すなわち、前述の許容限界参照用基準電圧発生部2に対
して、前述と同じN個の電圧比較回路を含む最低限界用
電圧比較部ILとこの各電圧比較回路のN個の出力の中
の一つを選択する前述と同様な最低限界用選択回路部3
Lと、上述と同じようなN個の電圧比較回路を含む最高
限界用電圧比較部IHと、この各電圧比較回路のN個の
出力の中の一つを選択する前述と同様な最高限界用選択
回路部3Hと、前記選択回路部3Hの出力側に挿入され
たインバータ4と、前記選択回路部3Lの出力と、前記
インバータ4の出力との論理積をとるアンドゲート5と
を設ける。
That is, for the above-mentioned allowable limit reference reference voltage generation section 2, the lowest limit voltage comparison section IL including the same N voltage comparison circuits as mentioned above and one of the N outputs of each voltage comparison circuit are used. The lowest limit selection circuit section 3 similar to the above-mentioned one selects the
L, a maximum limit voltage comparator IH including N voltage comparators similar to those described above, and a maximum limit voltage comparator IH similar to those described above that selects one of the N outputs of each voltage comparator circuit. A selection circuit section 3H, an inverter 4 inserted on the output side of the selection circuit section 3H, and an AND gate 5 that performs a logical product of the output of the selection circuit section 3L and the output of the inverter 4 are provided.

こうして、最低限界用選択回路部3Lに対する選択制御
信号人力50Lには、前述の許容最低限界電圧vLに対
する検出動作を行なわせる場合に説明したのと同様にし
て選択制御信号を設定する。
In this way, a selection control signal is set in the selection control signal 50L for the lowest limit selection circuit section 3L in the same manner as described in the case of performing the detection operation for the above-mentioned minimum allowable limit voltage vL.

また最高限界用選択回路3Hに対する選択制御信号人力
50Hには、前述の許容最高限界電圧VHに対する検出
動作を行なわせる場合に説明したのと同様にして選択制
御信号を設定する。
Further, the selection control signal 50H for the highest limit selection circuit 3H is set in the same manner as described above when performing the detection operation for the maximum allowable limit voltage VH.

このようにすると、アンドゲート5の出力80が論理レ
ベルIf I IIになっている状態では、入力電圧V
は、許容最低限界電圧VL、よシも高く許容最高限界電
圧VHよシも低い(つまりvL<vくVHである)こと
が確実に保証され、従って、出力80の論理レベルIt
 □ IIをもって、上述の状態が保証されなくなった
ことに対するアラームとして用いることができる。
In this way, when the output 80 of the AND gate 5 is at the logic level If I II, the input voltage V
is guaranteed to be higher than the lowest permissible limit voltage VL and lower than the highest permissible limit voltage VH (that is, vL<v<VH), and therefore the logic level It of the output 80 is
□ II can be used as an alarm that the above condition is no longer guaranteed.

以上のように本実施例によると、俵故の電源tE圧を使
用する集積回路中に含まれる比較的信頼性の低いこの集
積回路内部に設けられた電源回路の電圧の異常を検出す
るための砕実な手段を提供できる。とくに集積回路の中
に、比較の基準となるべき基準電圧をバラつきなく一様
に製造することは非常に困1・ILであるが、本実施例
においては、予め定めた範囲をカバーするような僅故の
基準電圧を発生するようにしておき、このいずれを実際
に用いるかは、何個の製品ができ上った後に1選択制御
信号の設定によりこれを決定するようにして以上の困難
を除去している。
As described above, according to the present embodiment, there is a method for detecting an abnormality in the voltage of the power supply circuit provided inside the relatively unreliable integrated circuit, which is included in an integrated circuit that uses the power supply voltage tE due to the electric current. We can provide you with a viable solution. In particular, it is very difficult to uniformly manufacture a reference voltage that is to be used as a reference for comparison in an integrated circuit without any variation, but in this example, a voltage that covers a predetermined range is used. It is much more difficult to generate a small reference voltage, and decide which one to actually use by setting the 1 selection control signal after the number of products has been completed. It is being removed.

なお、以上は本発明の一実施例を示したもので。Note that the above is an example of the present invention.

本発明は以上の実施例に限定されるものではない。The present invention is not limited to the above embodiments.

例えば以上の実施例においては、安全側をとって、確実
に許容限界電圧内にあることと、そうでないこととを区
別して表示させるようにしたために、アラームがでた場
合でも場合によってはまだわずかに許容限界電圧内に入
っている場合も生ずるが、このかわ9に、アラームが出
たら必らず限界電圧を越えているように設定することも
できる。
For example, in the above embodiment, to be on the safe side, the display clearly distinguishes between the voltage being within the permissible limit and the voltage not being within the allowable limit, so even if an alarm occurs, there may still be a slight Although there are cases where the voltage is within the permissible limit voltage, it is also possible to set the voltage limit so that the limit voltage is always exceeded when an alarm is generated.

この場合にはアラームが出なくてもわずかに限界電圧を
越える可能性が生ずることは明らかである。
In this case, it is clear that even if no alarm is issued, there is a slight possibility that the limit voltage will be exceeded.

また以上の説明においては比較回路を理想的なものとし
て説明したが実際の場合には、比較回路の特性も必要に
応じて考慮すべきことは明らかである。
Further, in the above description, the comparison circuit has been described as an ideal one, but in an actual case, it is clear that the characteristics of the comparison circuit should be considered as necessary.

また選択制(財)信号は集積回路の外部から供給するよ
うにしてもよいが、内部に設けたF ROM等金利用し
て製造後これに書込み設定するようにすることもできる
Further, the selection signal may be supplied from outside the integrated circuit, but it is also possible to write the selection signal into an internally provided FROM memory or the like and write the setting after manufacture.

(発明の効果) 以上述べたように本発明を用いると、複数の電源電圧を
内部で使用する集積回路中に設けられた内部電源回路の
電圧の異常を確実に検出するための適切な手段を提供で
きる。これによってこの種集積回路の信頼性向上を達成
できる。
(Effects of the Invention) As described above, by using the present invention, an appropriate means for reliably detecting an abnormality in the voltage of an internal power supply circuit provided in an integrated circuit that internally uses a plurality of power supply voltages is provided. Can be provided. This makes it possible to improve the reliability of this type of integrated circuit.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示すブロック図、第2図は
前記実施例の許容限界参照用基準電圧発生部の出力電圧
を説明するための図および第3図は本発明の他の実施例
を示すブロック図である。 図において、1・・・・・・電圧比較部、1−1〜1−
N・・・・・・電圧比鮫回路、2・・・・・・許容限界
参照用基準電圧発生部、3・・・・・・選択回路部、I
L・・・・・・最低限界用電圧比較部、IH・・・・・
・最高限界用電圧比較部、3L・・・・・・最低限界用
選択回路部、  3H・・・・・・最高限界用選択回路
部、4・・・・・・インバータ、5・・・・・・アンド
ゲート。 ン ぷ10
FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a diagram for explaining the output voltage of the reference voltage generator for permissible limit reference of the embodiment, and FIG. 3 is a block diagram showing another embodiment of the present invention. It is a block diagram showing an example. In the figure, 1... Voltage comparator, 1-1 to 1-
N...Voltage ratio shark circuit, 2... Reference voltage generation section for reference to allowable limits, 3... Selection circuit section, I
L: Voltage comparison section for lowest limit, IH:
・Highest limit voltage comparison section, 3L: Lowest limit selection circuit section, 3H: Highest limit selection circuit section, 4: Inverter, 5: ...and gate. 10

Claims (1)

【特許請求の範囲】[Claims]  複数の電源を有する集積回路において、異常を検出す
べき電源の許容限界電圧を包含する領域を複数の出力電
圧で分割して出力する複数の出力を有する許容限界参照
用基準電圧発生手段と、第1の入力を前記異常を検出す
べき電源に接続し第2の入力を前記基準電圧発生手段の
前記複数の出力の中の一つの出力に接続し前記第1の入
力の電圧と前記第2の入力の電圧とを比較して差を2値
信号として出力する電圧比較回路を前記基準電圧発生手
段の前記出力に対応する数だけ具備した電圧比較手段と
、前記電圧比較手段の具備する複数の前記電圧比較回路
の出力から任意の出力を選択して出力する選択手段とを
含むことを特徴とする異常電圧検出回路。
In an integrated circuit having a plurality of power supplies, a reference voltage generating means for reference to a tolerable limit has a plurality of output voltages that divides a region including the tolerable limit voltage of a power source in which an abnormality is to be detected into a plurality of output voltages, and outputs the divided output voltages; A first input is connected to the power supply where the abnormality is to be detected, and a second input is connected to one of the plurality of outputs of the reference voltage generating means, so that the voltage of the first input and the second input are connected. Voltage comparison means includes a number of voltage comparison circuits corresponding to the outputs of the reference voltage generation means, which compare the voltages of the input and output the difference as a binary signal; An abnormal voltage detection circuit comprising: selection means for selecting and outputting an arbitrary output from the outputs of the voltage comparison circuit.
JP21071884A 1984-10-08 1984-10-08 Detecting circuit for abnormal voltage Pending JPS6188551A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21071884A JPS6188551A (en) 1984-10-08 1984-10-08 Detecting circuit for abnormal voltage

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21071884A JPS6188551A (en) 1984-10-08 1984-10-08 Detecting circuit for abnormal voltage

Publications (1)

Publication Number Publication Date
JPS6188551A true JPS6188551A (en) 1986-05-06

Family

ID=16593947

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21071884A Pending JPS6188551A (en) 1984-10-08 1984-10-08 Detecting circuit for abnormal voltage

Country Status (1)

Country Link
JP (1) JPS6188551A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009245496A (en) * 2008-03-31 2009-10-22 Renesas Technology Corp Semiconductor integrated circuit device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009245496A (en) * 2008-03-31 2009-10-22 Renesas Technology Corp Semiconductor integrated circuit device

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