JPS6184048A - Integrated circuit device - Google Patents
Integrated circuit deviceInfo
- Publication number
- JPS6184048A JPS6184048A JP20654284A JP20654284A JPS6184048A JP S6184048 A JPS6184048 A JP S6184048A JP 20654284 A JP20654284 A JP 20654284A JP 20654284 A JP20654284 A JP 20654284A JP S6184048 A JPS6184048 A JP S6184048A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- electrode
- capacity
- potential
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 239000004065 semiconductor Substances 0.000 claims description 26
- 230000003071 parasitic effect Effects 0.000 abstract description 28
- 238000000034 method Methods 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 27
- 239000003990 capacitor Substances 0.000 description 9
- 230000000694 effects Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 230000006641 stabilisation Effects 0.000 description 2
- 238000011105 stabilization Methods 0.000 description 2
- 241000255789 Bombyx mori Species 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 208000021267 infertility disease Diseases 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0805—Capacitors only
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は集積回路装置に関し、特に容量素子を含む集積
回路装置に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an integrated circuit device, and particularly to an integrated circuit device including a capacitive element.
（従来の技術）
従来より、集積回路装置には、電位安定化の九めに容量
素子が広く用いら几ている。こ九には、ＰＮ接合を逆バ
イアス状態で用いる接合容量形のものと、チップ面上に
２ＮｆＩＶＣ積上げた電極の間に薄い絶縁膜を挾み込ん
だものとがあり、更にチップ面上の占積効率を良くする
ために、前記のものを複合し九タイプのものも用いられ
ている。これらの容量素子は、一般に、その電極部に寄
生容量を伴う。(Prior Art) Conventionally, capacitive elements have been widely used in integrated circuit devices for potential stabilization. There are two types of these devices: a junction capacitor type that uses a PN junction in a reverse bias state, and a type that has a thin insulating film sandwiched between electrodes stacked with 2NfIVC on the chip surface. In order to improve the product efficiency, nine types of composites of the above are also used. These capacitive elements generally have parasitic capacitance in their electrode portions.
第７図（ａ） 、 （ｂｌは半導体装置の容量素子の一
例の模式的断面図及びその等価回路図である。FIG. 7(a), (bl is a schematic cross-sectional view of an example of a capacitive element of a semiconductor device and its equivalent circuit diagram.
Ｐ型半導体基板１１ｃＮ型埋込み層２．Ｎ型領域３、Ｐ
型分離層４．Ｐ型領域５．Ｎ型領域６．絶縁膜７．端子
９，１０．１１を設けたとき、図示するように、端子９
，１０間で並列接続する接合容量Ｃ１，Ｃ２が得られ、
端子１０と端子１１との間には接合容量Ｃ３が得られる
、接合容量Ｃ３が寄生容量である。P-type semiconductor substrate 11cN-type buried layer 2. N-type region 3, P
Mold separation layer 4. P-type region5. N-type region6. Insulating film 7. When terminals 9, 10 and 11 are provided, as shown in the figure, terminal 9
, 10 are connected in parallel, junction capacitances C1 and C2 are obtained,
Junction capacitance C3 is obtained between terminal 10 and terminal 11, and junction capacitance C3 is a parasitic capacitance.
通常、基板には、そのチップの回路の最低電位が与えら
几、従って寄生容量Ｃ３は、最低電位との間に形成され
る容量である。従って、回路上、最低電位との間に容量
を挿入したい時は、端子９゜１１を最低電位とし、端子
１０との間の容ｔｉｔ利用すルば、容ｔｃ１１ｃ２．Ｃ
３の並列接続になるので、面積効率の良い容量素子が得
られる。そして、従来より、電位安定化のために用いら
れてきた容量素子では、前述の如く容量素子に寄生する
容量Ｃｚｆ並列に加えることによって面積効率を良くし
てきている。Usually, the lowest potential of the circuit of the chip is applied to the substrate, so the parasitic capacitance C3 is the capacitance formed between the substrate and the lowest potential. Therefore, if you want to insert a capacitor between the lowest potential in the circuit, set the terminal 9.11 to the lowest potential and use the capacitance between the terminal 10 and the capacitor tc11c2. C
Since 3 are connected in parallel, a capacitive element with good area efficiency can be obtained. In a capacitive element conventionally used for potential stabilization, area efficiency has been improved by adding a parasitic capacitance Czf to the capacitive element in parallel as described above.
しかしながら、−万では、寄生容量Ｃ３が付加すること
が逆に好ましくない場合もある。例えば、第８図に示す
Ｔ２Ｌ回路では、工〈知られているように、容ｔＣ＜ｆ
スピードアンプコンデンサトシて用いるが、この場合、
寄生容量Ｃ５は、入力容量と等価であり、動作速度を遅
くする方向に作用し、まに寄生容量Ｃ６は、出力トラン
ジスタＱ１のベース電位ｖ１の電位変化を妨げ、こ几も
また動作速度を遅くする。However, at -10,000, it may not be desirable to add the parasitic capacitance C3. For example, in the T2L circuit shown in FIG. 8, the capacitance tC<f
A speed amplifier capacitor is used, but in this case,
The parasitic capacitance C5 is equivalent to the input capacitance and acts to slow down the operating speed, while the parasitic capacitance C6 prevents the change in the base potential v1 of the output transistor Q1, which also slows down the operating speed. do.
これら動作速［１−遅くする方向に作用する寄生容量の
大きさは、トラ／ラスタ等に伴われる寄生容量値に比し
て十分に小さければもとより大した問題はなく、従来の
、消費電力が犬きく、従って駆動イ／ピーダ／スが小さ
いＴＬ回路に於ては特に入力容量と等価である寄生容＠
Ｃ５をさほど問題にはしなかった。The size of the parasitic capacitance that acts in the direction of slowing down these operating speeds is not a big problem as long as it is sufficiently small compared to the parasitic capacitance value associated with track/raster, etc., and conventional power consumption Parasitic capacitance, which is equivalent to the input capacitance, is especially important in TL circuits where the driving impedance is small and therefore the driving impedance is small.
I didn't have much of a problem with C5.
（発明が解決しようとする問題点）
しかし、トラ／２スタ等の素子の小形化による低電力、
高速化に伴い、スピードアップコ／デ／すの容量値をさ
ほど犬きくしなくてもスピードアップの効果が得らｎる
工うになる反面、寄生容量を相応に小さく抑えないと、
低電力化されているために駆動インビーダノスが高く、
その効果が得ら九ないという問題が起る。(Problems to be solved by the invention) However, the reduction in power consumption due to the miniaturization of elements such as transformers/two stars, etc.
As speed increases, the speed-up effect can be obtained without increasing the capacitance of the speed-up CO/D/S too much, but on the other hand, unless the parasitic capacitance is kept small,
Drive efficiency is high due to low power consumption,
The problem arises that the effect is not obtained.
本発明の目的は、上記欠点を除去し、寄生容量が小さい
容量素子を有する集積回路装置を提供することにある。An object of the present invention is to eliminate the above drawbacks and provide an integrated circuit device having a capacitive element with small parasitic capacitance.
（問題点を解決するための手段〉
本発明の集積回路装置は、−導電型半導体基板に少くと
も一つの反対導電型領域を設けて形成される容量素子を
有する集積回路装置において、前記容量素子の電極対の
少くとも一方の電極と前記半導体基板との間に、導電系
の接続による電位が印加されない領域が配置されている
ことを特徴として構成嘔れる。(Means for Solving the Problems) An integrated circuit device of the present invention has a capacitive element formed by providing at least one region of an opposite conductivity type on a -conductivity type semiconductor substrate. The structure is characterized in that a region to which no potential is applied due to connection of a conductive system is arranged between at least one electrode of the electrode pair and the semiconductor substrate.
（実施例） 次に、本発明の実施例について図面を用いて説明する。(Example) Next, embodiments of the present invention will be described using the drawings.
第１図は本発明の第１の実施例の模式的断面図である。FIG. 1 is a schematic cross-sectional view of a first embodiment of the present invention.
Ｐ型半導体基板１にＮ型領域３．Ｐ型分離層４゜Ｐ型領
域５．Ｎ型領域６．絶縁膜７．上層の電極８を設ける。An N-type region 3. is formed on a P-type semiconductor substrate 1. P-type separation layer 4° P-type region 5. N-type region6. Insulating film 7. An upper layer electrode 8 is provided.
Ｎ型領域６と電極８との間の絶縁膜１３によって容量Ｃ
９を形成する。Ｎ型領域６は電極１２に引出される。こ
の時、外部から強制的に電位が加えられていないＰ型領
域５とＮ型領域３、及び回路上の最低電位が与えられる
Ｐ型半導体基板１の存在によＩＩ）、Ｎ型領域６とＰ型
領域５との間に空乏層による容量Ｃ８が形成され、また
Ｎ型領域３とＰ型半導体基板１との間にも空乏層による
容量Ｃ７が形成され、こ几らはＮ型領域３とＰ型半導体
基板１との間に直列に形成さルるのでその間の容量値、
すなわち電極１２と回路上の最低電位間に寄生する容量
値を低減することができる。尚、Ｐ型半導体基板１と電
極１２との間に電圧が印加された時のＰ型領域５及びＮ
型領域３の電位は、印加電圧の容量分割によって定まる
が、その容１ｃ７．ｅ１１の値は″１友印加電圧に依存
する空乏層の大きさによって決まるので当該電圧値を求
めるのは一般に複雑である。また、Ｐ型領域５とＮ型領
域３との間にはＰＮ接合ダイオードＤが形成されており
、両領域の電位差に依存するイノビーダンスで相互に導
通している。The capacitance C is increased by the insulating film 13 between the N-type region 6 and the electrode 8.
form 9. N-type region 6 is drawn out to electrode 12 . At this time, due to the existence of the P-type region 5 and the N-type region 3 to which no potential is forcibly applied from the outside, and the P-type semiconductor substrate 1 to which the lowest potential on the circuit is applied, the N-type region 6 and A capacitance C8 due to a depletion layer is formed between the N-type region 5 and the P-type semiconductor substrate 1, and a capacitance C7 due to a depletion layer is also formed between the N-type region 3 and the P-type semiconductor substrate 1. and the P-type semiconductor substrate 1, so the capacitance value between them is
That is, the parasitic capacitance value between the electrode 12 and the lowest potential on the circuit can be reduced. Note that when a voltage is applied between the P-type semiconductor substrate 1 and the electrode 12, the P-type region 5 and the N
The potential of the mold region 3 is determined by capacitance division of the applied voltage, and the capacitance 1c7. Since the value of e11 is determined by the size of the depletion layer which depends on the applied voltage, it is generally complicated to determine the voltage value.Furthermore, there is a PN junction between the P-type region 5 and the N-type region 3. A diode D is formed and conducts with each other with an innovidance depending on the potential difference between the two regions.
第２図は本発明の第２の実施例の模式的断面図である。FIG. 2 is a schematic cross-sectional view of a second embodiment of the invention.
第２の実施例は、電極８の上に絶縁膜１４を設けて容量
媒体とし、その上に電極１５を設けて、電極８と電極１
５との間に容量Ｃ１Ｏを形成したものである。その他は
第１の実施例とほぼ同じである。In the second embodiment, an insulating film 14 is provided on the electrode 8 to serve as a capacitive medium, an electrode 15 is provided on the insulating film 14, and the electrode 8 and the electrode 1
A capacitor C1O is formed between the capacitor 5 and the capacitor C1O. The rest is almost the same as the first embodiment.
この第２の実施例において、電極８とＰ型半導体基板１
との間の寄生容量は、接合容量Ｃ７，Ｃ［１と、絶縁膜
７が形成する容量Ｃ９との直列接続によって低減される
。In this second embodiment, the electrode 8 and the P-type semiconductor substrate 1
The parasitic capacitance between the two is reduced by the series connection of the junction capacitance C7, C[1 and the capacitance C9 formed by the insulating film 7.
第３図は本発明の第３の実施例の模式的断面図である。FIG. 3 is a schematic cross-sectional view of a third embodiment of the present invention.
この実施例は、第１の実施例におけるＮ型領域６とＰ型
領域５とを持たない構造である。容量Ｃ９と０７とが直
列接続されるので電極１２と半導体基板ｌとの間の寄生
容量は低減逼れる。上記第２゜第３の実施例の両方にお
いて、Ｎ型領域３，６゜Ｐ型領域５は外部から強制的に
電位が加えられていない領域であることは言うまでもな
い。尚、第２図の第２の実施例のダイオードＤは第１図
のダイオードＤで説明したのと同様である。This embodiment has a structure that does not have the N-type region 6 and P-type region 5 in the first embodiment. Since the capacitors C9 and 07 are connected in series, the parasitic capacitance between the electrode 12 and the semiconductor substrate l is reduced. It goes without saying that in both of the second and third embodiments, the N-type regions 3, 6 and P-type regions 5 are regions to which no potential is forcibly applied from the outside. Note that the diode D in the second embodiment shown in FIG. 2 is the same as that described for the diode D in FIG. 1.
第４図は本発明の第４の実施例の模式的断面図である。FIG. 4 is a schematic cross-sectional view of a fourth embodiment of the present invention.
この実施例は、アイソプレーナ構造の場合を示すもので
、電極２６と電極２８との間の絶縁膜２７を容量媒体と
して容ｆｌｃ１ｓを形成し、電極２６は電極２９に引出
される。この構造において、絶縁膜２５は第１図、第２
図に示した絶縁膜１３，７エりも通常厚く、従って同郷
が形成する寄生容量成分０１４はかなり不妊い。このた
めその下のＮ型領域２２及びＰ型半導体基板２１との間
に形成される接合容ｔ０１３との直列接続で決まる、電
極２９とＰ型半導体基板２１との間の寄生容量は、大幅
に小さくすることができる。尚、この実施例に於てもＮ
型領域２２は、外部から強制的に電位が加えらｎでおら
ず、まｔ同領域はその両側に示すＮ型領域２４と同一工
程で形成されるものである。This embodiment shows the case of an isoplanar structure, in which a capacitance flc1s is formed using an insulating film 27 between an electrode 26 and an electrode 28 as a capacitance medium, and the electrode 26 is led out to an electrode 29. In this structure, the insulating film 25 is
The insulating films 13 and 7 shown in the figure are also usually thick, and therefore the parasitic capacitance component 014 formed by the same layer is quite infertile. Therefore, the parasitic capacitance between the electrode 29 and the P-type semiconductor substrate 21, which is determined by the series connection with the junction capacitance t013 formed between the N-type region 22 and the P-type semiconductor substrate 21 below, is significantly reduced. Can be made smaller. Furthermore, in this example, N
The type region 22 is not forcibly applied with an external potential, and is formed in the same process as the N type regions 24 shown on both sides thereof.
更に、上述した如く絶縁膜２５は厚いので、特にＮ型領
域２２を省き、同領域がＰ型半導体基板２１そのもので
あっても電極２９とＰ型半導体基板２１との間の寄生容
量削減効果は大きい。Furthermore, since the insulating film 25 is thick as described above, even if the N-type region 22 is omitted and the same region is the P-type semiconductor substrate 21 itself, the effect of reducing the parasitic capacitance between the electrode 29 and the P-type semiconductor substrate 21 is big.
第５図は本発明の第５の実施例の模式的断面図である。FIG. 5 is a schematic cross-sectional view of a fifth embodiment of the present invention.
この実施例は、第４図の絶縁膜２５とほぼ同等の厚さの
絶縁膜４５ｔ−有するものであるが、絶縁膜４５の形成
方法が異なっており、またＮ型領域４２はエピタキシャ
ル層であり、それに隣接するＮ型領域４４はＮ型領域４
２エリも高７塁度のＮ型不純物を有する領域である。そ
れ以外の本発明に係わる本質的な機能は第４図のものと
同等である。This embodiment has an insulating film 45t- which is approximately the same thickness as the insulating film 25 in FIG. 4, but the method of forming the insulating film 45 is different, and the N-type region 42 is an epitaxial layer. , the N-type region 44 adjacent thereto is the N-type region 4
The second area is also a region containing N-type impurities with a high degree of 7th base. Other essential functions of the present invention are the same as those in FIG. 4.
すなわち第５図の４１．４６，４７，４８．４９は、そ
れぞｎそ几から２０を引いた第４図の２１゜２６．２７
，２８．２９に対応し、第４図の実施例と同様、電極４
９とＰ型半導体基板４１間に形成される寄生８Ｗ’ｒを
大幅に小さくすることができる。In other words, 41.46, 47, and 48.49 in Figure 5 are 21°26.27 in Figure 4, which is obtained by subtracting 20 from the n solution.
, 28, 29, and similar to the embodiment of FIG. 4, the electrode 4
The parasitic 8W'r formed between the P-type semiconductor substrate 9 and the P-type semiconductor substrate 41 can be significantly reduced.
尚、以上の第２図〜第５図に於て説明した、外部から強
制的１ｃ電位が加えられない領域の電位は、いづ扛も詳
生容惜として作用するとき、その寄生容量両端の電圧の
容量分割にて定まることは言うまでもない。Furthermore, as explained in Figures 2 to 5 above, the potential in the area where the forced 1C potential is not applied from the outside is the voltage across the parasitic capacitance when the capacitance acts as a capacitance. Needless to say, it is determined by the capacity division.
さて、以上では、本発明による容ｌを形成する′ｒ１１
ｍの一端と対半導体基板間に形成される寄生容度低減効
果を諸実流側で述べてキ友が、本発明のもう一つの特徴
は、もう−万〇省極とその上層配線との間に形成される
寄生容量削減のための方法を同時に提供することである
。すなわち多層配線で形成される集積回路テップに於て
、第１図の電極８，１２．第２図の電極１５，１２．第
４図の電極２８，２９．第５図の電極４８．４９の上部
に、当該電極と同電位でない配線を設置しないか、又は
設置する場合、当該各電極の上層配線層のうち、１層を
隔てｆｃ２層目以上の配線層にてそれを行うことにより
、上層配線との間に形成さｎる寄生容量を低減すること
ができる。Now, in the above, 'r11 forming the volume l according to the present invention
Another feature of the present invention is the reduction in parasitic capacitance formed between one end of the semiconductor substrate and the semiconductor substrate. Another object of the present invention is to simultaneously provide a method for reducing parasitic capacitance formed between the two. That is, in an integrated circuit chip formed of multilayer wiring, the electrodes 8, 12 . Electrodes 15, 12 in FIG. Electrodes 28, 29 in FIG. Above the electrodes 48 and 49 in Fig. 5, do not install wiring that does not have the same potential as the electrode, or if it is installed, the fc second or higher wiring layer is separated by one layer among the upper wiring layers of each electrode. By doing so, it is possible to reduce the parasitic capacitance formed between the upper layer wiring and the upper layer wiring.
第６図は本発明の第６の実施例の模式的断面図である。FIG. 6 is a schematic cross-sectional view of a sixth embodiment of the present invention.
この実施例は第４図に示す第４の実施例の構造に上述の
寄生容量低減の構造を加えたものである。This embodiment is obtained by adding the above-described parasitic capacitance reduction structure to the structure of the fourth embodiment shown in FIG.
電極２８′を電極２８と同一層に同じ材料で形成し、そ
の上に絶縁膜３５を形成する。絶縁膜３５に開孔を設け
て、上層第１層目配線３６ｆ！：設け、電極２８．２８
’と接続する。更に、その上に絶縁膜３７を設けて開孔
し、上層第２層目配線３８゜３８′を形成する。配線３
８′は上層第１層目配線３６と接続する。−万、配線３
８は、容量を形成する電極２８の上部’に！い、従って
、そｎらの間に寄生容量Ｃ１６が伴わルるが、同容歇の
媒体は層間絶縁膜３５．及び３７の２層！Ｓ造になって
おり、従って蚕生容黴Ｃ１６を小ぜく抑えている。同媒
体部絶縁膜層が、更に上層間絶縁膜ｔ？積むことで厚く
なれば更にそれだけ寄生容量が不埒くなることは明白で
あり、又、上層第２層目配線３８゜あるいは更にその上
層の配線が電極２８．２９上を覆っていなければ、実質
的に容量Ｃ１６が消滅することも明らかである。The electrode 28' is formed in the same layer and of the same material as the electrode 28, and the insulating film 35 is formed thereon. An opening is provided in the insulating film 35, and the upper first layer wiring 36f! : Provided, electrode 28.28
Connect with '. Furthermore, an insulating film 37 is provided thereon and holes are formed to form upper second layer interconnections 38° and 38'. Wiring 3
8' is connected to the upper first layer wiring 36. - 10,000, wiring 3
8 is at the top of the electrode 28 that forms the capacitor! Therefore, a parasitic capacitance C16 is involved between them, but the same medium has an interlayer insulating film 35. And 37 2 layers! It is made of S construction, which suppresses silkworm C16 mold. The same medium part insulating film layer is further provided with an upper interlayer insulating film t? It is obvious that the parasitic capacitance becomes worse as the thickness increases due to stacking, and if the upper layer second layer wiring 38° or the wiring further above it does not cover the electrodes 28 and 29, It is also clear that the capacitance C16 disappears.
（発明の効果）
以上説明したように、本発明によれば、寄生容量の小路
い容量素子が得られ、集積回路に於て従来以上に容量素
子の適用範囲を広めることができる効果が得らｎる。(Effects of the Invention) As explained above, according to the present invention, a capacitive element with a small parasitic capacitance can be obtained, and the range of application of capacitive elements in integrated circuits can be expanded more than ever before. nru.
第１図乃至第６図は本発明の第１乃至第６の実施例の模
式的断面図、第７図（ａ） 、 ｆｂ）は従来の半導体
装置の容量素子の一例の模式的断面図及びその等価回路
図、第８図は従来のＴＬ 回路の一例の回路図である。
１・・・・・・Ｐ型半導体基板、２・・・・・・Ｎ型埋
込み層、３・・・・・・Ｎ型領域、４・・・・・・Ｐ型
分離層、５・・・・・・Ｐ型領域へ ６・・・・・・Ｎ
型領域、７・・・・・・絶縁膜、８・・・・・・電極、
９，１０．１１・・・・・・端子、１２・・・・・・電
極、１３゜１４・・・・・・絶縁膜、１５・・・・・・
電極、２１・・・・・・Ｐ型半導体基板、２２・・・・
・・Ｎ型領域、２４・・・・・・Ｎ型領域、２５・・・
・・・絶縁膜、２６・・・・・・電極、２７・・・・・
・絶縁膜、２８．２８’ 、２９・・・・・・電極、
３５．３６・・・・・・上層第１層目配線、３７・・・
・・・絶縁膜、３８．３８’・・・・・・上層第２層目
配線、４１・・・・・・Ｐ型半導体基板、４２・・・・
・・Ｎ型領域、４４・・・・・・Ｎ型領域、４５・・・
・・・絶縁膜、４６・・・・・・電極、４７・・・・・
・絶縁膜、４８゜４９・・・・・・電極、０１〜Ｃ１６
・・・・・・容量、Ｄ・・・・・・ダイオード。
第１図
竿ｚＴｉｆ
年３田
￥４図
栢左旧
卆 ２ 列1 to 6 are schematic sectional views of first to sixth embodiments of the present invention, and FIGS. 7(a) and 7(fb) are schematic sectional views of an example of a capacitive element of a conventional semiconductor device. Its equivalent circuit diagram, FIG. 8, is a circuit diagram of an example of a conventional TL circuit. DESCRIPTION OF SYMBOLS 1... P-type semiconductor substrate, 2... N-type buried layer, 3... N-type region, 4... P-type isolation layer, 5... ...to P-type region 6...N
mold region, 7... insulating film, 8... electrode,
9,10.11...terminal, 12...electrode, 13°14...insulating film, 15...
Electrode, 21... P-type semiconductor substrate, 22...
...N-type region, 24...N-type region, 25...
...Insulating film, 26...Electrode, 27...
・Insulating film, 28.28', 29... Electrode,
35.36... Upper layer first layer wiring, 37...
... Insulating film, 38.38' ... Upper second layer wiring, 41 ... P-type semiconductor substrate, 42 ...
...N-type region, 44...N-type region, 45...
...Insulating film, 46...Electrode, 47...
・Insulating film, 48°49... Electrode, 01~C16
...Capacity, D...Diode. Figure 1 Rod zTif Year 3 fields ¥ 4 Figure left old book 2 rows
Claims (2)
領域を設けて形成される容量素子を有する集積回路装置
において、前記容量素子の電極対の少くとも一方の電極
と前記半導体基板との間に、導電系の接続による電位が
印加されない領域が配置されていることを特徴とする集
積回路装置。(1) In an integrated circuit device having a capacitive element formed by providing at least one region of an opposite conductivity type on a semiconductor substrate of one conductivity type, at least one electrode of a pair of electrodes of the capacitive element and the semiconductor substrate An integrated circuit device characterized in that a region to which no potential is applied due to conductive connections is arranged in between.
線が存在しない特許請求の範囲第（１）項記載の集積回
路装置。(2) The integrated circuit device according to claim (1), in which there is no first layer wiring above the electrode of the capacitive element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20654284A JPS6184048A (en) | 1984-10-02 | 1984-10-02 | Integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20654284A JPS6184048A (en) | 1984-10-02 | 1984-10-02 | Integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6184048A true JPS6184048A (en) | 1986-04-28 |
Family
ID=16525101
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20654284A Pending JPS6184048A (en) | 1984-10-02 | 1984-10-02 | Integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6184048A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7557428B2 (en) | 2005-01-18 | 2009-07-07 | Kawasaki Microelectronics, Inc. | Semiconductor integrated circuit having a reduced parasitic capacitance and short start-up time |
| CN101866919A (en) * | 2009-04-15 | 2010-10-20 | 中国台湾积体电路制造股份有限公司 | Integrated circuit structure |
| JP2013546237A (en) * | 2010-10-15 | 2013-12-26 | ザイリンクス インコーポレイテッド | Tunable resonant circuit in integrated circuits |
-
1984
- 1984-10-02 JP JP20654284A patent/JPS6184048A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7557428B2 (en) | 2005-01-18 | 2009-07-07 | Kawasaki Microelectronics, Inc. | Semiconductor integrated circuit having a reduced parasitic capacitance and short start-up time |
| CN101866919A (en) * | 2009-04-15 | 2010-10-20 | 中国台湾积体电路制造股份有限公司 | Integrated circuit structure |
| JP2013546237A (en) * | 2010-10-15 | 2013-12-26 | ザイリンクス インコーポレイテッド | Tunable resonant circuit in integrated circuits |
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