JPS618354U - Direct memory access device - Google Patents
Direct memory access deviceInfo
- Publication number
- JPS618354U JPS618354U JP9151184U JP9151184U JPS618354U JP S618354 U JPS618354 U JP S618354U JP 9151184 U JP9151184 U JP 9151184U JP 9151184 U JP9151184 U JP 9151184U JP S618354 U JPS618354 U JP S618354U
- Authority
- JP
- Japan
- Prior art keywords
- dma
- memory access
- direct memory
- address bus
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Bus Control (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は本考案の一実施例を含むブロック図、第2図は
従来のダイレクトメモリアクセス装置を含むブ請ンク図
である。
図において、1・・・マイクロコンピュータ、2・・・
メモIJ(一般′用)、3・・・DMA制御器、4,4
1,42−・DMAメモリ、5・・・入出力装置、6・
・・アドレスバス、7・・・データパス、訃・・切替器
である。FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional direct memory access device. In the figure, 1... microcomputer, 2...
Memo IJ (for general use), 3...DMA controller, 4, 4
1,42--DMA memory, 5--input/output device, 6-
...address bus, 7...data path, and...switching device.
Claims (1)
リアクセス(DMA)に用いられる二系統のDMA用メ
モリと、前記マイクロコンピュータとアドレスバスおよ
びデータパスを介して接続されると共に入出力装置と直
接接続されかつこめマイクロコンピュータのDMA指令
に従って制御信号を出力するDMA制御手段と、前記制
御信号によって前pMA用メモリの接続系統を切替える
切替手段とを備え、この切替手蒔は、一方のDMA用メ
モリが前記アドレスバスおよびデータパスとそれぞれ接
続きれている時、他方のDMA用メモリがそのアドレス
バスとの接続系統を前記DMA制御手段と接続されかつ
そのデータパスとの接続系統を前記入出力装置と接続さ
れるように交互に切替えられることi特徴とするダイレ
クトメモリアクセス装置。Two systems of DMA memory used for direct memory access (DMA) based on instructions from the microcomputer; and a microcomputer connected to the microcomputer via an address bus and a data path, and directly connected to an input/output device. DMA control means for outputting a control signal in accordance with the DMA command, and switching means for switching the connection system of the previous pMA memory according to the control signal, and this switching means that one DMA memory is connected to the address bus and the data When each path is disconnected, the other DMA memory alternately connects its address bus to the DMA control means and its data path to the input/output device. A direct memory access device characterized in that it can be switched to
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9151184U JPS618354U (en) | 1984-06-19 | 1984-06-19 | Direct memory access device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9151184U JPS618354U (en) | 1984-06-19 | 1984-06-19 | Direct memory access device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS618354U true JPS618354U (en) | 1986-01-18 |
Family
ID=30647465
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9151184U Pending JPS618354U (en) | 1984-06-19 | 1984-06-19 | Direct memory access device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS618354U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62207944A (en) * | 1986-03-10 | 1987-09-12 | Agency Of Ind Science & Technol | Thermal conductivity measuring instrument |
-
1984
- 1984-06-19 JP JP9151184U patent/JPS618354U/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62207944A (en) * | 1986-03-10 | 1987-09-12 | Agency Of Ind Science & Technol | Thermal conductivity measuring instrument |
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