JPS6181147U - - Google Patents
Info
- Publication number
- JPS6181147U JPS6181147U JP1984166741U JP16674184U JPS6181147U JP S6181147 U JPS6181147 U JP S6181147U JP 1984166741 U JP1984166741 U JP 1984166741U JP 16674184 U JP16674184 U JP 16674184U JP S6181147 U JPS6181147 U JP S6181147U
- Authority
- JP
- Japan
- Prior art keywords
- electronic component
- electrodes
- insulating member
- main body
- open end
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 description 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
Landscapes
- Wire Bonding (AREA)
Description
第１図は電子部品の一例を示す側断面図、第２
図乃至第６図は第１図電子部品の製造方法を示す
側断面図、第７図及び第８図は本考案の他の実施
例を示す側断面図、第９図は従来の電子部品の一
例を示す側断面図、第１０図は第９図電子部品の
製造に用いられるリードフレームの斜視図である
。 ７……絶縁部材、７ａ，７ｂ……導電層、８…
…電子部品本体、８ａ，８ｂ……電極。
図乃至第６図は第１図電子部品の製造方法を示す
側断面図、第７図及び第８図は本考案の他の実施
例を示す側断面図、第９図は従来の電子部品の一
例を示す側断面図、第１０図は第９図電子部品の
製造に用いられるリードフレームの斜視図である
。 ７……絶縁部材、７ａ，７ｂ……導電層、８…
…電子部品本体、８ａ，８ｂ……電極。
Claims (1)
- 開口両端面に導電層を形成した筒状の絶縁部材
内に、両端に電極を有する電子部品本体を収容し
、絶縁部材の開口端と電子部品本体の電極とを電
気的に接続すると共に封止したことを特徴とする
電子部品。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984166741U JPS6181147U (ja) | 1984-10-31 | 1984-10-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984166741U JPS6181147U (ja) | 1984-10-31 | 1984-10-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6181147U true JPS6181147U (ja) | 1986-05-29 |
Family
ID=30724550
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1984166741U Pending JPS6181147U (ja) | 1984-10-31 | 1984-10-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6181147U (ja) |
-
1984
- 1984-10-31 JP JP1984166741U patent/JPS6181147U/ja active Pending