JPS6180813A - Thin film semiconductor element - Google Patents

Thin film semiconductor element

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Publication number
JPS6180813A
JPS6180813A JP59201705A JP20170584A JPS6180813A JP S6180813 A JPS6180813 A JP S6180813A JP 59201705 A JP59201705 A JP 59201705A JP 20170584 A JP20170584 A JP 20170584A JP S6180813 A JPS6180813 A JP S6180813A
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JP
Japan
Prior art keywords
region
semiconductor layer
thin film
subgrain
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59201705A
Other languages
Japanese (ja)
Inventor
Akio Mimura
三村　秋男
Michio Ogami
大上　三千男
Masayuki Obayashi
正幸 大林
Takaya Suzuki
誉也 鈴木
Masahiro Okamura
岡村　昌弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
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Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP59201705A priority Critical patent/JPS6180813A/en
Publication of JPS6180813A publication Critical patent/JPS6180813A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02433—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02609—Crystal orientation

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To obtain a thin film semiconductor element which does not contain a grain region nor a subgrain region which extremely affects the characteristics of the thin film semiconductor element by forming a region which does not contain grain nor subgrain in crystallization. CONSTITUTION:An insulation film 2 is formed on a semiconductor substrate 1 made of silicon and an aperture 12 is provided in the insulation film. A semiconductor layer 3 made of polycrystalline silicon is formed on the aperture and a protection film 4 is formed on the layer 3. A linear heater or a laser beam is used to crystallize the protection film. In this case, flow of heat after melting to cooling and caking is shown by an arrow C. That is, the insulation film 2 is not heat-conductive and the heat flows toward the aperture 12 and then to the semiconductor substrate 1. In this way, crystallization can be controlled by controlling the flow of heat. Since a region A is near the aperture 12 and the direction of crystallization is definite, the crystallization proceeds all alike and uniformly and the generating of a grain region or a subgrain region becomes difficult.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は、絶縁膜あるいは絶縁基板上で結晶化した半導
体層に形成した薄膜半導体素子に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a thin film semiconductor element formed on an insulating film or a semiconductor layer crystallized on an insulating substrate.

〔発明の背景〕[Background of the invention]

半導体素子の高集積化を目的とする三次元化。 Three-dimensionalization aims to increase the degree of integration of semiconductor devices.

耐放射線強化、液晶ディスプンイの製作等の観点から、
絶縁膜、めるいは、絶縁基板の上に半導体素子を形成す
る試みがなされている。この技術では、例えば、Ｓｉ１
ｉｃｏｎ　ｏｎ　Ｉｎ５ｕｌａｔｏｒ（３Ｑ　Ｉ　）が
使われる。３０Ｉを形成するには多くの方法が提案され
ているが、Ｖ−ザや電子線などのエネルギビームを使っ
て半導体ノーを結晶化する方法や、ストリップヒータを
使いゾーンメルティングする方法がとられている。ここ
で、まず、ゾーンメルティング方法にＬる８０Ｉの形成
方法を説明する。From the perspective of strengthening radiation resistance and manufacturing liquid crystal displays, etc.
Attempts have been made to form semiconductor elements on insulating films or insulating substrates. In this technology, for example, Si1
The icon on In5ulator (3Q I ) is used. Many methods have been proposed for forming 30I, including a method of crystallizing a semiconductor layer using an energy beam such as a V-zer or an electron beam, and a method of zone melting using a strip heater. ing. First, the method for forming 80I using the zone melting method will be explained.

第７図は、ゾーンメルティング法によるＳＯＩの結晶化
方法を示す、シリコンのような半導体基板１の上に、例
えば、ＳｉＯ２のような絶縁膜２を形成し、この上に半
導体層３として多結晶シリコン膜を形成する。これを保
護するために、Ｓｉ０ｇ膜からなる保護膜４を形成する
。こうした構造の基板の上を、高温に加熱した線状ヒー
タ５を走査して、半導体層３を熔融結晶イヒするう結晶
化を左から右に行なう場合、半導体層３のＡの部分は多
結晶の状態、ヒータ直下のＢの部分は熔融した状態、Ｃ
の領域は結晶化した状態となる。FIG. 7 shows a method of crystallizing SOI using a zone melting method, in which an insulating film 2 such as SiO2 is formed on a semiconductor substrate 1 such as silicon, and a multilayer semiconductor layer 3 is formed on this. Form a crystalline silicon film. In order to protect this, a protective film 4 made of a Si0g film is formed. When crystallizing the semiconductor layer 3 from left to right by scanning the linear heater 5 heated to a high temperature over the substrate with such a structure, the portion A of the semiconductor layer 3 is polycrystalline. , part B directly under the heater is in a molten state, and part C is in a molten state.
The region becomes a crystallized state.

ところで、この半導体層３の結晶性が、素子を形成する
うえで問題となる。By the way, the crystallinity of this semiconductor layer 3 poses a problem when forming an element.

第８図は半導体層３の表面の結晶欠陥の状態を示す。欠
陥は大別して二種類になる。大きな欠陥は粒界６であり
、これを境として結晶の方向が大きく変る大傾角粒界で
あり、転位を含む大きな結晶欠陥の集合体である。亜粒
界７は、それを境として結晶の方向がわずかに異なるの
みであり、転位の連なったものでおる。このような粒界
６や亜粒界７は、異常拡散の原因やキャリアの散乱の原
因となる。これらの粒界は熔融した半導体層が急激に冷
却されて固化するとき、その同化方向が不規則であるた
めに起こる。従って、漬品性を高めるには、後に述べる
ように結晶方向の改善が必要となる。FIG. 8 shows the state of crystal defects on the surface of the semiconductor layer 3. Defects can be roughly divided into two types. The large defect is the grain boundary 6, which is a large-angle grain boundary at which the direction of the crystal changes significantly, and is an aggregate of large crystal defects including dislocations. The sub-grain boundaries 7 are a series of dislocations, with only a slight difference in the direction of the crystals across the sub-grain boundaries. Such grain boundaries 6 and sub-grain boundaries 7 cause abnormal diffusion and scattering of carriers. These grain boundaries occur because the direction of assimilation is irregular when the molten semiconductor layer is rapidly cooled and solidified. Therefore, in order to improve pickling properties, it is necessary to improve the crystal orientation as described later.

ところで、このような粒界、亜粒界の存在する半導体層
に素子を形成する場合には特異な問題が発生する。By the way, when an element is formed in a semiconductor layer in which such grain boundaries and sub-grain boundaries exist, a unique problem occurs.

第９図は、亜粒界の方向と平行にＭＯＳＦＥＴのノース
・ドレインを形成した例を示す。半導体層３には亜粒界
７が走っている。ここにポリノリコンゲート８を形成し
て、接合９．９′を形成する。次に、コ／タクト窓１０
．１０’を開けて、電極１１．１１’を形成ｒるっこの
措造のＭＯＳＦＥＴにおいて、拡散で接合９．９′を形
成する際　亜粒界７に沿って不純物の異常拡散を起こす
。FIG. 9 shows an example in which the north drain of the MOSFET is formed parallel to the direction of the sub-grain boundary. A subgrain boundary 7 runs through the semiconductor layer 3 . A polyconverter gate 8 is formed here to form a junction 9.9'. Next, the Co/Tact window 10
．． 10' is opened to form electrodes 11 and 11'. In a MOSFET with a circular structure, abnormal diffusion of impurities occurs along the sub-grain boundary 7 when a junction 9.9' is formed by diffusion.

従って、正常な場合はチャンネル長りの素子となるが、
異常拡散が起こる場合は、実効的なチャンネル長はＬよ
υ短かくなる。従って、ソース・ドレイン耐圧の低下、
あるい（１、リーク電流の増加などの不都合が生じやす
い。たてし、キャリアは亜粒界７に沿って流れるため、
散乱され雄＜、比較的大きな移動度が得られるう従って
高速化には有利となる。Therefore, under normal conditions, it will be an element with a long channel, but
When abnormal diffusion occurs, the effective channel length becomes shorter by L. Therefore, the source/drain breakdown voltage decreases,
Or (1) Problems such as an increase in leakage current are likely to occur.Since carriers flow along the sub-grain boundaries 7,
If the particles are scattered, a relatively large mobility can be obtained, which is advantageous for speeding up.

第１０図は、亜粒界とソース・ドレインの方向が直角と
なるように素子を構成した例を示す。この場合、亜粒界
７に沿った異常拡散が起こったと　　　　　　１しても
、亜粒界７はソース・ドレインと直角に走っているため
、実効的なチャンネル長りが小さくなる程度は小さく、
ソース・ドレインの耐圧低下やリーク電流増加の現象は
見られなくなる、ただし、キャリアが亜粒界にぶつかり
易くなるため、移動度はやや小さくなる。FIG. 10 shows an example in which the device is configured such that the subgrain boundaries and the source/drain directions are perpendicular to each other. In this case, even if abnormal diffusion occurs along the sub-grain boundary 7, since the sub-grain boundary 7 runs perpendicular to the source/drain, the extent to which the effective channel length will be reduced is small.
Phenomena of a decrease in source/drain breakdown voltage and an increase in leakage current are no longer observed, but carriers collide with subgrain boundaries more easily, so mobility becomes slightly smaller.

第１１図は、ソース・ドレイン及び亜粒界の方向とノー
ス・ドレイン耐圧歩留りとの関係を示す。FIG. 11 shows the relationship between the direction of the source/drain and subgrain boundaries and the north drain breakdown voltage yield.

Ａは、ノース・ドレインの方向と亜粒界の方向が平行の
場合（第９図）を示すウチャン不ル長りが犬さくなるに
従い、歩留りの低下が著しくなる。A shows a case where the north drain direction and the subgrain boundary direction are parallel (FIG. 9). As the grain length becomes shorter, the yield decreases significantly.

Ｂは、ソース−ドレインの方向と亜粒界の方向が直角の
場合を示すっこの場合は、チャンネル長りが５〜１０μ
ｍで、わずかに歩留りが落ちる程度でおろう 以上述べたように、亜粒界の方向の取り扱いの仕方によ
って、素子の特性が著しく変ることになるう素子を微細
化する場合、すなわち、チャンネル長を短かくする場合
には、素子の歩留りを維持する意味から、ソース・ドレ
インの方向と亜粒界の方向を直角に形成することが不可
欠となる。このため、任意の方向の素子を得ることが不
可能で、素子間の配線の引きまわしなどにより、集積度
の低下となろう ｆた、ソース・ドレインの方向と粒界の方向を直角にな
るように形成しても亜粒界が能動領域（ノース・ドレイ
ン接合領域及びチャンネル領域）に含むため、異常拡散
による歩留り低下という問題が残り、また、亜粒界を含
むことから、キャリアの散乱が起こる可能性があり、動
作速度の点からも不利である。B shows the case where the source-drain direction and the subgrain boundary direction are perpendicular. In this case, the channel length is 5 to 10μ.
As mentioned above, the characteristics of the device will change significantly depending on how the direction of the sub-grain boundary is handled. In order to shorten the length, it is essential to form the source/drain direction and the subgrain boundary at right angles in order to maintain the yield of the device. For this reason, it is impossible to obtain elements with arbitrary orientations, and the degree of integration may decrease due to wiring between elements, etc., and the source/drain direction and the grain boundary direction are perpendicular to each other. Even if sub-grain boundaries are formed in the active region (north-drain junction region and channel region), there remains the problem of reduced yield due to abnormal diffusion. This is disadvantageous in terms of operating speed.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、薄膜半導体素子の特性に著しい影響を
及ばず、粒界又は亜粒界を含まぬ薄膜半導体素子を提供
することにある。An object of the present invention is to provide a thin film semiconductor device that does not significantly affect the characteristics of the thin film semiconductor device and does not contain grain boundaries or subgrain boundaries.

〔発明の概要〕[Summary of the invention]

本発明は、結晶化に際して、粒界又は亜粒界のない領域
を形成し、また、この領域に薄膜半導体素子を形成する
ことを特徴とする。The present invention is characterized in that a region without grain boundaries or sub-grain boundaries is formed during crystallization, and a thin film semiconductor element is formed in this region.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の詳細な説明す；１゜ まず、本発明を実現するた、◇の基本となる２粒界又は
亜粒界を含まない半４体層の形成方法について、第１図
を用いて説明する、ここでは半導体としてシリコンをσ
りにとり説明する。第１図（ａ）において、／リコ／よ
りなる半導体基板１に絶縁膜２を形成し、これに開口部
１２を設ける。この上に、多結晶シリコンである半導体
層３を形成し、この上に保護膜４を形成する。半導体層
１３は、第１図（ｂ）に示すように分割して２く。これ
を、図中の矢印で示した方向に結晶化させる。結晶化さ
せるには、第７図に示した線状ヒータやＶ−ザビーム等
を使用する。この時、熔融後冷却固化するときの熱の流
れは、第１図（ｂ）に示した矢印のようになる。すなわ
ち、絶縁膜２は熱伝導性が悪いため、熱は開口部１２に
向って流れ、ここから、半導体基板１に流れていく。こ
のように、熱の流れを制御してやることにより、結晶化
の状態を制御することができるっ第１図（ｂ）に示した
Ａの領域は、開口部１２に近く、熱の流れの方向が定ま
っており、結晶化の方向が定まっているため、結晶化が
そろって均一に進行し、亜粒界が発生し難くなる。従っ
て、第８図で示したように、亜粒界や粒界が多数発生す
ることはない。Ｂの領域では開口部１２から遠ざかり熱
の流れが緩やかとなるため、比較的過冷却の状態が発生
し易くなるため、結晶化が急激に起こシ易く、結晶比が
そろい雅しくなり亜粒界が発生し易くなる。The present invention will be described in detail below; 1゜First, in order to realize the present invention, the method for forming a semi-four-body layer that does not include two grain boundaries or sub-grain boundaries, which is the basis of ◇, will be explained using FIG. Here, silicon is used as a semiconductor with σ
Let me explain. In FIG. 1(a), an insulating film 2 is formed on a semiconductor substrate 1 made of /Rico/, and an opening 12 is provided therein. A semiconductor layer 3 made of polycrystalline silicon is formed on this, and a protective film 4 is formed on this. The semiconductor layer 13 is divided into two parts as shown in FIG. 1(b). This is crystallized in the direction shown by the arrow in the figure. For crystallization, a linear heater, V-the beam, or the like shown in FIG. 7 is used. At this time, the flow of heat during cooling and solidification after melting is as shown by the arrows in FIG. 1(b). That is, since the insulating film 2 has poor thermal conductivity, heat flows toward the opening 12 and from there to the semiconductor substrate 1. In this way, by controlling the flow of heat, the state of crystallization can be controlled.The region A shown in FIG. 1(b) is close to the opening 12, and the direction of the flow of heat is Since the direction of crystallization is fixed, crystallization progresses uniformly and subgrain boundaries are less likely to occur. Therefore, as shown in FIG. 8, many sub-grain boundaries and grain boundaries do not occur. In region B, the flow of heat becomes slower as it moves away from the opening 12, making it relatively easy for a state of supercooling to occur. Therefore, crystallization tends to occur rapidly, and the crystal ratio becomes uniform and elegant, resulting in subgrain boundaries. is more likely to occur.

ところで、開口部１２を設けることにより、半導体／８
３が、単結晶の半導体基板１と接触していることによシ
、種結晶とすることができ、半導体基板１と同じ面方位
の半導体層３を形成することができる。例えば、半導体
基板ｌにＳｉの（１００）面を使うことにより、半導体
層３の結晶面も（１００）とすることができ、ＭＯＳ　
　ＦＥＴを作成するうえでは好適となろう 第３図は第１図で形成した半導体層における亜粒界７の
分布状況を示す。第１図で示したように、Ａの領域では
亜粒界７をほとんど無くすることができる。このような
溝造で、半導体基板の任意の　　　　　　　１位置に亜
粒界を含まない半導体層で設けることができる。By the way, by providing the opening 12, the semiconductor/8
Since 3 is in contact with the single crystal semiconductor substrate 1, it can be used as a seed crystal, and the semiconductor layer 3 having the same plane orientation as the semiconductor substrate 1 can be formed. For example, by using the (100) plane of Si for the semiconductor substrate l, the crystal plane of the semiconductor layer 3 can also be (100), and the MOS
FIG. 3 shows the distribution of sub-grain boundaries 7 in the semiconductor layer formed in FIG. 1, which will be suitable for manufacturing FETs. As shown in FIG. 1, subgrain boundaries 7 can be almost eliminated in the region A. With such a groove structure, a semiconductor layer containing no sub-grain boundaries can be provided at any one position on the semiconductor substrate.

次に、第６図において、具体的な素子の形成方法につい
て説明する。Next, referring to FIG. 6, a specific method of forming the element will be described.

第６図（ａ）では、第１図に示した方法で結晶化を行な
い、半導体層３のなかで、亜粒界がなく、半導体素子を
形成するのに必要な領域である半導体層３′の位置を決
定する。In FIG. 6(a), the semiconductor layer 3' is crystallized by the method shown in FIG. determine the position of

（ｂ）において、使用する半導体層３′以外の部分を除
去するか、あるいは、部分酸化にょシ酸化膜に変換する
。In (b), the portions other than the semiconductor layer 3' to be used are removed or converted into a partially oxidized oxide film.

（Ｃ）では、ポリ／リコ／ゲート８を形成してノース°
ドレイ／接合を形成する、半導体層３には亜粒界が含ま
れていないため、ソース・ドレインの方向は任意に選ぶ
ことができるうここでは、二拙急の方向について例示し
である。In (C), poly/lico/gate 8 is formed and the north
Since the semiconductor layer 3 forming the drain/junction does not contain subgrain boundaries, the direction of the source/drain can be arbitrarily selected. Here, two careless directions are illustrated.

（ｄ）で、ゲート電極８′２．ノース・ドレインの電極
１１，１１′を形成して、任意の方向のソース・ドレイ
／を持つ薄膜半導体素子が完成する。(d), the gate electrode 8'2. North and drain electrodes 11 and 11' are formed to complete a thin film semiconductor device having a source and a drain in an arbitrary direction.

本発明の薄膜半導体素子では、能動領域、すなわち、ソ
ース・ドレイン接合領域及びチャンネル領域には亜粒界
、あるいは、粒界が存在しないため、異常拡散によるソ
ース・ドレイン耐圧の低下や、リーク電流の増加が起こ
らない。また、亜粒界が存在しないため、キャリアの散
乱が起こらず、ＳＯＩ本来の特質である高速素子の実現
が可能となる。また、任意の方向にソース・ドレインを
形成できるため、回路設計の自由度が増し、集積度の高
い回路を実現できろう 第２図、第４図および第５図は本発明の異なる実施例を
示す。この例では、絶縁基板１３に半導体層３、保護膜
４が形成されているうこの上を線状ヒータ５を通過させ
ることＫより、第７図と同様に結晶化を行なうことがで
きる。半導体層３０Ａの部分は多結晶、Ｂの部分は熔融
層、Ｃの部分は結晶化層である。絶縁基板１３を使う場
合は、上部を加熱する方法以外に、下部から高温の腺状
領域で加熱することが可能である。In the thin film semiconductor device of the present invention, since there are no sub-grain boundaries or grain boundaries in the active region, that is, the source-drain junction region and the channel region, the source-drain breakdown voltage decreases due to abnormal diffusion and leakage current decreases. No increase occurs. Further, since there are no sub-grain boundaries, carrier scattering does not occur, making it possible to realize a high-speed device, which is an inherent characteristic of SOI. In addition, since the source and drain can be formed in any direction, the degree of freedom in circuit design increases and a circuit with a high degree of integration can be realized. Figures 2, 4, and 5 show different embodiments of the present invention. show. In this example, crystallization can be performed in the same manner as in FIG. 7 by passing the linear heater 5 over the insulating substrate 13 on which the semiconductor layer 3 and the protective film 4 are formed. A portion of the semiconductor layer 30A is polycrystalline, a portion B is a molten layer, and a portion C is a crystallized layer. When using the insulating substrate 13, instead of heating the upper part, it is also possible to heat the lower part using a high-temperature glandular region.

絶縁基板を使う場合は種結晶を使うことはできない。そ
こで何らかの方向で配向性を制御することが必要である
。When using an insulating substrate, seed crystals cannot be used. Therefore, it is necessary to control the orientation in some direction.

ｇ４図は半導体層３の整形方法を示す、ここでは、熱の
流れ方向を制御するため、半導体層３がくびれを持つよ
うに、分離溝１４を設ける。この分離溝１４を設けるこ
とにより、第１図と同様な熱の流れを作り出すことがで
き、結晶配向の制御も可能となり、はぼ（１００）面の
結晶が得られる。また、亜粒界を含まぬ領域の形成も可
能となる。Figure g4 shows a method for shaping the semiconductor layer 3. Here, in order to control the direction of heat flow, a separation groove 14 is provided so that the semiconductor layer 3 has a constriction. By providing this separation groove 14, it is possible to create a heat flow similar to that shown in FIG. 1, and it is also possible to control the crystal orientation, so that a crystal with a (100) plane can be obtained. Furthermore, it is also possible to form a region that does not include subgrain boundaries.

第５図は、以上の方法で形成した場合の半導体Ｉａ　３
における亜粒界の分布を示したもので、第３図と同様な
結果が得られることを示す。FIG. 5 shows the semiconductor Ia 3 formed by the above method.
This figure shows the distribution of subgrain boundaries in , and shows that the same results as in Figure 3 can be obtained.

素子を形成する過程は前例の第６図と同様である。The process of forming the element is the same as the previous example shown in FIG.

以上の実施例では薄膜半導体素子としてＭＯＳＦＥＴを
例にとりあげてきたが、バイポーラ素子も形成すること
ができ、同様な効果が得られる。In the above embodiments, a MOSFET has been taken as an example of a thin film semiconductor element, but a bipolar element can also be formed and similar effects can be obtained.

第１２図は本発明のさらに異なる実施例を示す。FIG. 12 shows yet another embodiment of the invention.

ここでは、粒径が数十μｍ以上に大きくなるよに形成し
、任意の位置の粒界あるいは亜粒界の内側に素子を形成
するものである。Here, the grain size is formed to be larger than several tens of micrometers, and the element is formed inside the grain boundary or sub-grain boundary at an arbitrary position.

第１２図（ａ）において、結晶化した後の半導体層３に
化学エツチング処理を施こし、亜粒界７の位置を蝕刻し
て明らかにする。こうして、亜粒界７がなく素子を形成
する半導体層３′の位置を決定する。以下は、第６図と
同様なプロセスで、素子を形成する。（ｂ）では半導体
層３′を加工する。能動領域以外に亜粒界７が含まれて
いても、特性に影響されることはない。（Ｃ）で、ポリ
シリコンゲート８を形成し、（ｄ）で、ノース脅ドレイ
ンの電極１１．１１’を形成して素子が完成する。In FIG. 12(a), the semiconductor layer 3 after crystallization is subjected to a chemical etching process, and the positions of the sub-grain boundaries 7 are etched and clarified. In this way, the position of the semiconductor layer 3', which has no sub-grain boundaries 7 and forms a device, is determined. The following process is similar to that shown in FIG. 6 to form elements. In (b), the semiconductor layer 3' is processed. Even if sub-grain boundaries 7 are included in areas other than the active region, the characteristics are not affected. In (C), the polysilicon gate 8 is formed, and in (d), the electrodes 11 and 11' of the north drain are formed, and the device is completed.

この実施例では薄膜半導体素子としてＭＯＳＦＥＴを例
示してきたが、バイポーラ素子の場合でも、同様な効果
が得られる。In this embodiment, a MOSFET has been exemplified as a thin film semiconductor element, but similar effects can be obtained even in the case of a bipolar element.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、薄膜半導体素子の能動領域に粒界、あ
るいは、亜粒界が存在しないため、異常拡散による接合
耐圧の低下やリーク電流の増大が起こらない。また、亜
粒界によるキャリアの散乱が起きないため、高速素子の
実現が可能であろっ　　　　　　　１また、任意の方向
に接合の位置を設けることかでき、回路形成の自由度が
増す。According to the present invention, since there are no grain boundaries or sub-grain boundaries in the active region of the thin film semiconductor element, a reduction in junction breakdown voltage and an increase in leakage current due to abnormal diffusion do not occur. In addition, since scattering of carriers due to subgrain boundaries does not occur, it is possible to realize high-speed devices.1 Also, the junction position can be provided in any direction, increasing the degree of freedom in circuit formation.

【図面の簡単な説明】[Brief explanation of the drawing]

１１図及び第２図はＳＯＩ本発明の一実施例の拾遺の基
板断面図、第３図、第４図及び第５図は本発明の半導体
層の平面図、第６図は本発明の薄膜半尋体素子形成過程
全示すための素子平面図、第７図は従来のＳＯＩ構造の
基板断面図、第８図は従来の半導体層の平面図、第９図
及び第ｉｏ図は従来の７ｔ５膜半導体素手の部分平面図
、第１１図は従来のチャンネル長と耐圧歩留りの関係図
、第・１２図は本発明の他の実施例の組立図である。 ｌ・・・半導体基板、２・・・絶縁ノ摸、３．３’・・
・半６体層、４・・保護膜、６・・・粒界、７・・・亜
粒界、９，９／・・・接合。11 and 2 are cross-sectional views of a substrate of an embodiment of the SOI invention, FIGS. 3, 4, and 5 are plan views of a semiconductor layer of the invention, and FIG. 6 is a thin film of the invention. 7 is a cross-sectional view of a substrate of a conventional SOI structure, FIG. 8 is a plan view of a conventional semiconductor layer, and FIG. 9 and IO are a plan view of a conventional SOI structure. FIG. 11 is a partial plan view of a bare film semiconductor; FIG. 11 is a diagram showing the relationship between the conventional channel length and breakdown voltage yield; and FIG. 12 is an assembly diagram of another embodiment of the present invention. l...Semiconductor substrate, 2...Insulation sample, 3.3'...
・Semi-6 body layer, 4...protective film, 6...grain boundary, 7...subgrain boundary, 9,9/...junction.

Claims (1)

【特許請求の範囲】 １、絶縁膜あるいは絶縁基板上で、エネルギビーム照射
、又は、加熱によつて結晶化された半導体層に形成され
た薄膜半導体素子において、 前記薄膜半導体素子の能動部分に、前記半導体層の粒界
又は亜粒界を含まないように構成したことを特徴とする
薄膜半導体素子。 ２、特許請求の範囲第１項において、前記絶縁膜がＳｉ
Ｏ＿２であり、前記絶縁基板が石英であり、前記半導体
層がＳｉであることを特徴とする薄膜半導体素子。[Scope of Claims] 1. In a thin film semiconductor element formed in a semiconductor layer crystallized by energy beam irradiation or heating on an insulating film or an insulating substrate, in an active part of the thin film semiconductor element, A thin film semiconductor device characterized in that the semiconductor layer is configured so as not to include grain boundaries or subgrain boundaries. 2. In claim 1, the insulating film is made of Si.
O_2, the insulating substrate is quartz, and the semiconductor layer is Si.
JP59201705A 1984-09-28 1984-09-28 Thin film semiconductor element Pending JPS6180813A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59201705A JPS6180813A (en) 1984-09-28 1984-09-28 Thin film semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59201705A JPS6180813A (en) 1984-09-28 1984-09-28 Thin film semiconductor element

Publications (1)

Publication Number Publication Date
JPS6180813A true JPS6180813A (en) 1986-04-24

Family

ID=16445552

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59201705A Pending JPS6180813A (en) 1984-09-28 1984-09-28 Thin film semiconductor element

Country Status (1)

Country Link
JP (1) JPS6180813A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005333150A (en) * 2005-06-13 2005-12-02 Hitachi Ltd Tft substrate and display device
US7834353B2 (en) 2001-10-10 2010-11-16 Hitachi Displays, Ltd. Method of manufacturing display device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7834353B2 (en) 2001-10-10 2010-11-16 Hitachi Displays, Ltd. Method of manufacturing display device
JP2005333150A (en) * 2005-06-13 2005-12-02 Hitachi Ltd Tft substrate and display device
JP4628879B2 (en) * 2005-06-13 2011-02-09 株式会社 日立ディスプレイズ Manufacturing method of display device

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