JPS6178187A - Semiconductor laser - Google Patents

Semiconductor laser

Info

Publication number
JPS6178187A
JPS6178187A JP59200086A JP20008684A JPS6178187A JP S6178187 A JPS6178187 A JP S6178187A JP 59200086 A JP59200086 A JP 59200086A JP 20008684 A JP20008684 A JP 20008684A JP S6178187 A JPS6178187 A JP S6178187A
Authority
JP
Japan
Prior art keywords
wire
laser element
semiconductor laser
gold
thick film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59200086A
Other languages
Japanese (ja)
Inventor
Tatsuya Ito
達也 伊藤
Hirokazu Hashimoto
廣和 橋本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujikura Ltd
Original Assignee
Fujikura Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujikura Ltd filed Critical Fujikura Ltd
Priority to JP59200086A priority Critical patent/JPS6178187A/en
Publication of JPS6178187A publication Critical patent/JPS6178187A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)
  • Semiconductor Lasers (AREA)

Abstract

PURPOSE:To improve wire bonding properties, and to enhance yield and reliability by die-bonding a metallic thick film on the upper surface of a semiconductor laser element with a heat sink and wire-bonding a lead wire with a metallic thick film on a lower surface. CONSTITUTION:Photo-resist layers 4 and 4a according to the same pattern in the upper and lower surfaces of a laser element 3 are each formed onto the upper and lower surface so that the positions of the upper and lower surfaces are conformed by using a device such as a double-side mask aligner. Metallic thick films 5 consisting of gold, silver, tin or the like and 5a composed of the same metal are shaped severally onto the upper and lower surfaces of the laser element 3 through selective plating, the photo-resist layers 4 and 4a are removed, and the whole is changed into chips. The upper and lower sections of the laser element 3 are turned upside down and the metallic thick film 5 is die-bonded onto a heat sink 6, and one tip of a gold wire 7 is wire- bonded with the upper surface of the metallic thick film 5a and the other tip of the gold wire 7 with a lead terminal 8 respectively.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は半導体レーザに関する。[Detailed description of the invention] [Industrial application field] This invention relates to semiconductor lasers.

〔従来技術〕[Prior art]

第１図は従来の半導体レーザの製造工程を示す図でおり
、この図において（イ）は、活性層、クラッド層等が形
成され、さらに１上面にジャンクション側の電極１か、
下面に電極２が各々形成されたストライプ構造の半導体
レーザ素子３の光射出面を示す図である（但し、素子内
部の＃構成は図示していない。）。従来の製造工程にお
いては、同図（ロ）Ｋ示すようＫこのレーザ素子３の上
面にフォトレジスト層４を形成し、次いで同図（／つに
示すように１金または銀等の金属厚膜５を選択メッキ（
ｆｉ解メッキ）によシ金属電極面上に形成する。FIG. 1 shows the manufacturing process of a conventional semiconductor laser.
2 is a diagram showing a light emitting surface of a semiconductor laser device 3 having a stripe structure in which electrodes 2 are each formed on the bottom surface (however, # structure inside the device is not shown). FIG. In the conventional manufacturing process, a photoresist layer 4 is formed on the upper surface of the laser element 3 as shown in FIG. Select 5 plating (
It is formed on the surface of the metal electrode by fi-electroplating.

この場合、金り厚膜５の厚さは数μｍ〜ＩＱμｍである
。ｔＫ、に１同図に）Ｋ示すようにフオトレジス）Ｆｆ
４４を除去した後、チップ化する。次に同図（ホ）に示
すように１ストライプ電極面であるジャンクション１ｌ
ｌＩヲ下Ｋして銅、シリコン、ダイヤモンド等からなる
ヒートシンク６上ＫＩｎ、Ｓｎ等の金私を用いてダイボ
ンデインクし、次いで、金線（またはＡｔ＠）７によシ
ミ極２とリード端子８とを接続する（ワイヤボンディン
グ）。In this case, the thickness of the thick gold film 5 is several μm to IQ μm. tK, as shown in the same figure)
After removing 44, it is made into a chip. Next, as shown in FIG.
Then, die-bond the heat sink 6 made of copper, silicon, diamond, etc. using gold wire such as KIn, Sn, etc., and then attach the stained electrode 2 and the lead terminal to the gold wire (or At@) 7. 8 (wire bonding).

以上の工程において、ヒートシンク６は半導体レーザの
動作時に発生する熱を逃がすためのものである。ま尭、
金属厚膜５を選択メンキしている理由は次の通シである
。すなわち、半導体レーザ素子３をヒートシンク６にダ
イボンティングする際、レーザ索子３とヒートシンク６
との熱膨張率ｏ差などｘよシ、レーザ索子３にストレス
か加わり、これがレーザ素子３の劣化、すなわち、しき
い値電流の増加、ダークラインの発生勢の原因となシ、
発振不良を招く。これを避けるために、金ｒＡｎ膜５の
選択メッキを行って、ストレスを緩和している。In the above steps, the heat sink 6 is used to release heat generated during operation of the semiconductor laser. Makoto,
The reason why the thick metal film 5 is selectively used is as follows. That is, when die-bonding the semiconductor laser element 3 to the heat sink 6, the laser cable 3 and the heat sink 6 are
Due to the difference in coefficient of thermal expansion between
This will cause oscillation failure. In order to avoid this, selective plating of the gold rAn film 5 is performed to alleviate stress.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

ところで、上述した半導体レーザ素子３の下面側の電極
２０表面は通常−〜３μｍ程度の粒子径の研摩剤で荒研
摩（ラッピング）されておシ、さらに電極２の一部には
オーミック電極としてＡｕＱ　ｏ等の合金電極か形成さ
れているが、上述した研摩や、合金電極の酸化および金
属間化合物の生成等か原因で金＠７を電極２にボンディ
ングする際のボンディング性が悪くなシ、この結果歩溜
シか悪化する問題があった。By the way, the surface of the electrode 20 on the lower surface side of the semiconductor laser element 3 described above is usually roughly polished (wrapped) with an abrasive having a particle size of about 3 μm, and furthermore, a part of the electrode 2 is coated with AuQ as an ohmic electrode. However, due to the above-mentioned polishing, oxidation of the alloy electrode, and the formation of intermetallic compounds, the bonding properties when bonding gold@7 to electrode 2 are poor. As a result, there was a problem that the yield was getting worse.

そこでこの発明は、ワイヤボンディング性を向上させ、
もって歩溜りの向上および信頼性の向上を図った半導体
レーザな提供することを目的としている。Therefore, this invention improves wire bonding properties,
The purpose of this invention is to provide a semiconductor laser with improved yield and reliability.

〔問題を解決する七めの手段〕[Seventh way to solve the problem]

この発明は、半導体レーザ索子の上面Ｋ（ジャンクショ
ン側の面）に金属厚膜を形成するのみならず、該レーザ
素子の下面にも、好ましくはジャンクション側の面の金
属厚膜を形成する際同時に金属厚膜を形成し、この下面
の金属厚膜に金線等かワイヤボンディングされているこ
とを特徴としている。This invention not only forms a thick metal film on the upper surface K (surface on the junction side) of the semiconductor laser element, but also forms a thick metal film on the lower surface of the laser element, preferably on the surface on the junction side. It is characterized in that a thick metal film is formed at the same time, and a gold wire or the like is wire-bonded to the thick metal film on the lower surface.

〔作用〕[Effect]

電極面に直接ワイヤボンディングするのではなく、電極
面に金属厚膜を形成し、この金属厚膜にワイヤボンディ
ングするので、ボンディング性が大幅に向上する。Rather than wire bonding directly to the electrode surface, a thick metal film is formed on the electrode surface and wire bonding is performed to this thick metal film, which greatly improves bonding performance.

〔実施例〕〔Example〕

第２図はこの発明による半導体レーザの製造工程を示す
図であり、この図において０）は、第一図（イ）と同様
に１上下面に各々電極１．２か形成され上半導体レーザ
素子３を示す図である。この実施例による製造工程にお
いては、まず、同図（ロ）Ｋ示すようにル−ザ素子３の
上下面に各々、両面マスクアライナ等の装置を用いるこ
とによシ、上下面同一のパターンによるフォトレジスト
層４および４ａを上下面の位置を合わせて形成する。次
に１同図（ハ）に示すようＫ、レーザ素子３の上下面に
各々金または銀あるいは錫等の金属厚膜５および同様な
金６よ〕なる５ａ（数μｍ〜１０μｍ）を選択メンキに
よシ形成し、次いで同図に）Ｋ示すように１フォトレジ
スト層４および４ａを除去した後、４゜チップ化する。FIG. 2 is a diagram showing the manufacturing process of a semiconductor laser according to the present invention. In this figure, 0) indicates an upper semiconductor laser element with electrodes 1 and 2 formed on the upper and lower surfaces of 1, respectively, as in FIG. 1 (A). It is a figure showing 3. In the manufacturing process according to this embodiment, first, as shown in FIG. Photoresist layers 4 and 4a are formed with their upper and lower surfaces aligned. Next, as shown in FIG. 1(c), a thick metal film 5 of gold, silver, or tin, and a similar gold film 5a (several μm to 10 μm) are selected and coated on the upper and lower surfaces of the laser element 3, respectively. After removing the first photoresist layers 4 and 4a as shown in FIG.

次に同図（ホ）Ｋ示すように、レーザ素７−３の上下を
逆にして金属厚膜５をヒートシンク６上にダイボンデイ
ンクし、次いで、金属厚膜５ａの上面に金＠７の一端を
、リード端子８に金＠７の他端を各々ワイヤボンディン
グする。Next, as shown in FIG. One end and the other end of gold@7 are wire-bonded to the lead terminal 8, respectively.

〔発明の効果〕〔Effect of the invention〕

以上述べ九ように１この発明によれば電極形成か終了し
上半導体レーザ素子の上面（ジャンクション側の面東金
属厚膜を形成し、さら（好ましくは同時に下面にも金属
厚膜を形成し、この下面の金属厚膜に金線等のリード線
をワイヤボンディングされるよ５ＫＬ、＆ので、従来に
比ベワイヤボンデイング性か大幅に向上し、この結果、
信頼性お上び歩溜シか共に向上する効果か得られる。ま
たこの発明によれば、ダイボンディング時にコレット等
でチップを押し付ける際のコレットの押し付は圧力によ
るストレスを緩和することかでき、この結果、ダイボン
デインク時におけるチップ割れを防止することができる
効果も得られる。As described above, 1. According to the present invention, after the electrode formation is completed, a thick metal film is formed on the upper surface (junction side surface) of the upper semiconductor laser element, and a thick metal film is also formed on the lower surface (preferably at the same time). Lead wires such as gold wires are wire-bonded to this thick metal film on the bottom surface.As a result, the wire bonding performance is greatly improved compared to conventional methods.
The effect of improving both reliability and yield can be obtained. Further, according to the present invention, when pressing a chip with a collet or the like during die bonding, the pressing of the collet can relieve stress caused by pressure, and as a result, it is possible to prevent chip cracking during die bonding. You can also get

【図面の簡単な説明】[Brief explanation of drawings]

第２図はこの発明の一実施例による半導体レーザの製造
工程を示す図、第２図は従来の半導体レーザの製造工程
の一例を示す図である ５、５ａ・・・・・・金属厚膜、６・・・・・・ヒート
シンク、７・・・・・・金線。 第２図2 is a diagram showing a manufacturing process of a semiconductor laser according to an embodiment of the present invention, and FIG. 2 is a diagram showing an example of a manufacturing process of a conventional semiconductor laser. 5, 5a...Metal thick film , 6... Heat sink, 7... Gold wire. Figure 2

Claims (2)

【特許請求の範囲】[Claims] （１）電極形成工程が終了した半導体レーザ素子の上下
面に各々金属厚膜が形成されており、上面の前記金属厚
膜がヒートシンクにダイボンディングされ、下面の前記
金属厚膜にリード線がワイヤボンディングされているこ
とを特徴とする半導体レーザ。(1) Thick metal films are formed on the top and bottom surfaces of the semiconductor laser element after the electrode formation process, the thick metal film on the top surface is die-bonded to a heat sink, and the lead wire is wired to the thick metal film on the bottom surface. A semiconductor laser characterized by being bonded. （２）前記半導体レーザの下面の金属厚膜が金または銀
あるいは錫が厚膜メッキされたものであることを特徴と
する特許請求の範囲第１項記載の半導体レーザ。(2) The semiconductor laser according to claim 1, wherein the metal thick film on the lower surface of the semiconductor laser is plated with gold, silver, or tin.
JP59200086A 1984-09-25 1984-09-25 Semiconductor laser Pending JPS6178187A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59200086A JPS6178187A (en) 1984-09-25 1984-09-25 Semiconductor laser

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59200086A JPS6178187A (en) 1984-09-25 1984-09-25 Semiconductor laser

Publications (1)

Publication Number Publication Date
JPS6178187A true JPS6178187A (en) 1986-04-21

Family

ID=16418619

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59200086A Pending JPS6178187A (en) 1984-09-25 1984-09-25 Semiconductor laser

Country Status (1)

Country Link
JP (1) JPS6178187A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100658939B1 (en) 2005-05-24 2006-12-15 엘지전자 주식회사 Package for light emitting device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100658939B1 (en) 2005-05-24 2006-12-15 엘지전자 주식회사 Package for light emitting device

Similar Documents

Publication Publication Date Title
US6297543B1 (en) Chip scale package
JPH04326534A (en) Chip bonding method of semiconductor device
JP5100967B2 (en) Lead frame, semiconductor chip package using the same, and manufacturing method thereof
JPH0689919A (en) Electric internal connection substrate provided with both wire bond and solder connection and manufacture
JPS632332A (en) Die-bonding process
US11594504B2 (en) Nickel alloy for semiconductor packaging
JP5103731B2 (en) Mold package
WO2007034791A1 (en) Solder layer, heat sink using such solder layer and method for manufacturing such heat sink
JP2001345411A (en) Lead frame and semiconductor device using the same and its manufacturing method
JPS6178187A (en) Semiconductor laser
JPH04155854A (en) Semiconductor integrated circuit device and lead frame therefor
JP2000196005A (en) Semiconductor device
JP2000195894A (en) Manufacture of semiconductor device
JPH09330992A (en) Semiconductor device mounting body and its manufacture
JP3148604B2 (en) Semiconductor device
TWI723932B (en) Side wettable package component and its manufacturing method
JPS62287657A (en) Semiconductor device
JPH11135532A (en) Semiconductor chip and semiconductor device
JPS5815252A (en) Bump structure
JPH06196824A (en) Manufacture of semiconductor element
JPS6129139A (en) Semiconductor device
JPH04162638A (en) Manufacture of semiconductor integrated circuit device
JPS5928049B2 (en) Semiconductor device lead connection method
JP3220638B2 (en) Method for manufacturing semiconductor device
JPH08250545A (en) Semiconductor device and manufacture thereof