JPS617667A - Manufacture of field-effect transistor - Google Patents
Manufacture of field-effect transistorInfo
- Publication number
- JPS617667A JPS617667A JP12860184A JP12860184A JPS617667A JP S617667 A JPS617667 A JP S617667A JP 12860184 A JP12860184 A JP 12860184A JP 12860184 A JP12860184 A JP 12860184A JP S617667 A JPS617667 A JP S617667A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- source
- active layer
- etching
- mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 6
- 230000005669 field effect Effects 0.000 title claims description 5
- 238000005530 etching Methods 0.000 claims abstract description 20
- 239000013078 crystal Substances 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 239000004065 semiconductor Substances 0.000 claims description 2
- 238000003486 chemical etching Methods 0.000 abstract description 3
- 230000001681 protective effect Effects 0.000 abstract description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract 2
- 238000000034 method Methods 0.000 description 12
- 239000002184 metal Substances 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 238000010438 heat treatment Methods 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000004943 liquid phase epitaxy Methods 0.000 description 2
- 239000011259 mixed solution Substances 0.000 description 2
- 230000003213 activating effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
- 239000002966 varnish Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、単結晶めエツチング特性を利用してソース、
ドレイン及びゲート電極をセルファライン化した、電界
効果トランジスタの製造方法に関するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention utilizes single crystal etching characteristics to
The present invention relates to a method of manufacturing a field effect transistor in which drain and gate electrodes are self-aligned.
ＭＥＳ ＦＥＴ （Ｍｅｔａｌ Ｓｅｍ１ｃｏ
ｎｄｕｃｔｏｒ ＦｉｅｌｄＥｆｆｅｃｔ Ｔｒａ＋１
ｓｉｓｔｏｒ ）においては、ソース、ドレイン及び、
ゲート電極のセルファライン化の方法が多く提案されて
いる。MES FET (Metal Sem1co
ndductor FieldEffect Tra+1
sister), the source, drain and
Many methods have been proposed for making gate electrodes self-aligned.
たとえば選択イオン注入により形成された活性層上にＳ
ｉＯ□を堆積し、その上に金属層を形成して将来ゲート
電極となる部分だけをエツチングにより残す。次に１．
ソース、ドレイン領域に高濃度のイオン注入を行い、該
ゲート部の金＠層をマスクとして、該ゲート部の５ｔｏ
２（以下単にＳｉ ０２ ダミーゲートとする）をサイ
ドエツチングし、全面に５ｉ０２を堆積して、Ｎ＋ 層
活性化のためのアツールを行う。その後Ａ ｕ Ｇ ｅ
／ Ａ ｕ ｈ・らなるオーミック電極を形成して、
該ゲート部の上部からＳ ｉ ０２ 層までを除去し
、ゲート電極を形成する。この方法では、ゲート電極形
成の際のマスク合せが不要で、サイドエツチングを行う
たもサブミクロンゲートの形成が可能である。（電子通
信学会技術研究報告 ５ＳＤ８３−１０９）〔発明が解
決しようとする問題点〕
誘電体膜を将来ゲート部になる部分に用いたものではソ
ース、ドレイン電極を形成する際の熱処理時において、
該誘電体膜と活性層の膨張率が違うために生じる活性層
の劣化がありまた短ゲートにする場合においてもゲート
長さの再現性に問題がある。またリセスエッチングが難
しいのでソース、ドレイン間の耐圧が低くなり易いとい
う問題が生じる。For example, S on the active layer formed by selective ion implantation.
iO□ is deposited, a metal layer is formed thereon, and only the portion that will become the gate electrode in the future is left by etching. Next 1.
High-concentration ion implantation is performed in the source and drain regions, and the 5to
2 (hereinafter simply referred to as Si 02 dummy gate) is side-etched, 5i02 is deposited on the entire surface, and a tooling for activating the N+ layer is performed. After that A u G e
/ A u h · form an ohmic electrode,
A gate electrode is formed by removing the portion from the upper part of the gate portion to the Si 02 layer. This method does not require mask alignment when forming the gate electrode, and it is possible to form submicron gates by performing side etching. (IEICE technical research report 5SD83-109) [Problems to be solved by the invention] In the case where a dielectric film is used in the part that will become the gate part in the future, during the heat treatment when forming the source and drain electrodes,
The active layer deteriorates due to the difference in expansion coefficient between the dielectric film and the active layer, and there is also a problem in the reproducibility of the gate length even when the gate is made short. Further, since recess etching is difficult, there arises a problem that the withstand voltage between the source and drain tends to be low.
この他にフォトレジストを用いたもの、たとえば基板上
にフォトレジストを塗布し、パターニングを行いゲート
金属をリフトオフにより形成する。In addition, a photoresist is used, for example, a photoresist is applied onto a substrate, patterned, and a gate metal is formed by lift-off.
その後通常の方法でソース電極とドレイン電極を形成す
る方法等においても、ソースとドレイン電極の熱処理時
（通常４００℃以上）にゲート電極の劣化が生じる。Even in methods such as forming a source electrode and a drain electrode by a normal method, the gate electrode deteriorates during heat treatment of the source and drain electrodes (usually at 400° C. or higher).
本発明は、上記問題点を解消したＭＥＳ ＦＥＴの製
造方法を提供するもので、その手段は半導体基板上に活
性層を設け、該活性層上にエツチングによって形成され
た逆台形の単結晶のダミーゲートを設け、該ダミーゲー
トをマスクとして用いてソース、ドレイン電極を位置決
めし、該ダミーゲートを除去して該活性層内に台形のリ
セスを形成し、リセス部の台形上部の活性層の庇部によ
り、ゲートの位置を自己整合させることを特徴とする電
界効果トランジスタの製造方法によってなされる。The present invention provides a method for manufacturing a MES FET that solves the above-mentioned problems, and the method includes providing an active layer on a semiconductor substrate, and forming an inverted trapezoidal single crystal dummy by etching on the active layer. A gate is provided, the source and drain electrodes are positioned using the dummy gate as a mask, the dummy gate is removed to form a trapezoidal recess in the active layer, and the eaves of the active layer above the trapezoid of the recessed portion is removed. This is accomplished by a method of manufacturing a field effect transistor characterized by self-aligning the position of the gate.
活性層上に、活性層に格子整合できる単結晶を形成し、
エツチングで残った逆台形の部分をダミーゲートとして
使用する。この際に、ゲート長さとダ評９−トの厚みを
設定すると必然的にマスクのストライプ幅がきまるので
該マスクで逆台形状のダミーゲートを作成する。次に、
ソース、ドレイン電極を形成し、ダミーゲートを除去し
て台形状のリセス構造を作成し、その部分にゲート電極
を形成することでＭＥＳ ＦＥＴの各電極が高精度に容
易に製造できるものである。Forming a single crystal on the active layer that can lattice match the active layer,
Use the inverted trapezoidal part left after etching as a dummy gate. At this time, setting the gate length and the thickness of the gate inevitably determines the stripe width of the mask, so an inverted trapezoidal dummy gate is created using the mask. next,
By forming the source and drain electrodes, removing the dummy gate to create a trapezoidal recess structure, and forming the gate electrode in that portion, each electrode of the MES FET can be easily manufactured with high precision.
以下に本発明の一実施例を示す。符号は全図を通じて同
一部分には同一符号を付して示した。An example of the present invention is shown below. The same parts are denoted by the same reference numerals throughout the figures.
第１図参照。See Figure 1.
（１００）面を有する半絶縁性の基板ＧａＡｓ１、上に
気相エピタキシャル成長で（１００）面活性層（０，５
〜１ μｎ） ＧａＡｓ ２．を形成する。該活性層の
形成法にはこの他に液相成長法（ＬＰＥ）、有機金属気
相成長法（ＭＯＣＶＤ）、分子ビーム成長法（ＭＢＥ）
等がありイオン注入法を採用してもよい。該活性層上に
続けて成長した単結晶（活性層と同一物質、もしくは格
子整合できるもの）、ＧａＡｓ （あるいはＧ ａ
Ａ ｊｌ！ Ａ ｓ ） （０゜５〜１μｍ）３．に
エツチングマスク（０，１〜０．３μｍ） Ｓ ｉ ０
２ ４．を付着させる。A semi-insulating GaAs substrate with a (100) plane is grown on a (100) plane active layer (0,5) by vapor phase epitaxial growth.
~1 μn) GaAs 2. form. Other methods for forming the active layer include liquid phase epitaxy (LPE), metal organic chemical vapor deposition (MOCVD), and molecular beam epitaxy (MBE).
etc., and ion implantation methods may be adopted. A single crystal (same material as the active layer or one that can lattice match), GaAs (or Ga
A jl! A s ) (0°5-1 μm)3. Etching mask (0.1-0.3 μm) S i 0
2 4. Attach.
（一般的に１．５〜３μｍ）であるストライプをフォト
リソ法で作成し作成したエツチングマクス４′を用いて
活性層に格子整合した単結晶３をＫＯＨ・Ｈ２Ｏ２・Ｈ
２Ｃの混液もしくはＨ２ＳＯリ ・Ｈ２０□ ・Ｈ２Ｃ
の混液で異方性エツチングしてストライプ状に単結晶を
残す（例えば後者、硫酸系で１８：１：１の場合０．８
μｍ／ｍ ｉ ｎ）。(generally 1.5 to 3 μm) is formed by photolithography, and a single crystal 3 lattice-matched to the active layer is formed using etching mask 4' using KOH, H2O2, H
2C mixture or H2SO ・H20□ ・H2C
Anisotropic etching is performed with a mixed solution of
μm/min).
これをダミーゲート結晶とする。このとき、該活性層と
ストライプの側面とで形成される角度θ＝４５°である
。該ダミーゲートを形成した時点で性能を高めるために
ソース、ドレイン領域へイオン注入を行ってもよい。This is used as a dummy gate crystal. At this time, the angle θ formed by the active layer and the side surface of the stripe is 45°. At the time when the dummy gate is formed, ions may be implanted into the source and drain regions to improve performance.
第３図参照。See Figure 3.
エツチングマスクを除去し、該ダミーゲートを用いて、
Ａ ｕ Ｇ ｅ ／ Ａ ｕ ５．を蒸着により形成す
ることでソース、ドレイン電極をセルファラインして形
成した後、熱処理を行う。（エツチングマスクを付着し
たままＡ ｕ Ｇ ｅ ／ Ａ ｕを形成してもよい。Remove the etching mask and use the dummy gate,
A u G e / A u 5. After the source and drain electrodes are formed by self-alignment by vapor deposition, heat treatment is performed. (A u G e / A u may be formed with the etching mask attached.
） 第４図参照。) See Figure 4.
フォトレジスト（ＡＺ−１３５０Ｊ）６．を塗布（〜３
μｍ）し、反応性イオンエ・７チングＲ，Ｉ。Photoresist (AZ-1350J)6. Apply (~3
μm) and reactive ion etching R,I.
Ｅ、 （Ｒｅａｃｔｉｖｅ−Ｔｏｎ Ｅｔｃｈｉｎｇ
） 、あるいは、０２プラズマ（０□プラズマの場合
、ダミーゲート・トップのメタルまでエツチングし、次
いで選択エツチングでメタル及び誘電体膜を落す。）で
該ダミーゲートのトップまでエツチングする。第５図参
照。E, (Reactive-Ton Etching
), or etching to the top of the dummy gate using 02 plasma (in the case of 0□ plasma, etching is performed to the metal on the top of the dummy gate, and then the metal and dielectric film are removed by selective etching). See Figure 5.
第６図参照。See Figure 6.
° ダミーゲートを除去しリセス構造を作成するために
、ケミカルエツチングをする。この場合、ＧａＡｓのエ
ツチングではＨ２ＳＯ，、Ｈ２Ｏ２。° Perform chemical etching to remove the dummy gate and create a recess structure. In this case, H2SO, H2O2 is used for GaAs etching.
Ｈ２Ｃ，の混液へひたすことにより活性層にリセス構造
をつくる。A recess structure is created in the active layer by dipping it into a mixed solution of H2C.
第７図参照。See Figure 7.
次いでゲートメタルＡｌ （〜３０００人゛）７．をた
のち表面安定化のために表面保護膜Ｓｉ３ Ｎｔｔ８゜
をプラズマ化学気相成長法（プラズマＣｈｅｍｉｃａｌ
Ｖａｐｏｕｒ Ｄｅｐｏｓｉｔｉｏｎ ）で付着させて
パターニングを行う。第８図参照。Next, Gate Metal Al (~3000 people)7. After that, a surface protective film of Si3 Ntt8° was deposited using plasma chemical vapor deposition method (plasma chemical vapor deposition) to stabilize the surface.
(Vapour Deposition) and patterning is performed. See Figure 8.
第９図参照。See Figure 9.
第９図は第５図での上面図を示す。FIG. 9 shows a top view of FIG. 5.
第４図の工程で塗布したフォトレジスト（ＡＺ−１３５
０Ｊ）は上方から見ると、ソース電極笈びドレイン電極
より広範囲（図中、砂地部）を覆っている。Photoresist (AZ-135) applied in the process shown in Figure 4
0J) covers a wider area (sandy area in the figure) than the source and drain electrodes when viewed from above.
ここで更にポジ型のフォトレジスト（０ＭＲ７８５）を
塗布し、ソース、）″レイン電極より大きめの窓開け、
をする。Then, apply a positive photoresist (0MR785) and open a window larger than the source and )'' rain electrodes.
do.
これによりゲート金属はソース・ドレインより長く外側
へつき抜けて形成されることになる。As a result, the gate metal is formed to penetrate outward for a longer length than the source/drain.
以上述べたように、該ダミーゲートに単結晶を用いるこ
とにより、ソース、トレイン、及びゲート電極がすべて
セルファライン化でき、ゲート長設定のためのフォトプ
ロセスは微細パターンを使用しないので簡単になる。As described above, by using a single crystal for the dummy gate, the source, train, and gate electrodes can all be self-lined, and the photo process for setting the gate length can be simplified because no fine pattern is used.
本発明によれば単結晶のダミーゲートのもつ化学エツチ
ングの面方位依存性の特性を利用することによって、ワ
ニス。ドレイン電極の位置を定めることができる。According to the present invention, the varnish is produced by utilizing the surface orientation dependence characteristic of chemical etching of a single crystal dummy gate. The position of the drain electrode can be determined.
また、ダ佼シートの厚みを変化させることによりゲート
、ソース、ドレイン電極の相対的な距離の制御ができ、
ゲート長キも同時に決定できる。In addition, by changing the thickness of the Daka sheet, the relative distance between the gate, source, and drain electrodes can be controlled.
Gate length key can also be determined at the same time.
また、三電極を容易にセルファライン化することができ
る。リセス形成過程でもエンチングの形状は、広範囲の
エツチング条件において定形なので再現性や精度９歩留
まりを良くすることができる。Further, the three electrodes can be easily formed into a self-aligned line. Even in the recess formation process, the etched shape remains constant under a wide range of etching conditions, which improves reproducibility, precision, and yield.
また活性層に格子整合できる単結晶を用いてダミーゲー
トを作るので熱処理のときに活性層が損傷を受けること
がない。Furthermore, since the dummy gate is made using a single crystal that can be lattice-matched to the active layer, the active layer is not damaged during heat treatment.
第１図乃至第８図は、本発明の一実施例のＭＥ層、３．
は活性層に格子整合する単結晶ＧａＡｓ。
４、は絶縁膜ｓ、 ｉ ０ｑ” ＋ ５−は導電ｉｉ
ｔ Ａ ｕ Ｇ ｅ ／ Ａ ｕ 。
６、はネガ型レジスト、７．は導電ＮＡｌ１．Ｂ、は表
面保護膜５＝３Ｎｙ 、 １０．は開孔部（リセス）
、１５はポジ型レジストである。1 to 8 illustrate the ME layer of one embodiment of the present invention, 3.
is single-crystal GaAs that is lattice-matched to the active layer. 4 is the insulating film s, i 0q" + 5- is the conductive ii
t A u G e / A u . 6. is a negative resist; 7. is conductive NAl1. B, surface protective film 5=3Ny, 10. is the opening (recess)
, 15 are positive resists.
Claims (1)
によって形成された断面が逆台形の単結晶のダミーゲー
トを設け、該ダミーゲートをマスクとして用いてソース
、ドレイン電極を位置決めし、該ダミーゲートを除去し
て該活性層内に断面が台形のリセスを形成し、リセス部
の台形上部の活性層の庇部によりゲートの位置を自己整
合させることを特徴とする電界効果トランジスタの製造
方法。An active layer is provided on a semiconductor substrate, a single-crystal dummy gate with an inverted trapezoid cross section is provided on the active layer by etching, and the source and drain electrodes are positioned using the dummy gate as a mask. 1. A method of manufacturing a field effect transistor, comprising: removing a gate to form a recess with a trapezoidal cross section in the active layer; and self-aligning the position of the gate with the eaves of the active layer above the trapezoid of the recess.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12860184A JPS617667A (en) | 1984-06-22 | 1984-06-22 | Manufacture of field-effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12860184A JPS617667A (en) | 1984-06-22 | 1984-06-22 | Manufacture of field-effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS617667A true JPS617667A (en) | 1986-01-14 |
Family
ID=14988804
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12860184A Pending JPS617667A (en) | 1984-06-22 | 1984-06-22 | Manufacture of field-effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS617667A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62141780A (en) * | 1985-12-16 | 1987-06-25 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| CN103681328A (en) * | 2012-09-10 | 2014-03-26 | 中国科学院微电子研究所 | Method for manufacturing field effect transistor |
-
1984
- 1984-06-22 JP JP12860184A patent/JPS617667A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62141780A (en) * | 1985-12-16 | 1987-06-25 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| CN103681328A (en) * | 2012-09-10 | 2014-03-26 | 中国科学院微电子研究所 | Method for manufacturing field effect transistor |
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