JPS6167268A - Thin film transistor and manufacture thereof - Google Patents
Thin film transistor and manufacture thereofInfo
- Publication number
- JPS6167268A JPS6167268A JP18813184A JP18813184A JPS6167268A JP S6167268 A JPS6167268 A JP S6167268A JP 18813184 A JP18813184 A JP 18813184A JP 18813184 A JP18813184 A JP 18813184A JP S6167268 A JPS6167268 A JP S6167268A
- Authority
- JP
- Japan
- Prior art keywords
- film
- region
- cdse
- semiconductor layer
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000010408 film Substances 0.000 claims abstract description 73
- 239000004065 semiconductor Substances 0.000 claims abstract description 40
- UHYPYGJEEGLRJD-UHFFFAOYSA-N cadmium(2+);selenium(2-) Chemical compound [Se-2].[Cd+2] UHYPYGJEEGLRJD-UHFFFAOYSA-N 0.000 claims abstract description 30
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 25
- 239000012535 impurity Substances 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000000151 deposition Methods 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 abstract description 13
- 239000002184 metal Substances 0.000 abstract description 13
- 239000011521 glass Substances 0.000 abstract description 4
- 229910052782 aluminium Inorganic materials 0.000 abstract 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 abstract 1
- 229910052593 corundum Inorganic materials 0.000 abstract 1
- 229910001845 yogo sapphire Inorganic materials 0.000 abstract 1
- 238000000034 method Methods 0.000 description 34
- 238000000206 photolithography Methods 0.000 description 9
- 238000011109 contamination Methods 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 5
- 230000007423 decrease Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- 238000005036 potential barrier Methods 0.000 description 2
- 238000001771 vacuum deposition Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 231100000989 no adverse effect Toxicity 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000004506 ultrasonic cleaning Methods 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78681—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は薄膜トランジスタの改良に関し、特にゲート絶
縁膜と半導体層との界面を良好にした薄膜トランジスタ
およびその製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to improvements in thin film transistors, and particularly to a thin film transistor with a good interface between a gate insulating film and a semiconductor layer, and a method for manufacturing the same.
（従来例の構成とその問題点）
ＣｄＳｅを半導体層とする薄膜トランジスタの従来例を
第１図に示す。ガラス基板１上にＡｇ等の金属層で形成
したゲート電極２、ＡＮ、Ｏ，等からなるゲ−ト絶縁膜
３、ｎ形の導電型を与える不純物１例えばＩｎ、Ｇａ、
ＡＮ等を含んだＣｄＳｅからなる半導体層４゜Ａ＆等の
金属層からなるソース電極５およびドレイン電極６とか
ら構成されている。このような構造の薄膜トランジスタ
において所定の領域に半導体層を形成する方法として、
半導体の付着領域以外を金属薄片でカバーするメタルマ
スク方式とＩＣ技術として周知のフォトレジスト膜を用
いるフォトリソグラフィ方式とがある。蒸着法などによ
りＣｄＳｅを付着する領域の形状が数１０μ国以下にな
るとメタルマスク方式は精度の点で難がしくフォトリン
グラフィ方式を用いざるを得ない。この場合には、Ｃｄ
Ｓｅを確実にかつ容易に所定領域のみに形成するために
、フォトレジスト膜を用いたりフトオフ法が通常使われ
ている。この方法は、ゲート絶縁膜３上にフォトレジス
ト膜を全面塗布形成した後、露光、現像処理によりＣｄ
Ｓｅを付着する領域のみのフォトレジスト膜を除去する
。この後、全面にＣｄＳｅを蒸着法などにより付着した
後フォトレジスト膜およびフォトレジスト膜上のＣｄＳ
ｅを除去する方法である。この従来の方法では、ＣｄＳ
ｅを付着する領域中に、フォトレジスト膜の残渣やフォ
トレジスト膜中に含まれる不純物の付着、また露光、現
像処理中のプロセスの汚染があると、薄膜トランジスタ
においてチャネル領域となる絶縁層とＣｄＳｅ層との界
面は非常に汚れた状態となり、キャリアのトラップ・レ
ベル等も多く発生し、良好なトランジスタ特性を得るこ
とができない。例えば、同一構成で同一形状のＣｄ５ｅ
−ＴＰＴをメタルマスク方式およびフォトリソグラフィ
方式で試作した時の各々の電気特性を表に比較して示す
。(Structure of a conventional example and its problems) A conventional example of a thin film transistor using CdSe as a semiconductor layer is shown in FIG. A gate electrode 2 formed of a metal layer such as Ag on a glass substrate 1, a gate insulating film 3 made of AN, O, etc., an impurity 1 imparting n-type conductivity, such as In, Ga, etc.
It is composed of a semiconductor layer 4 made of CdSe containing AN, etc., and a source electrode 5 and a drain electrode 6 made of a metal layer such as A&. As a method for forming a semiconductor layer in a predetermined region in a thin film transistor having such a structure,
There are two methods: a metal mask method in which areas other than the area to which the semiconductor is attached are covered with a metal thin piece, and a photolithography method using a photoresist film, which is well known as IC technology. When the shape of the region to which CdSe is deposited by vapor deposition or the like is less than several tens of microns, the metal mask method becomes difficult in terms of accuracy, and the photolithography method must be used. In this case, Cd
In order to reliably and easily form Se only in predetermined areas, a photoresist film or a foot-off method is usually used. In this method, a photoresist film is coated on the entire surface of the gate insulating film 3, and then Cd
The photoresist film is removed only from the region where Se is to be attached. After that, CdSe is deposited on the entire surface by vapor deposition, etc., and then the photoresist film and the CdSe on the photoresist film are deposited.
This is a method of removing e. In this conventional method, CdS
If there is residue of the photoresist film, impurities contained in the photoresist film, or contamination from the exposure and development processes in the area where the CdSe film is deposited, the insulating layer and CdSe layer, which will become the channel region of the thin film transistor, will be damaged. The interface with the substrate becomes extremely dirty, and many trap levels of carriers occur, making it impossible to obtain good transistor characteristics. For example, Cd5e with the same configuration and shape
-The table shows a comparison of the electrical characteristics of TPT manufactured using a metal mask method and a photolithography method.
表
の場合には、閾値電圧Ｖ、は増加し、トランジスタ特性
から求めたＣｄＳｅの移動度μは極端に減少する。In the case of the table, the threshold voltage V increases, and the mobility μ of CdSe determined from the transistor characteristics extremely decreases.
また電子のＣｄＳｅ膜中の移動度μは減少しドレイン電
流工。も少なくなりかっ工。の安定性も悪い。ゲート絶
縁膜とＣｄＳｅ層との界面に与えるフォトレジスト膜工
程の影響が、 ＴＰＴの特性の劣化に大きく作用してい
ることは明らかである。In addition, the electron mobility μ in the CdSe film decreases and the drain current decreases. There are also fewer brackets. The stability is also poor. It is clear that the influence of the photoresist film process on the interface between the gate insulating film and the CdSe layer has a large effect on the deterioration of the TPT characteristics.
（発明の目的）
本発明の目的は、以上のような従来技術に鑑み、絶縁層
と半導体層との界面をメタルマスク方式と同程度に良好
にし、 ＴＦＴの特性の改善を図ることにある。(Objective of the Invention) In view of the above-mentioned conventional techniques, an object of the present invention is to improve the characteristics of a TFT by making the interface between an insulating layer and a semiconductor layer as good as that of a metal mask method.
（発明の構成）
本発明は上記目的を達成するために、少なくともゲート
市極を含む領域上にゲート絶縁膜を介して低抵抗率の所
定形状の第１の半導体領域が形成されており、前記ゲー
ト絶縁膜上の前記第１の半導体領域の周囲に高抵抗率の
第２の半導体領域が形成されており、少なくとも前記ゲ
ート電極上の前記第１の半導体領域上にソースおよびド
レイン電極が形成されていることを特徴とする薄膜トラ
ンジスタおよびその製□造方法を提供する。すなわち、
本発明による薄膜トランジスタは、ゲート絶縁膜上全面
に形成した高抵抗ＣｄＳｅ膜上にフォトリングラフィ方
式によるフォトレジスト膜のパターン形成を行ない所定
領域のみにｎ形の導電性を与える不純物を付着した後、
熱処理を施しＣｄＳｅ中に前記不純物を拡散させて低抵
抗率のＣｄＳｅ膜を形成しＴＰＴのアクティブ領域とす
る。この方法によって、ＴＰＴのチャンネル領域となる
ゲート絶縁膜とＣｄＳｅ膜との界面には、従来例に見ら
れたフォトリソグラフィ方式によるフォトレジスト膜工
程での汚れはほとんど無くなり、ＴＦＴの特性はメタル
マスク方式の場合と同程度のＶ？＋μ、■。を得ること
ができた。(Structure of the Invention) In order to achieve the above object, the present invention includes forming a first semiconductor region having a predetermined shape and having a low resistivity over a region including at least a gate electrode with a gate insulating film interposed therebetween; A second semiconductor region with high resistivity is formed around the first semiconductor region on the gate insulating film, and source and drain electrodes are formed on at least the first semiconductor region on the gate electrode. A thin film transistor and a method for manufacturing the same are provided. That is,
In the thin film transistor according to the present invention, a photoresist film is patterned by a photolithography method on a high-resistance CdSe film formed on the entire surface of a gate insulating film, and an impurity that gives n-type conductivity is deposited only in a predetermined region.
A heat treatment is performed to diffuse the impurity into CdSe to form a CdSe film with low resistivity, which becomes the active region of the TPT. With this method, the interface between the gate insulating film and the CdSe film, which forms the channel region of the TPT, is almost completely free of contamination caused by the photoresist film process using the photolithography method, which was seen in conventional examples, and the characteristics of the TFT are similar to those of the metal mask method. The same V as in the case of ? ＋μ、■. I was able to get
（実施例の説明） 以下１本発明を実施例に従って詳細に説明する。(Explanation of Examples) Hereinafter, the present invention will be explained in detail according to examples.
第２図は本発明の一実施例をなす１膜トランジスタの構
成を示す断面図である。２０００人程度０厚みを有する
Ａρ等の金属からなるゲート電極８を備えたガラス等の
絶縁性基板７上に４０００人程度０厚さを有するＡｌ、
０３等からなるゲート絶縁膜９が形成されている。前記
ゲート絶縁膜９上に１０００人程度０厚さを有し、その
抵抗率が１０６〜１０’Ω・■程度のＣｄＳｅ等からな
る高抵抗の半導体層１０が形成されでおり、前記高抵抗
半導体層１０中で少なくともゲート電極８を含む領域上
に、 Ｇａ、Ｉｎ、１等のｎ形の導電率を与える不純物
を含む抵抗率が１０３〜ＩＯ４Ω・国程度のＣｄＳｅ等
からなる所定形状の低抵抗の半導体領域１１が形成され
ている。少なくとも前記低抵抗の半導体領域１１を含む
領域上に２０００人程度０厚さを有するＡＮ等からなる
ソース電極１２およびドレイン電極１３が形成されてい
る。本発明による構造では、半導体層１０はゲート絶縁
膜９上に微細な領域を限定することなく形成されている
ため、絶縁膜上に直接フォトレジスト膜を塗布形成し、
微細パターンを作成する工程がないため、従来問題とな
っていたフォトレジスト膜工程によるゲート絶縁膜９と
半導体層１０との界面の汚熟は全く発生しない。薄１１
１；Ｊトランジスタの微細なチャネルと領域の決定は前
記高抵抗半導体層１０上にフォトリングラフィ方式によ
り作製した微細な半導体領域１１中にｎ形の導電率を与
える不純物を導入することにより、電気的に活性な低抵
抗の半導体領域を形成することにより行なわれる。この
時、前記高抵抗半導体層１０上に直接フォトレジスト膜
が塗布形成されるが、この際の汚染は前記高抵抗半導体
層表面に限定され、絶縁膜と半導体層との界面には何等
悪い影響を与えなかった。また、ソース電極やドレイン
電極に対しても薄膜トランジスタの動作上問題となるよ
うな悪い影響は見っからながった。・本発明による構造
の薄膜トランジスタのｖ７は約１ｖ、μは約２００ａＪ
／ｖ、ｓとメタルマスク方式で作製した薄膜トランジス
タをほぼ同様の特性が得られた。FIG. 2 is a cross-sectional view showing the structure of a single-film transistor that constitutes an embodiment of the present invention. An insulating substrate 7 made of glass or the like is provided with a gate electrode 8 made of a metal such as Aρ having a thickness of about 2000, and Al having a thickness of about 4000,
A gate insulating film 9 made of 03 or the like is formed. A high-resistance semiconductor layer 10 made of CdSe or the like is formed on the gate insulating film 9 and has a thickness of about 1,000 Ω and a resistivity of about 10 6 to 10' Ω·■. On the region including at least the gate electrode 8 in the layer 10, a low resistance film of a predetermined shape made of CdSe or the like having a resistivity of about 103 to IO4Ω including impurities such as Ga, In, 1, etc. that gives n-type conductivity is placed. A semiconductor region 11 is formed. A source electrode 12 and a drain electrode 13 made of AN or the like having a thickness of approximately 2,000 mm are formed on a region including at least the low-resistance semiconductor region 11. In the structure according to the present invention, since the semiconductor layer 10 is formed on the gate insulating film 9 without defining a fine region, a photoresist film is directly applied and formed on the insulating film.
Since there is no process of creating a fine pattern, there is no contamination of the interface between the gate insulating film 9 and the semiconductor layer 10 due to the photoresist film process, which has been a problem in the past. Thin 11
1; The fine channel and region of the J transistor are determined by introducing an impurity giving n-type conductivity into the fine semiconductor region 11 formed on the high-resistance semiconductor layer 10 by photolithography. This is done by forming a low-resistance semiconductor region that is actively active. At this time, a photoresist film is directly applied and formed on the high resistance semiconductor layer 10, but contamination at this time is limited to the surface of the high resistance semiconductor layer, and there is no adverse effect on the interface between the insulating film and the semiconductor layer. did not give. Further, there was no apparent adverse effect on the source electrode or drain electrode that would cause problems in the operation of the thin film transistor.・V7 of the thin film transistor having the structure according to the present invention is approximately 1V, and μ is approximately 200aJ.
Almost the same characteristics were obtained for the thin film transistor manufactured by the metal mask method as /v,s.
この結果、本発明の薄膜トランジスタでは、フォトリン
グラフィ方式を用いた微細なチャネル形状をしているに
もかかわらず、その絶縁膜と半導体層との界面はメタル
マスク方式の場合と同程度の清浄さであることが明らか
であり、その電気特性は従来構造の薄膜トランジスタに
比べ大幅に改善された。As a result, in the thin film transistor of the present invention, despite having a fine channel shape using the photolithography method, the interface between the insulating film and the semiconductor layer is as clean as that in the case of the metal mask method. It is clear that the electrical characteristics are significantly improved compared to thin film transistors with conventional structures.
次に第３図を用いて本発明の薄膜トランジスタの装置方
法の一例を示す。Next, an example of a method for manufacturing a thin film transistor according to the present invention will be described with reference to FIG.
ガラス等の絶縁性基板７上に抵抗加熱法を用いた真空蒸
着等により約２０００人の厚さのＡＱ等からなるゲート
電極８を所定の形状に作製する。しかる後、前記絶縁性
基板７およびゲート電極８上にＡｒ：Ｏ，＝３：１，４
Ｘ １Ｏ−３Ｔｏｒｒの雰囲気ガス中で例えばＡＱを
スパッタすることにより約４０００人の厚さのＡｔ’２
０．膜９を形成する。つづいて、約３００℃に加熱した
前記１．Ｏ，膜９上に例えば抵抗加熱法を用いた真空蒸
着により約１０００人の厚みのＣｄＳｅ膜を０．５人／
ｓｅｃ程度の速さで形成する。このようにして作製した
ＣｄＳｅ膜の組成は化学量論比に非常に近い値でありま
た、その電気抵抗率は１０’〜１０’Ω・口と高い値を
示す。また、その移動度μは多結晶粒界での電位障壁の
影響を受けて０．１ａ（／ｖ、ｓ程度の小さな値を示す
（第３図（Ａ））。On an insulating substrate 7 made of glass or the like, a gate electrode 8 made of AQ or the like having a thickness of about 2,000 wafers is fabricated in a predetermined shape by vacuum evaporation using a resistance heating method or the like. After that, Ar:O,=3:1,4 is applied on the insulating substrate 7 and gate electrode 8.
At'2 with a thickness of about 4000 by sputtering, for example, AQ in an atmospheric gas of
0. A film 9 is formed. Next, the above 1. heated to about 300°C. O, a CdSe film with a thickness of about 1,000 layers is deposited on the film 9 by vacuum deposition using, for example, a resistance heating method.
It is formed at a speed of about sec. The composition of the CdSe film produced in this manner is very close to the stoichiometric ratio, and its electrical resistivity is as high as 10' to 10' Ω. Further, the mobility μ shows a small value of about 0.1a(/v,s) due to the influence of the potential barrier at the polycrystalline grain boundary (FIG. 3(A)).
前記高抵抗ＣｄＳｅ膜１０上の全面にフォトレジスト（
例えばＡＺ１３００：商品名）を約１．５μｍの厚さに
塗布した後、周知のフォトリソグラフィ法により所定形
状のフォトレジスト膜１４のパターンを形成する。A photoresist (
For example, after applying AZ1300 (trade name) to a thickness of about 1.5 μm, a pattern of a photoresist film 14 having a predetermined shape is formed by a well-known photolithography method.
しかる後、例えば抵抗加熱法を用いた真空蒸着により、
ｎ形の導電性を与える不純物１５１例えばＧａ 、 Ｉ
ｎ 、 ＡＮ等を数人程度の厚さで前記高抵抗ＣｄＳｅ
膜ｌＯおよびフォトレジスト膜１４上に形成する（第３
図（Ｂ））。After that, for example, by vacuum deposition using a resistance heating method,
Impurity 151 that provides n-type conductivity, such as Ga, I
The high-resistance CdSe is coated with a thickness of several layers, such as AN, AN, etc.
Formed on the film 1O and the photoresist film 14 (third
Figure (B)).
アセトン中での超音波洗浄などにより前記フォトレジス
ト膜１４およびその上の不純物１５を除去したのち、前
記高抵抗ＣｄＳｅ膜１０上に付着している不純物１５に
非酸化性雰囲気中で２００℃−１時間程度の熱処理を施
こし、前記不純物１５を前記高抵抗ＣｄＳｅ膜１０中に
均一に拡散せしめ、前記高抵抗ＣｄＳｅ膜１０を低抵抗
で電気的に活性なＣｄＳｅ膜１１に変換する。After removing the photoresist film 14 and the impurities 15 thereon by ultrasonic cleaning in acetone, etc., the impurities 15 adhering to the high resistance CdSe film 10 are heated at 200° C.-1 in a non-oxidizing atmosphere. A heat treatment is performed for about an hour to uniformly diffuse the impurity 15 into the high-resistance CdSe film 10 and convert the high-resistance CdSe film 10 into a low-resistance, electrically active CdSe film 11.
この低抵抗ＣｄＳｅ＠ｌｌの抵抗率は１０３〜１０’Ω
・■であり、その移動度は、各多結晶粒界のｎ形に反転
していた電位障壁がｎ形の不純物により低減されるため
約２００ａｌｔ／ｖ、ｓと非常に大きな値になる。この
領域を薄膜トランジスタのチャネル領域として使用する
ため高ｇ１の素子が得られる（第３図（Ｃ））。The resistivity of this low resistance CdSe@ll is 103~10'Ω
・■, and its mobility becomes a very large value of about 200 alt/v,s because the potential barrier that was inverted to n-type at each polycrystalline grain boundary is reduced by n-type impurities. Since this region is used as a channel region of a thin film transistor, a high g1 element can be obtained (FIG. 3(C)).
この後５例えば周知のフォトリソグラフィ法を用いて所
定形状のＡＱ等からなるソース電極１２およびドレイン
電極１３を前記低抵抗ＣｄＳｅ膜１１を含む領域に形成
する（第３図（Ｄ））。Thereafter, a source electrode 12 and a drain electrode 13 made of AQ or the like having a predetermined shape are formed in a region including the low resistance CdSe film 11 using, for example, a well-known photolithography method (FIG. 3(D)).
このように本発明による薄膜トランジスタの製造方法に
よれば、ゲート絶縁膜９上にフォトレジスト膜を塗布す
ることは全く必要ないので、従来、フォトレジスト膜や
その中の不純物のゲート絶縁膜９上への付着あるいは所
定のパターン形成時の汚染などにより発生していた薄膜
トランジスタの特性上の問題点が全く無くなった。As described above, according to the method of manufacturing a thin film transistor according to the present invention, there is no need to apply a photoresist film on the gate insulating film 9, so that conventionally, the photoresist film and impurities therein are not coated on the gate insulating film 9. Problems in the characteristics of thin film transistors, which were caused by adhesion of particles or contamination during the formation of a predetermined pattern, have completely disappeared.
（発明の効果）
以上の説明から明らかなように１本発明によれば、フォ
トリングラフィ法を用いて作製した微細パターンの薄１
摸トランジスタの電気特性を、メタルマスク法により作
製した薄膜トランジスタの特性と同程度に容易に高める
ことができ、各種表示装置の駆動等に広く利用できるも
のである。(Effects of the Invention) As is clear from the above description, according to the present invention, a thin 1
The electrical characteristics of the simulated transistor can be easily improved to the same level as the characteristics of a thin film transistor manufactured by the metal mask method, and can be widely used for driving various display devices.
第１図は従来例の薄膜トランジスタの断面図、第２図は
本発明の薄膜トランジスタの断面図、第３図は本発明の
薄膜トランジスタの製造方法の一例を示す図である。
２．８ ・・ゲート電極、 ４，１１ ・・低抵抗率半
導体領域、１０ ・・高抵抗率半導体層、 ５゜１
２・・・ ソース電極、６．１３・・・ ドレイン電極
。
特許出願人 松下電器産業株式会社
第１図
第２図
第３図
（Ａ）
（Ｂ）FIG. 1 is a sectional view of a conventional thin film transistor, FIG. 2 is a sectional view of a thin film transistor of the present invention, and FIG. 3 is a diagram showing an example of a method for manufacturing a thin film transistor of the present invention. 2.8...Gate electrode, 4,11...Low resistivity semiconductor region, 10...High resistivity semiconductor layer, 5゜1
2... Source electrode, 6.13... Drain electrode. Patent applicant: Matsushita Electric Industrial Co., Ltd. Figure 1 Figure 2 Figure 3 (A) (B)
Claims (3)
膜を介して低抵抗率の所定形状の第１の半導体領域が形
成されており、前記ゲート絶縁膜上の前記第１の半導体
領域の周囲に高抵抗率の第２の半導体領域が形成されて
おり、少なくとも前記ゲート電極上の前記第１の半導体
領域上にソースおよびドレイン電極が形成されているこ
とを特徴とする薄膜トランジスタ。(1) A first semiconductor region of a predetermined shape with low resistivity is formed on at least a region including a gate electrode via a gate insulating film, and a first semiconductor region of a predetermined shape with low resistivity is formed around the first semiconductor region on the gate insulating film. A thin film transistor characterized in that a second semiconductor region having a high resistivity is formed, and a source and a drain electrode are formed at least on the first semiconductor region above the gate electrode.
純物を含んだＣｄＳｅ膜からなり、前記第２の半導体領
域がＣｄＳｅ膜からなることを特徴とする特許請求の範
囲第（１）項記載の薄膜トランジスタ。(2) Claim (1) characterized in that the first semiconductor region is made of a CdSe film containing an impurity giving n-type conductivity, and the second semiconductor region is made of a CdSe film. The thin film transistor described in Section 1.
ゲート絶縁膜を形成する工程、前記ゲート絶縁膜上に第
１の半導体層を形成した後、前記第１の半導体層上にフ
ォトレジスト膜を塗布し所定の形状のパターンを形成す
る工程、前記第１の半導体層および前記フォトレジスト
膜上にｎ形の導電型を与える不純物を付着した後、前記
フォトレジスト膜を除去する工程、前記不純物を前記第
１の半導体層中に拡散せしめ第２の半導体層を形成する
工程、少なくとも前記第２の半導体層を含む領域にソー
スおよびドレイン電極を形成する工程を有することを特
徴とする薄膜トランジスタの製造方法。(3) A step of forming a gate insulating film in a region including a gate electrode formed on an insulating substrate, after forming a first semiconductor layer on the gate insulating film, applying a photoresist on the first semiconductor layer. a step of applying a film to form a pattern of a predetermined shape; a step of depositing an impurity imparting n-type conductivity on the first semiconductor layer and the photoresist film, and then removing the photoresist film; A thin film transistor comprising the steps of: diffusing impurities into the first semiconductor layer to form a second semiconductor layer; and forming source and drain electrodes in at least a region including the second semiconductor layer. Production method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18813184A JPS6167268A (en) | 1984-09-10 | 1984-09-10 | Thin film transistor and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18813184A JPS6167268A (en) | 1984-09-10 | 1984-09-10 | Thin film transistor and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6167268A true JPS6167268A (en) | 1986-04-07 |
Family
ID=16218270
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18813184A Pending JPS6167268A (en) | 1984-09-10 | 1984-09-10 | Thin film transistor and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6167268A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6043113A (en) * | 1995-07-31 | 2000-03-28 | 1294339 Ontario, Inc. | Method of forming self-aligned thin film transistor |
-
1984
- 1984-09-10 JP JP18813184A patent/JPS6167268A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6043113A (en) * | 1995-07-31 | 2000-03-28 | 1294339 Ontario, Inc. | Method of forming self-aligned thin film transistor |
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