JPS6162227A - Digital tank circuit - Google Patents
Digital tank circuitInfo
- Publication number
- JPS6162227A JPS6162227A JP18479184A JP18479184A JPS6162227A JP S6162227 A JPS6162227 A JP S6162227A JP 18479184 A JP18479184 A JP 18479184A JP 18479184 A JP18479184 A JP 18479184A JP S6162227 A JPS6162227 A JP S6162227A
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- adder
- output
- input
- bit
- delay means
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- Analogue/Digital Conversion (AREA)
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Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は入力したアナログ信号から単一周波数成分を抽
出するディジタルタンク回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a digital tank circuit that extracts a single frequency component from an input analog signal.
従来ディジタルタンク回路は、アナログ信号をサンプリ
ングされた２進符号に変える手段と、加算器１乗算器、
および遅延器を含むディノクルフィルタとから構成され
ている。しかしながらディソタルフィルタに用いられる
乗算器は構成が複雑でらる上４個を必要とするため、装
置価格が高くなる欠点を有していた。またディノタルフ
ィルタの利得特性を上げようとして中心周波数でのピー
クを鋭くしようとすればする程１乗算器によシ発生する
量子化誤差の影響が無視できなくなるという欠点かぎっ
た。Conventional digital tank circuits include a means for converting an analog signal into a sampled binary code, an adder 1 multiplier,
and a dinocle filter including a delay device. However, the multipliers used in the disortal filter have a complicated structure and require four multipliers, which has the disadvantage of increasing the cost of the device. Another disadvantage is that the more you try to sharpen the peak at the center frequency in order to improve the gain characteristics of the dinotal filter, the more the influence of the quantization error generated by the 1 multiplier cannot be ignored.
したがって本発明の１つの目的は２乗算器を用いなくて
済むディジタルタンク回路を得ようとするものである。Therefore, one object of the present invention is to provide a digital tank circuit that does not require the use of squaring multipliers.
また本発明の他の目的は、量子化誤差の少ない ：′
＋１ディジタルタンク回路を得ようとするものでちる。Another object of the present invention is to reduce quantization errors:'
+1 If you are trying to get a digital tank circuit, it will fail.
本発明は上記の目的な達成するために、・す゛ツノ′。 The present invention has been made to achieve the above objects.
リング周波数を適当に選んで乗算器を使わなくて済むよ
うに改良したものであり、又前記の改良した部分に量子
化誤差相殺回路を付加したものである。This is an improvement that eliminates the need for a multiplier by appropriately selecting the ring frequency, and a quantization error canceling circuit is added to the improved part.
すなわち本発明によれば１本発明の第１の実施例の（）
」７成を示す第１図を参照して、アナログ信号を周波数
１８でサンプリングされた２進符号に変える手段と、遅
延時間が前記サンプリングの周波数の周期１／ｆｓの２
つ分に相当する遅延手段を用いて前記２進符号から中心
周波数ｆｏのタイミングの抽出を行うディヅタルフィル
タとから成るタンク回路において、前記サンプリングの
周波数ｆを前記中心周、波数ｆの４倍に選び、且つ前記
ディノタルフィルタ（３３）が、ｎを正の整数と１−で
、直列に同じ向きに配置され中間点が前記遅延手段（３
９゜４０）の入力に接続されている第１および第２の加
算器（４１，４２）と、出力が前記第１の加算器（４１
）の一方の入力に接続されている第３の加算器（４３）
と、前記２進符号を受け出力を前記第１の加算器（＝１
１）の他の入力に送るｎビット右シフト（３７）と。That is, according to the present invention, (1) of the first embodiment of the present invention
Referring to FIG. 1, which shows a system for converting an analog signal into a binary code sampled at a frequency of 18, and a delay time of 1/fs of the period of said sampling frequency,
and a digital filter that extracts the timing of the center frequency fo from the binary code using delay means equivalent to 1.5 times, the sampling frequency f is set to 4 times the center frequency and the wave number f. and the dinotal filter (33) is arranged in series in the same direction, with n being a positive integer and 1-, and the midpoint is selected as the delay means (33).
first and second adders (41, 42) connected to the inputs of the first adder (41, 40);
) a third adder (43) connected to one input of the
, the binary code is received and the output is sent to the first adder (=1
1) with an n-bit right shift (37) sent to the other input.
前記遅延手段（３９、４０）の出力を共通に受け、出力
を前記第３の加算器（４３）７）２つの入力にそれぞれ
送るビット反転（３４）およびｎビット右シフトＣ３５
）の並列回路と、前記遅延手段（３９、４０）の出力を
受け出力を前記第２の加算器（４２）に送る１ビット右
ノフ）（３６）と、前記第２の加算器（４２）の出力を
受け出力が前記中心周波数ｆｏのタイミングとなる１ビ
ット右シフト（３８）とを有していることを特徴とする
デイヅタルタンク回路が得られる。bit inversion (34) and n-bit right shift C35 which commonly receives the output of the delay means (39, 40) and sends the output to the two inputs of the third adder (43) 7);
), a 1-bit right nof (36) that receives the output of the delay means (39, 40) and sends the output to the second adder (42), and the second adder (42). A digital tank circuit is obtained which is characterized in that it receives the output of , and has a 1-bit right shift (38) whose output is at the timing of the center frequency fo.
また本発明によれば、第１図および第２の実施例の構成
を示す第２図を併せ参照して、前記の第１の発明による
デイノタルタンク回路を主体とし。Further, according to the present invention, with reference to FIG. 1 and FIG. 2 showing the configuration of the second embodiment, the deinotal tank circuit according to the first invention is mainly used.
このタンク回路の遅延手段（３９、４０）の出力とｎビ
ット右シフト（３５ンの入力との間に１両者に接続され
た第４の加算器（４４）と、この第４の加算器（・１４
）の出力を入力とする下位ｎビット切出しく４８）。A fourth adder (44) is connected between the output of the delay means (39, 40) of this tank circuit and the input of the n-bit right shift (35);・14
) as input and extracts the lower n bits 48).
ビット反転（４７）、および前記遅延手段（３９、４Φ
と実質的に同じ遅延時間を持ち、出力を前記第・ｔの加
算器（４りの入力に送る付加遅延手段（Ｌ ５ ＋、
ｉｌ ６）を記載の順に配置した直列回路を付加したこ
とな特徴とするディジタルタンク回路が得られる。bit inversion (47), and the delay means (39, 4Φ
additional delay means (L 5 +,
A digital tank circuit characterized by adding a series circuit in which il 6) is arranged in the order described is obtained.
本発明は以上のような構成により、４つの複雑な構成の
乗算器を簡単な構成のビットシフト回路及びビット反転
回路各１つで置き換えることができて装置構成が非常に
簡略化され、また付加回路により出力中に含まれる量子
化誤差成分が効果的に低減される。With the above configuration, the present invention can replace four multipliers with a complex configuration with one each of a bit shift circuit and a bit inversion circuit with a simple configuration, greatly simplifying the device configuration. The circuit effectively reduces the quantization error component contained in the output.
第３図は従来技術によるディヅタルタンク回路の４Ｒ成
を示した図である。信号ａは抽出すべき中心周波数ｆの
成分を強く含むように予め変換を施した高周波アナログ
信号である。ここに前記の変換とは、バイポーラ信号の
ときは全波整流を掛け。FIG. 3 is a diagram showing a 4R configuration of a digital tank circuit according to the prior art. The signal a is a high frequency analog signal that has been converted in advance so that it strongly contains the component of the center frequency f to be extracted. Here, the conversion mentioned above involves applying full-wave rectification in the case of a bipolar signal.
ＮＲＺ信号の場合は微分したあと全波整流を掛けること
を意味する。こうして得られた高周波アナログ信号は比
較器１１に入力され、スライスされて０−１信号に変換
され、さらにサンプラ１２によシ周波数ｆでサンプリン
グされ、ディノタルフィルタ１３に入力される。なお前
記の代υに高周波アナログ信号をサンプラでサンプリン
グしてからＡ／Ｄコンバータで量子化する方法もある。In the case of an NRZ signal, this means performing full-wave rectification after differentiation. The high frequency analog signal thus obtained is input to a comparator 11, sliced and converted into a 0-1 signal, further sampled at a frequency f by a sampler 12, and input to a dinotal filter 13. Note that there is also a method in which the high frequency analog signal is sampled using a sampler and then quantized using an A/D converter.
ただφコンバータは構造が複雑である。However, the φ converter has a complicated structure.
ディノタルフィルター３はａｌ 、ａ２ 、ａ３
。Dinotal filter 3 is al, a2, a3
.
ａ４をそれぞれ乗算係数とする乗算器１４，１５゜１６
．１７とｌｃ＋ｄだけそれぞれビットのシフトを行うビ
ットシフト１８，１９と、サンプリング周期１／ｆを遅
延時間とする遅延器２１．２２と、加算器２２，２３，
２４．２５とから成っている。この回路では４つの乗算
器１４〜１７の乗算係数を調整してタンク回路の中心周
波数ｆでデイノタルフィルター３の利得特性が鋭いピー
クを持つように設計される。従って従来の装置では。Multipliers 14 and 15゜16 each using a4 as a multiplication coefficient
．． bit shifters 18 and 19 that shift bits by 17 and lc+d, delayers 21 and 22 whose delay time is the sampling period 1/f, adders 22 and 23,
It consists of 24.25. This circuit is designed so that the gain characteristics of the deinotal filter 3 have a sharp peak at the center frequency f of the tank circuit by adjusting the multiplication coefficients of the four multipliers 14 to 17. Therefore in conventional equipment.
先に述べたように、複雑な構成の乗算器を４つも必要と
し、又乗算器によシ発生する量子化誤差の影響が無視出
来なくなる。 ｔ〔本え、。As mentioned above, as many as four multipliers with complicated configurations are required, and the influence of quantization errors generated by the multipliers cannot be ignored. t [Honoe,.
実□ｆｌｌ ） ’１
第１図は本発明の一実施例の構成をあられした図である
。高周波アナログ信号ａが比較器３１で０−１信号に変
換され、サンプラ３２でサングリ般に２次ＩＩＲフィル
タの伝達函数は、第７図のディノタルフィルタ１３の構
成をもとにしてあられすと。Real □ full ) '1
FIG. 1 is a diagram showing the configuration of an embodiment of the present invention. The high frequency analog signal a is converted into a 0-1 signal by the comparator 31, and the sampler 32 converts it into a 0-1 signal.In general, the transfer function of the second-order IIR filter is calculated based on the configuration of the dinotal filter 13 shown in FIG. .
であられされるが、この伝達函数においてサンプリング
周波数１８をタンク回路の中心周波数ｆｏ０４倍に選ん
です、＝０とし１周波数０ 、 ｆｓ／２Ｃ２ｆｏ）の
２点に零点を設けてａ、＝０．ａ２＝−１とし。In this transfer function, the sampling frequency 18 is selected to be 4 times the center frequency of the tank circuit, fo0, = 0, and zero points are provided at two points, 1 frequency 0, fs/2C2fo), and a, = 0. Let a2=-1.
さらにｂ２ ”−１＋２−ｎの形にすると、このときの
伝達函数Ｈ（７，）は
で与えられる。Furthermore, if it is made into the form b2''-1+2-n, the transfer function H(7,) in this case is given by.
ディノタルフィルタ３２の構成は上記の伝達函数をその
まま実現しているもので８分母の一１＋２″′ｎの演算
は、ビット反転３４とｎビット右シフトはビット反転３
６で＋ ２−ｎ−’の演算はｎビット右シフト３７と１
ビット右シフト３８でそれぞれ行っている。遅延器３９
と４０は第１図の遅延器２０．２１と全く同じであって
、いずれもサンプリング周期１／ｆｓをその遅延量とし
ている。加算器４１．４２．４３については特に説明す
る必要はないであろう。The configuration of the dinotal filter 32 directly realizes the above transfer function, and the operation of 8 denominator 1 + 2'''n is performed by bit inversion 34 and n-bit right shift by bit inversion 3.
In 6, +2-n-' operation is n-bit right shift 37 and 1
Each bit is shifted to the right by 38 bits. delay device 39
and 40 are exactly the same as the delay devices 20 and 21 in FIG. 1, and both have a sampling period of 1/fs as their delay amount. Adders 41, 42, 43 do not require any special explanation.
以上の説明から分るように、第【図の本発明によるデソ
タルタンク回路では、複雑な構成の乗算器を用いること
なしに第４図の従来の回路と全く同じ動作を行うことが
できる。As can be seen from the above description, the desotal tank circuit according to the present invention shown in FIG. 4 can perform exactly the same operation as the conventional circuit shown in FIG. 4 without using a complex multiplier.
第２図は本発明の第２の実施例の構成をあられした図で
ある。この回路が第１図の回路と異る点は、ｎビット右
シフト３５の入力端に加ｇ器４ｔ１を挿入し、この加算
器を含めて遅延器４５．４６゜ビット反転器４７．及び
下位ｎビット切出し４８で構成した量子化誤差相殺悸倫
回路４９を設けたことである。この付加回路において、
ｎビット右シフト３５の動作の際に切りすてる量（量子
化誤の出力は２ｎｅ（ｔ）であられされ、この量のビッ
トを反転した量−２ｎｅ（ｔ）が２段の遅延回路４４と
４５を通って加算器４４に加えられ、フィードバックさ
れる。このとき、ｅ（ｔ）を入力とみたときの伝達関数
Ｈｃｉｚｌは。FIG. 2 is a diagram showing the configuration of a second embodiment of the present invention. The difference between this circuit and the circuit shown in FIG. 1 is that an adder 4t1 is inserted at the input end of the n-bit right shifter 35, and including this adder, a delay unit 45.46° bit inverter 47. and a quantization error cancellation circuit 49 consisting of a lower n bit cutout 48. In this additional circuit,
The amount to be cut off during the operation of the n-bit right shift 35 (the output of quantization error is 2ne(t), and the amount obtained by inverting the bits of this amount - 2ne(t) is the amount to be cut off by the two-stage delay circuit 44. 45 and is fed back to the adder 44. At this time, the transfer function Hcizl when e(t) is considered as an input is:
で与えられ。given by.
ＩＩ ｌ（ｃ ＩＩ〜＝ＩＴ挿、 １Ｈｅ（ｚ）１４は
たかだかΔ／２（Δ＝２ 、ｂは小数点以下のビット数
）なので、出力中の誤差成分の］辰幅はΔ／２程度とな
る。II l(c II~=IT insertion, 1He(z)14 is at most Δ/2 (Δ=2, b is the number of bits below the decimal point), so the width of the error component in the output is about Δ/2. Become.
一方、付加回路を設けない場合、ｎビット右シフト３５
の出力の誤差は最大２ｎ倍に増幅され。On the other hand, if no additional circuit is provided, n-bit right shift 35
The error in the output of is amplified by a maximum of 2n times.
出力中の誤差成分の振幅は２ ｎＭ′２程度となる。す
なわち、付加回路のない場合は出力の下位ｎ＋１ビット
が誤差を含むこととなるのに対し、付加回路をつけると
、下位１ビットのみに抑えられろ。The amplitude of the error component in the output is approximately 2 nM'2. That is, if there is no additional circuit, the lower n+1 bits of the output will contain an error, but with the additional circuit, the error can be suppressed to only the lower 1 bit.
以上の説明から分るように、こ、の付加回路を設けるこ
とにより量子化誤差の成分が大きく相殺される。従って
第３図のデジタルタンク回路は１乗算器を用いないこと
によって回路構成が筒型になることと相俟って、タンク
回路として極めて優れた特性を有していることになる。As can be seen from the above explanation, by providing this additional circuit, the quantization error component is largely canceled out. Therefore, the digital tank circuit shown in FIG. 3 has extremely excellent characteristics as a tank circuit, in combination with the fact that the circuit configuration is cylindrical by not using a 1 multiplier.
第１図は１本発明の一実施例の構成を示す図。
第２図は本発明の第２の実施例の構成を示す図。
第３図は従来のディジタルタンク回路構成を示す図であ
る。
記号の説明：１４＋１５．１６．１７は乗０２３゜２０
．２１は遅延器、３１は比較器、３２はサンプラ、３３
はデイノタルフィルタ、３４はビット反転、３５はｎビ
ット右シフト、３６はビット反 ’Ｊ、 ｔｉ転、３７
はｎビット右シフト、３８は１ビット右シフト、３９．
４０は遅延回路（合わせて遅延手段）、’４５．４６は
遅延回路（合わせて付加遅延手段）、４７はビット反転
、４８は下位ｎビット切出し、４９は量子化誤差相殺神
喘回路をそれぞれあられしている。
手続補正書（自発） ＜
昭和６０年１２月３日FIG. 1 is a diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a diagram showing the configuration of a second embodiment of the present invention. FIG. 3 is a diagram showing a conventional digital tank circuit configuration. Symbol explanation: 14+15.16.17 is the power 023°20
．． 21 is a delay device, 31 is a comparator, 32 is a sampler, 33
is a deinotal filter, 34 is bit inversion, 35 is n-bit right shift, 36 is bit inversion 'J, ti inversion, 37
is an n-bit right shift, 38 is a 1-bit right shift, 39.
40 is a delay circuit (combined as a delay means), '45.46 is a delay circuit (combined as an additional delay means), 47 is a bit inversion, 48 is a lower n bit cutout, and 49 is a quantization error canceling circuit. are doing. Procedural amendment (voluntary) < December 3, 1985
Claims (2)
た２進符号に変える手段と、遅延時間が前記サンプリン
グの周波数の周期１／ｆ＿ｓの２つ分に相当する遅延手
段を用いて前記２進符号から中心周波数ｆ＿ｏのタイミ
ングの抽出を行うディジタルフィルタとから成るタンク
回路において、前記サンプリングの周波数ｆ＿ｓを前記
中心周波数ｆ＿ｏの４倍に選び、且つ前記ディジタルフ
ィルタが、ｎを正の整数として、直列に同じ向きに配置
され中間点が前記遅延手段の入力に接続されている第１
および第２の加算器と、出力が前記第１の加算器の一方
の入力に接続されている第３の加算器と、前記２進符号
を受け出力を前記第１の加算器の他の入力に送るｎビッ
ト右シフトと、前記遅延手段の出力を共通に受け、出力
を前記第３の加算器の２つの入力にそれぞれ送るビット
反転およびｎビット右シフトの並列回路と、前記遅延手
段の出力を受け出力を前記第２の加算器に送る１ビット
右シフトと、前記第２の加算器の出力を受け出力が前記
中心周波数ｆ＿ｏのタイミングとなる１ビット右シフト
とを有していることを特徴とするディジタルタンク回路
。(1) Using means for converting an analog signal into a binary code sampled at a frequency f_s, and a delay means whose delay time corresponds to two cycles of the sampling frequency, 1/f_s, In a tank circuit consisting of a digital filter that extracts the timing of a frequency f_o, the sampling frequency f_s is selected to be four times the center frequency f_o, and the digital filters are connected in series in the same direction, where n is a positive integer. a first one located at and having an intermediate point connected to the input of said delay means;
and a second adder, a third adder having an output connected to one input of the first adder, and a third adder receiving the binary code and transmitting the output to the other input of the first adder. a bit inversion and n-bit right shift parallel circuit that commonly receives the output of the delay means and sends the outputs to two inputs of the third adder, respectively; and an output of the delay means. and a 1-bit right shift that receives the output of the second adder and sends the output to the second adder, and a 1-bit right shift that receives the output of the second adder and causes the output to be at the timing of the center frequency f_o. Features a digital tank circuit.
た２進符号に変える手段と、遅延時間が前記サンプリン
グの周波数の周期１／ｆ＿ｓの２つ分に相当する遅延手
段を用いて前記２進符号から中心周波数ｆ＿ｏのタイミ
ングの抽出を行うディジタルフィルタとから成るタンク
回路において、前記サンプリングの周波数ｆ＿ｓを前記
中心周波数ｆ＿ｏの４倍に選び、且つ前記ディジタルフ
ィルタが、ｎを正の整数として、直列に同じ向きに配置
され中間点が前記遅延手段の入力に接続されている第１
および第２の加算器と、出力が前記第１の加算器の一方
の入力に接続されている第３の加算器と、前記２進符号
を受け出力を前記第１の加算器の他の入力に送るｎビッ
ト右シフトと、前記遅延手段の出力を受け出力を前記第
３の加算器の一方の入力に送るビット反転および前記遅
延手段の出力を第４の加算器を介して受け出力を前記第
３の加算器の他方の入力に送るｎビット右シフトの並列
回路と、前記第４の加算器の出力を入力とする下位ｎビ
ット切出し、ビット反転、および前記遅延手段と実質的
に同じ遅延時間を持ち、出力を前記第４の加算器の入力
に送る付加遅延手段を記載の順に配置した直列回路と、
前記遅延手段の出力を受け出力を前記第２の加算器に送
る１ビット右シフトと、前記第２の加算器の出力を受け
出力が前記中心周波数ｆ＿ｏのタイミングとなる１ビッ
ト右シフトとを有していることを特徴とするディジタル
タンク回路。(2) converting the analog signal into a binary code sampled at a frequency f_s, and using a delay means whose delay time corresponds to two cycles of the sampling frequency, 1/f_s; In a tank circuit consisting of a digital filter that extracts the timing of a frequency f_o, the sampling frequency f_s is selected to be four times the center frequency f_o, and the digital filters are connected in series in the same direction, where n is a positive integer. a first one located at and having an intermediate point connected to the input of said delay means;
and a second adder, a third adder having an output connected to one input of the first adder, and a third adder receiving the binary code and transmitting the output to the other input of the first adder. n-bit right shifting, receiving the output of the delay means and sending the output to one input of the third adder, and receiving the output of the delay means through a fourth adder and sending the output to the third adder. A parallel circuit for right-shifting n bits to be sent to the other input of the third adder, cutting out the lower n bits using the output of the fourth adder as input, inverting the bits, and delaying substantially the same as the delay means. a series circuit having additional delay means arranged in the order listed and having an output time and sending an output to the input of the fourth adder;
A 1-bit right shift that receives the output of the delay means and sends the output to the second adder, and a 1-bit right shift that receives the output of the second adder and causes the output to be at the timing of the center frequency f_o. A digital tank circuit characterized by:
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18479184A JPS6162227A (en) | 1984-09-04 | 1984-09-04 | Digital tank circuit |
| DE8585111106T DE3584864D1 (en) | 1984-09-04 | 1985-09-03 | DIGITAL VIBRATION CIRCUIT. |
| EP85111106A EP0174593B1 (en) | 1984-09-04 | 1985-09-03 | Digital tank circuit |
| US06/772,537 US4755961A (en) | 1984-09-04 | 1985-09-04 | Digital tank circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18479184A JPS6162227A (en) | 1984-09-04 | 1984-09-04 | Digital tank circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6162227A true JPS6162227A (en) | 1986-03-31 |
| JPH0314364B2 JPH0314364B2 (en) | 1991-02-26 |
Family
ID=16159353
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18479184A Granted JPS6162227A (en) | 1984-09-04 | 1984-09-04 | Digital tank circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6162227A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02228118A (en) * | 1989-02-28 | 1990-09-11 | Toshiba Corp | Cyclic type digital filter |
| JPH03263910A (en) * | 1990-03-14 | 1991-11-25 | Fujitsu Ltd | Iir filter |
-
1984
- 1984-09-04 JP JP18479184A patent/JPS6162227A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02228118A (en) * | 1989-02-28 | 1990-09-11 | Toshiba Corp | Cyclic type digital filter |
| JPH03263910A (en) * | 1990-03-14 | 1991-11-25 | Fujitsu Ltd | Iir filter |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0314364B2 (en) | 1991-02-26 |
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