JPS6161470A - Nonvolatile semiconductor memory device - Google Patents
Nonvolatile semiconductor memory deviceInfo
- Publication number
- JPS6161470A JPS6161470A JP18280984A JP18280984A JPS6161470A JP S6161470 A JPS6161470 A JP S6161470A JP 18280984 A JP18280984 A JP 18280984A JP 18280984 A JP18280984 A JP 18280984A JP S6161470 A JPS6161470 A JP S6161470A
- Authority
- JP
- Japan
- Prior art keywords
- floating gate
- side wall
- tunnel
- film
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract 7
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 239000012535 impurity Substances 0.000 claims abstract 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052710 silicon Inorganic materials 0.000 abstract description 7
- 239000010703 silicon Substances 0.000 abstract description 7
- 230000005684 electric field Effects 0.000 abstract description 4
- 239000010408 film Substances 0.000 description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 230000014759 maintenance of location Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 2
- 238000001947 vapour-phase growth Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、浮遊ゲートと１ｕｕ御ゲートを有する不揮発
性メモリメモリ装置に係り、侍に′に気的に書き換え可
能なメモリ装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a non-volatile memory device having a floating gate and a 1UU control gate, and relates to a memory device that can be permanently rewritten.
浮遊ゲートを有する電気的に書き換え可能な不揮発性メ
モリとして、例えば第３図に示すものが知られている。For example, the one shown in FIG. 3 is known as an electrically rewritable nonvolatile memory having a floating gate.
第３図の（ａ）は平面図であり、（ｂ）ｌ（Ｃ）はそれ
ぞれ（ａ）のＡ−Ａ’ 、 Ｂ−Ｂ’断面図である。Ｐ
型シリコン基板（１１）に形成されたｎ中層（１２１）
（１２２） 、これらのｎ中層（１２１）＊（１２２
）間に絶縁膜を介して積層された浮遊ゲートμｊとこの
浮遊ゲート（１３上に絶縁膜を介して積層された制御ゲ
ート（１４）によシメモリトランジスタが溝成されてい
る。またｎ中層（１２２）、（１２３とこれらのｎ中層
（１２２） 、 （１２３）間に、Ｓａ膜を介して形成
されたゲート電極霞により選択用トランジスタが溝成さ
れている。記憶内容の書き換えはｎ中層（１２２）と連
続的に形成されたｎ中層（１２４）上にトンネル電流の
流れうる薄い絶縁膜σηを介して浮遊ゲート１Ｌ３ｔ−
延在させて浮遊ゲートＵりとｎ中層（１２４）間の電荷
の授受により行なわれる。Ｈはフィールド絶縁膜である
。FIG. 3(a) is a plan view, and FIG. 3(b) and (C) are sectional views taken along line AA' and line BB' in FIG. 3(a), respectively. P
n middle layer (121) formed on a type silicon substrate (11)
(122), these n middle layers (121)*(122
) and a control gate (14) stacked on the floating gate (13) with an insulating film interposed between them. Between (122), (123) and these n-middle layers (122) and (123), a selection transistor is formed by a gate electrode haze formed through a Sa film.Rewriting of the memory contents is possible in the n-middle layer. The floating gate 1L3t-
This is done by extending the floating gate U and receiving and receiving charges between the N middle layer (124). H is a field insulating film.
この様な構造のメモＩＪ ）ランジスタにおいては。In a memo IJ) transistor with such a structure.
ｎ中層（１２４）と浮遊ゲートｕ３）間で電子の注入及
び放出を行うため、トンネル絶縁膜は７）を微細化する
事が困難であった。従って、書き込み条件において、低
いパルス電圧で高速に書き換えを可能とする素−子の実
現には限度があシ、記憶素子自体の微細化にも限界があ
った。また記憶保持を向上する上でも、トンネル領域は
小さい方が望ましい。Since electrons are injected and emitted between the n-middle layer (124) and the floating gate u3), it has been difficult to miniaturize the tunnel insulating film 7). Therefore, under writing conditions, there is a limit to the realization of an element that allows high-speed rewriting with a low pulse voltage, and there is also a limit to miniaturization of the memory element itself. Furthermore, in order to improve memory retention, it is desirable that the tunnel region be small.
本発明は上記の点に鑑みなされたもので、トンネル領域
を小さくシ、より高速に書き換えが可能で、素子の微細
化に適し、記憶保持を向上させる記憶素子を提供する事
を目的としている。The present invention has been made in view of the above points, and an object of the present invention is to provide a memory element that has a smaller tunnel region, can be rewritten at higher speed, is suitable for miniaturization of the element, and improves memory retention.
本発明では例えば第１図に示す如く、浮遊ゲートαｊの
側壁に残置されたトンネル絶縁膜αＩｙ＆：介して、突
起部αｅが側壁部に沿って延在し、この突起部（１ｅが
ｎ中層（１２２）と直接、接触している。電子の授受は
浮遊ゲート（１３の側壁部におけるトンネル絶縁膜ｆｌ
ｌ全通して行なわれ、トンネル領域が占める面積は浮遊
ゲートａｓの膜厚に依存するため、トンネル領域の縮小
が可能となる。従ってトンネル領域の縮小化に伴う電界
集中によシ、低い書き込み電圧で高速に書き換えが可能
となる。！、たトンネル酸化膜（ＬｌがＰ型シリコン基
板（ｉυに対して垂直方向に延在するため、記憶素子に
おけるトンネル絶縁膜Ｕの占める面積が極めて小となり
、記憶素子の微細化に適する。In the present invention, for example, as shown in FIG. 1, a protrusion αe extends along the sidewall via the tunnel insulating film αIy &: left on the sidewall of the floating gate αj, and this protrusion (1e) extends from the n middle layer ( 122).Electrons are exchanged through the tunnel insulating film fl on the side wall of the floating gate (13).
Since the area occupied by the tunnel region depends on the film thickness of the floating gate AS, the tunnel region can be reduced. Therefore, due to the electric field concentration caused by the reduction of the tunnel region, high-speed rewriting is possible with a low write voltage. ! Since the tunnel oxide film (L1) extends perpendicularly to the P-type silicon substrate (iυ), the area occupied by the tunnel insulating film U in the memory element becomes extremely small, making it suitable for miniaturization of the memory element.
本発明によればトンネル領域を局小化する事ができるた
め、それに伴う電界集中ばよシ、従来の書き込み条件よ
シも、より低い電圧で書き換えの高速化を図る事ができ
、記憶保持特性を向上させなり、又、シリコン基板に対
してトンネル領域が垂直方向に延在するため、記憶素子
の微細化が出来る。According to the present invention, since the tunnel region can be localized, the electric field concentration associated with it can be reduced, the rewriting speed can be increased with a lower voltage than the conventional write conditions, and the memory retention characteristics can be increased. Furthermore, since the tunnel region extends perpendicularly to the silicon substrate, the memory element can be miniaturized.
次に本発明′ｔ−第１図（ａ） 、 （ｂ） 、第２図
（ａ） 〜（ｄ） Ｋ示す。第２図（ａ）に示す如＜、
Ｐａシリコン基板住υ上に、例えば酸化膜住ηをシリコ
ン露出面全面に３０ＣＩＡ成長させ、その上に、気相成
長により多結晶ケイ素よシ成る選択用トランジスタのゲ
ート電極（Ｌ５１及び浮遊ゲート（Ｌ３ｔ−マスク材ｏ
１）を用いて所望の形に形成する。賭はフィールド絶縁
膜である。次に（ｂ）に示す如く、酸化膜を表面に例え
ば２００Ａ形成し、異方性エツチング（反応性イオンエ
ツチング法）により、ゲート電極α９及び浮遊ゲート１
贈の側壁部以外は酸化膜を除去する。次に（Ｃ）に示す
如く、表面に多結・晶ケイ素層（２Ｇ’を堆積し、リン
拡散を行なった後、アニール等によシ、Ｐ型シリコン基
板（ｌυにｎ中層（１２１）〜（１２３）を形成する。Next, the present invention is shown in FIGS. 1(a), (b) and 2(a) to (d). As shown in Figure 2(a),
For example, an oxide film η is grown for 30 CIA on the entire exposed silicon surface on a Pa silicon substrate, and on top of that, a gate electrode (L51) and a floating gate (L3t) of a selection transistor made of polycrystalline silicon are grown by vapor phase growth. -Mask material o
1) into the desired shape. The bet is field insulation. Next, as shown in (b), an oxide film of, for example, 200 Å is formed on the surface, and anisotropic etching (reactive ion etching method) is performed to form the gate electrode α9 and the floating gate 1.
The oxide film is removed except for the sidewalls of the base. Next, as shown in (C), a polycrystalline silicon layer (2G') is deposited on the surface and phosphorus is diffused. (123) is formed.
次に異方性エツチング（反応性イオン・エツチング法）
によシゲート電極霞及び浮遊ゲートａ３の側壁部を残し
て、多結晶ケイ素を除去する。この時、ｎ中層（１２２
）と結合し友突起部ｕｅが形成される。Next, anisotropic etching (reactive ion etching method)
The polycrystalline silicon is removed, leaving behind the gate electrode haze and the side wall of the floating gate a3. At this time, the n middle layer (122
) to form a friend protrusion ue.
それ以外のゲート電極α９及び、浮遊ゲートＱ３の側壁
部に残置した多結晶ケイ素は、突起部１ｅをマスク材で
マスクした後５等方性エツチング（ドライ・エツチング
法）によシ除去する（ｄ）。以降は公知の如く、気相成
長により多結晶ケイ素よシ成る制御ゲートを積層し、素
子を形成する。The polycrystalline silicon remaining on the side walls of the other gate electrode α9 and the floating gate Q3 is removed by isotropic etching (dry etching method) after masking the protrusion 1e with a mask material (5). ). Thereafter, as is well known, a control gate made of polycrystalline silicon is laminated by vapor phase growth to form an element.
この素子は、例えばｎ中層（１２２）がｏ■、浮遊ゲー
トに容量結合する制御ゲートＩが２０Ｖの時電子が注入
され、夫々２０Ｖ、ＯＶの時電子が放出されて消去とな
る。注入、放出は浮遊ゲートの側壁部のトンネル絶縁膜
においてのみ生じ、その面積は小さい念め保持性能が高
く、また電界集中によｐ高速な書き換えに有効である。In this element, for example, electrons are injected when the n middle layer (122) is o2 and the control gate I capacitively coupled to the floating gate is 20V, and electrons are emitted and erased when the voltage is 20V and OV, respectively. Injection and emission occur only in the tunnel insulating film on the side wall of the floating gate, and its area is small, providing high retention performance and effective for high-speed rewriting due to electric field concentration.
第１図（ａ） （ｂ）は本発明の詳細な説明するための
平面図及び断面図、第２図（ａ）〜（ｄ）は本発−〇−
実施例を示す断面図、第Ｓ図（ａ）は従来例を説明する
ための平面図、 （ｂ）（Ｃ）はその断面図である。
図において、１１・・・Ｐ型シリコン基板、１３・・・
浮遊ゲート、１４・・・制御ゲート、１５・・・ゲート
電極、１６・・・突起部、１７・・・ゲート絶縁膜、１
８・・・フィールド絶縁膜、１９・・・トンネル酸化膜
、２０・・・多結晶ケイ素薄膜、２１・・・マスク材、
１２１〜１２４・・・ｎ中層。
代理人 弁理士 則近憲佑（ほか１名）第 １ 図
（ｄ）
第 ２ 図
（α）
図FIGS. 1(a) and 1(b) are plan views and sectional views for explaining the present invention in detail, and FIGS. 2(a) to (d) are the present invention.
A cross-sectional view showing the embodiment, FIG. S (a) is a plan view for explaining a conventional example, and FIGS. In the figure, 11...P-type silicon substrate, 13...
floating gate, 14... control gate, 15... gate electrode, 16... protrusion, 17... gate insulating film, 1
8... Field insulating film, 19... Tunnel oxide film, 20... Polycrystalline silicon thin film, 21... Mask material,
121-124...n middle layer. Agent Patent attorney Kensuke Norichika (and one other person) Figure 1 (d) Figure 2 (α) Figure
Claims (1)
た制御ゲートを有する電気的書き換え可能な不揮発性半
導体記憶装置において、半導体基体表面に形成された前
記半導体基板と逆導電型の高濃度不純物領域上に導電性
の突起部がトンネル絶縁膜を介して前記浮遊ゲートの側
壁部に沿って延在し、前記浮遊ゲートヘの電荷の授受は
前記導電性の突起部との間で前記トンネル絶縁膜を介し
て行なわれる事を特徴とする不揮発性半導体記憶装置。In an electrically rewritable nonvolatile semiconductor memory device having a floating gate and a control gate capacitively coupled to the floating gate, a highly concentrated impurity region of a conductivity type opposite to that of the semiconductor substrate formed on the surface of the semiconductor substrate is provided. A conductive protrusion extends along the side wall of the floating gate via a tunnel insulating film, and charge is transferred to and from the floating gate via the tunnel insulating film. A non-volatile semiconductor memory device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18280984A JPS6161470A (en) | 1984-09-03 | 1984-09-03 | Nonvolatile semiconductor memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18280984A JPS6161470A (en) | 1984-09-03 | 1984-09-03 | Nonvolatile semiconductor memory device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6161470A true JPS6161470A (en) | 1986-03-29 |
Family
ID=16124814
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18280984A Pending JPS6161470A (en) | 1984-09-03 | 1984-09-03 | Nonvolatile semiconductor memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6161470A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01196876A (en) * | 1988-02-02 | 1989-08-08 | Matsushita Electron Corp | Manufacture of semiconductor storage device |
| JPH01211979A (en) * | 1988-02-19 | 1989-08-25 | Toshiba Corp | Nonvoltaile semiconductor memory |
| US6845935B2 (en) | 2001-11-20 | 2005-01-25 | Fuji Photo Film Co., Ltd. | Recording tape cartridge |
| US6988686B2 (en) | 2001-11-20 | 2006-01-24 | Fuji Photo Film Co., Ltd. | Recording tape cartridge |
| US7021579B2 (en) | 2001-10-15 | 2006-04-04 | Fuji Photo Film Co., Ltd. | Recording tape cartridge |
| US7051968B2 (en) | 2001-10-15 | 2006-05-30 | Fuji Photo Film Co., Ltd. | Recording tape cartridge |
-
1984
- 1984-09-03 JP JP18280984A patent/JPS6161470A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01196876A (en) * | 1988-02-02 | 1989-08-08 | Matsushita Electron Corp | Manufacture of semiconductor storage device |
| JPH01211979A (en) * | 1988-02-19 | 1989-08-25 | Toshiba Corp | Nonvoltaile semiconductor memory |
| US7021579B2 (en) | 2001-10-15 | 2006-04-04 | Fuji Photo Film Co., Ltd. | Recording tape cartridge |
| US7051968B2 (en) | 2001-10-15 | 2006-05-30 | Fuji Photo Film Co., Ltd. | Recording tape cartridge |
| US7204447B2 (en) | 2001-10-15 | 2007-04-17 | Fujifilm Corporation | Recording tape cartridge |
| US6845935B2 (en) | 2001-11-20 | 2005-01-25 | Fuji Photo Film Co., Ltd. | Recording tape cartridge |
| US6988686B2 (en) | 2001-11-20 | 2006-01-24 | Fuji Photo Film Co., Ltd. | Recording tape cartridge |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2921653B2 (en) | Trench memory structure and method of manufacturing the same | |
| JP4104133B2 (en) | Nonvolatile semiconductor memory device and manufacturing method thereof | |
| KR940006094B1 (en) | Nonvolatile semiconductor memory device and fabricating method thereof | |
| KR100221062B1 (en) | A flash memory and manufacturing method of the same | |
| JPH065824A (en) | Three-dimensional direct writing eeprom array and manufacture thereof | |
| JPH09120998A (en) | Flash eeprom cell, its preparation, program method and read method | |
| US5614429A (en) | Method for fabricating EEPROM with control gate in touch with select gate | |
| JP2980012B2 (en) | Nonvolatile semiconductor memory device | |
| JPH07240478A (en) | Preparation of nonvolatile semiconductor memory device | |
| JPS6161470A (en) | Nonvolatile semiconductor memory device | |
| US5793080A (en) | Nonvolatile memory device | |
| JPH02308571A (en) | Semiconductor memory device | |
| US20040171217A1 (en) | Method of manufacturing a floating gate and method of manufacturing a non-volatile semiconductor memory device comprising the same | |
| JPH01278781A (en) | Nonvolatile semiconductor memory device | |
| JPH06104451A (en) | Nonvolatile semiconductor storage device | |
| EP0166208B1 (en) | Charge storage structure for nonvolatile memory | |
| KR0135239B1 (en) | Flash eeprom cell and its fabrication | |
| JPH05226662A (en) | Semiconductor storage device | |
| JP2598523B2 (en) | Nonvolatile semiconductor memory device and method of manufacturing the same | |
| JPH03280580A (en) | Semiconductor storage device and its manufacture | |
| JPS60106175A (en) | Semiconductor memory device | |
| JPS611056A (en) | Nonvolatile semiconductor memory device | |
| JP3139165B2 (en) | Method for manufacturing nonvolatile memory cell | |
| KR100240276B1 (en) | Eeprom cell and manufacturing method therefor | |
| JP2608965B2 (en) | Semiconductor memory device and method of manufacturing the same |