JPS6161434A - Manufacture of element region for semiconductor integrated circuit - Google Patents
Manufacture of element region for semiconductor integrated circuitInfo
- Publication number
- JPS6161434A JPS6161434A JP18390284A JP18390284A JPS6161434A JP S6161434 A JPS6161434 A JP S6161434A JP 18390284 A JP18390284 A JP 18390284A JP 18390284 A JP18390284 A JP 18390284A JP S6161434 A JPS6161434 A JP S6161434A
- Authority
- JP
- Japan
- Prior art keywords
- epitaxial layer
- type
- grown
- layer
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/761—PN junctions
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
（１）発明の篇する技術分野
本発明は、半導体集積回路の素子領域の製造方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION (1) Technical field to which the invention pertains The present invention relates to a method of manufacturing an element region of a semiconductor integrated circuit.
（２）従来技術
従来、この種の半導体集積回路は、まず、基板上にエピ
タキシャル層を成長させ、次に絶縁拡散し、最後に熱処
理し、Ｐ Ｎ接合分離された素子領域を形成しているが
、この方法では、熱処理による絶縁拡散層の横方向への
拡がシは、エピタキシャル層の厚さくらいとなシ、エピ
タキシャル層の厚さが大きいほどこの絶縁拡散層の横方
向の拡が９も大きくなるという欠点があった。(2) Prior Art Conventionally, in this type of semiconductor integrated circuit, an epitaxial layer is first grown on a substrate, then insulated and diffused, and finally heat treated to form element regions separated by P-N junctions. However, in this method, the lateral expansion of the insulating diffusion layer due to heat treatment is about the same as the thickness of the epitaxial layer, and the greater the thickness of the epitaxial layer, the more the lateral expansion of the insulation diffusion layer increases. It had the disadvantage of being large.
（３）発明の詳細な説明
本発明の目的は、上記請求の範囲に示す方法によシ、上
記絶縁拡散層の横方向の拡がシを従来方法のそれの半分
はどにし、絶縁拡散層を含めた絶縁素子領域を小さくで
きるようにした半導体集積回路の素子領域の製造方法を
提供することにある。(3) Detailed Description of the Invention The object of the present invention is to provide a method according to the above claims, in which the lateral expansion of the insulating diffusion layer is reduced to half that of the conventional method, and the insulating diffusion layer is It is an object of the present invention to provide a method for manufacturing an element region of a semiconductor integrated circuit, which allows the insulating element region including the insulating element region to be reduced in size.
（４）発明の構成
本発明の特徴は、基板上に一導電型の第１のエピタキシ
ャル層を成長させ、次に逆導電型の絶縁分離用の拡散を
し、次に一導電型の第２のエピタキシャル層を成長させ
、熱処理を行うことである。(4) Structure of the Invention The present invention is characterized by growing a first epitaxial layer of one conductivity type on a substrate, then diffusing an opposite conductivity type for isolation, and then growing a second epitaxial layer of one conductivity type. The first step is to grow an epitaxial layer and perform heat treatment.
（５）発明の実施例
本発明の実施例について説明する前に、従来方法につい
て第１図を参照して説明する。第１図ＶＣ示すように、
まず、Ｐ形基板１にｎ形エピタキシャル）Ｗｉ ２を成
長させ、次にＰ形絶縁拡散し、Ｐ形波散層３及び４を形
成する。次いで熱処理し、ＰＮ接合分離された素子領域
５を形成する。第１図よシ明らかなように、絶縁拡散層
６及び７の横方向の拡が９は、かな夛大きいことがわか
る。(5) Embodiments of the Invention Before describing embodiments of the present invention, a conventional method will be explained with reference to FIG. As shown in Figure 1 VC,
First, n-type epitaxial (Wi) 2 is grown on a P-type substrate 1, and then P-type insulation is diffused to form P-type scattering layers 3 and 4. Next, a heat treatment is performed to form a device region 5 separated by a PN junction. As is clear from FIG. 1, the lateral extent 9 of the insulating diffusion layers 6 and 7 is quite large.
次に本発明の実施例について、第２図を参照して説明す
る。第２図に示すように、まず、Ｐ形基板１１に所定の
エピタキシャル層の第１半分の厚さのｎ形エピタキシャ
ル層１８ｔ−成長させ、次にＰ形絶縁拡散し、Ｐ形波散
層１３及び１４を形成する。更に、ｌ）の半分の厚さの
第２ｎ形エピタキシヤル層１９を成長させる。次いで熱
処理し、ＰＮ接合分離された素子領域１５を形成する。Next, an embodiment of the present invention will be described with reference to FIG. As shown in FIG. 2, first, an n-type epitaxial layer 18t having a thickness of the first half of a predetermined epitaxial layer is grown on a P-type substrate 11, then a P-type insulation is diffused, and a P-type scattering layer 13 is grown. and 14. Furthermore, a second n-type epitaxial layer 19 with a thickness half that of l) is grown. Next, a heat treatment is performed to form a device region 15 separated by a PN junction.
第２図から明らかなように、絶縁拡散層１６及び１７の
横方向の拡が）は、従来方法のそれと比して半分はどで
あることがわかる。As is clear from FIG. 2, the lateral expansion of the insulating diffusion layers 16 and 17 is half that of the conventional method.
したがって、本発明の実施例によれば、絶縁拡散層を従
来方法のそれよシ小さくできる。Therefore, according to embodiments of the present invention, the insulating diffusion layer can be made smaller than that of the conventional method.
（６）発明の効果
本発明は、以上説明したように絶縁拡散層を小さくでき
ることによシ、絶縁拡散層を含めた絶縁素子領域が小さ
くでき、半導体集積回路の素子集積度を大きくする効果
がある。(6) Effects of the Invention As explained above, the present invention has the effect that by making the insulating diffusion layer smaller, the insulating element area including the insulating diffusion layer can be made smaller, and the element integration degree of the semiconductor integrated circuit can be increased. be.
第１図は、従来方法を示した断面図、第２図は、本発明
の実施例を示した断面図である。
１・・・・・・Ｐ形基板、２・・・・・・エピタキシャ
ル層、３゜４・・・・・・Ｐ膨拡散層、５・・・・・・
素子領域、６，７・・・・・・絶縁拡散層、１１・・・
・・・Ｐ形基板、１３．１４・・・・・・Ｐ膨拡散層、
１５・・・・・・素子領域、１６．１７・・・・・・絶
縁拡散層、１８・・・・・・第１ｎ形エピタキシヤル層
、１９・・・・・・第２ｎ形エピタキシヤル層、２１，
２２゜２３．２４・・・・・・熱酸化膜。
（α）
（ｂ）
（Ｃン
芽 ｌ 図
（α）
（ｂ）
（Ｃン
（ｄ）
第２ 閏FIG. 1 is a sectional view showing a conventional method, and FIG. 2 is a sectional view showing an embodiment of the present invention. 1...P type substrate, 2...Epitaxial layer, 3゜4...P swelling diffusion layer, 5...
Element region, 6, 7...Insulating diffusion layer, 11...
... P type substrate, 13.14 ... P swelling diffusion layer,
15...Element region, 16.17...Insulating diffusion layer, 18...First n-type epitaxial layer, 19...Second n-type epitaxial layer ,21,
22゜23.24...Thermal oxide film. (α) (b) (C-bud l Figure (α) (b) (C-n (d) Second leap
Claims (1)
導電型の第１のエピタキシャル層を成長させ、次に逆導
電型の絶縁分離用の拡散をし、更に残りの約半分の厚さ
の一導電型の第２のエピタキシャル層を成長させ、次に
熱処理し、ＰＮ接合分離された素子領域を形成すること
を特徴とする半導体集積回路の素子領域の製造方法。A first epitaxial layer of one conductivity type is grown on the substrate, approximately half the thickness of the predetermined epitaxial layer, and then an insulating layer of the opposite conductivity type is grown, followed by a second epitaxial layer approximately half the thickness of the remaining epitaxial layer. 1. A method of manufacturing a device region of a semiconductor integrated circuit, comprising growing a second epitaxial layer of one conductivity type and then heat-treating the layer to form a device region separated by a PN junction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18390284A JPS6161434A (en) | 1984-09-03 | 1984-09-03 | Manufacture of element region for semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18390284A JPS6161434A (en) | 1984-09-03 | 1984-09-03 | Manufacture of element region for semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6161434A true JPS6161434A (en) | 1986-03-29 |
Family
ID=16143808
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18390284A Pending JPS6161434A (en) | 1984-09-03 | 1984-09-03 | Manufacture of element region for semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6161434A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8205313B2 (en) | 2007-09-10 | 2012-06-26 | Honda Motor Co., Ltd. | Structure for attaching vibration insulating member |
-
1984
- 1984-09-03 JP JP18390284A patent/JPS6161434A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8205313B2 (en) | 2007-09-10 | 2012-06-26 | Honda Motor Co., Ltd. | Structure for attaching vibration insulating member |
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