JPS6159565A - Interrupt input device of multicomputer system - Google Patents
Interrupt input device of multicomputer systemInfo
- Publication number
- JPS6159565A JPS6159565A JP18058684A JP18058684A JPS6159565A JP S6159565 A JPS6159565 A JP S6159565A JP 18058684 A JP18058684 A JP 18058684A JP 18058684 A JP18058684 A JP 18058684A JP S6159565 A JPS6159565 A JP S6159565A
- Authority
- JP
- Japan
- Prior art keywords
- interrupt
- address
- input
- signal
- register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Multi Processors (AREA)
- Bus Control (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は、マルチコンピュータシステムに係り、特に、
割込処理に好適な割込入力装置に関する６〔発明の背景
〕
従来の装置は特開昭５８−４３０５４号、特開昭５８−
６０３３４号公報に記載のように、複数台の中央処理装
置（以下ＣＰＵ）とプロセス入出力装置ｉ！（以下ＰＩ
１０）を共用転送バスを用いて結合したマルチコンピュ
ータシステムではＰＩ／○データは共用のデータバスを
通して各ＣＰＵに、サイクリックに転送を行なっていた
。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a multi-computer system, and in particular,
6 Concerning an interrupt input device suitable for interrupt processing [Background of the invention] Conventional devices are disclosed in Japanese Patent Laid-Open No. 58-43054 and Japanese Patent Laid-open No. 58-58-
As described in Publication No. 60334, multiple central processing units (hereinafter referred to as CPUs) and process input/output devices i! (hereinafter referred to as PI
In a multi-computer system in which 10) are connected using a shared transfer bus, PI/○ data is cyclically transferred to each CPU through the shared data bus.
しかし、割込入力信号を一台あるいは複数のＣＰＵに共
通に与え、割込処理を行なう点については配慮されてい
なかった。まず、ＣＰＵ毎に割込専用カードを設けると
すると、その割込情報は該当するＣＰＵへの入力のみと
なり、他のＣＰＵへは転送されない。また、全ＣＰＵに
共通した割込専用カードを設けると、前述のＣＰＵとＰ
Ｉｌｏを結ぶ共用転送バス以外に割込専用カードと全Ｃ
ＰＵ間に接続が必要となる。しかも、システムの変更が
容易に行なえないという問題がある。また、共用転送バ
スを介して割込入力信号をＣＰＵに読み込ませようとす
ると、ＣＰＵは、常に、サイクリックに割込専用カード
のアドレスをアクセスしていなければならない、そこで
、一つの割込入力信号を複数のＣＰＵで共用でき、かつ
、簡単なハードで構成される方法が必要となってきた。However, no consideration has been given to providing an interrupt input signal to one or more CPUs in common to perform interrupt processing. First, if an interrupt-only card is provided for each CPU, the interrupt information will only be input to the corresponding CPU, and will not be transferred to other CPUs. In addition, if an interrupt-only card is provided that is common to all CPUs, the above-mentioned CPU and
In addition to the shared transfer bus connecting Ilo, an interrupt-only card and all C
Connections are required between PUs. Moreover, there is a problem in that the system cannot be easily changed. Furthermore, when attempting to read an interrupt input signal to the CPU via the shared transfer bus, the CPU must always cyclically access the address of the interrupt-only card. There is now a need for a method that allows signals to be shared by multiple CPUs and that is constructed using simple hardware.
なお、この方法として関連するものには、例えば、特公
昭５８−４６７２５号公報に開示されている。A related method is disclosed in Japanese Patent Publication No. 58-46725, for example.
本発明の目的は、割込専用カードを用いることなく、Ｃ
ＰＵが読み取り後、リセットされる割込信号を、非同期
で動作する複数のＣＰＵ間で共用するための割込入力装
置を提供するにある。The object of the present invention is to
An object of the present invention is to provide an interrupt input device for sharing an interrupt signal, which is reset after being read by a PU, among a plurality of CPUs operating asynchronously.
本発明は、複数のＣＰＵごとに割込入力検出回路及び割
込レジスタを設け、任意の割込アドレスの割込情報を、
全てのＣＰＵ、あるいは、特定のＣＰＵの割込レジスタ
に入力し、共通の割込信号により各ＣＰＵが割込処理を
行なうようにしたものである。In the present invention, an interrupt input detection circuit and an interrupt register are provided for each of a plurality of CPUs, and interrupt information of an arbitrary interrupt address is
This signal is input to the interrupt register of all CPUs or a specific CPU, and each CPU performs interrupt processing using a common interrupt signal.
第１図は、本発明の実施例の全体構成図である。 FIG. 1 is an overall configuration diagram of an embodiment of the present invention.
図において、ＣＰＵ−Ａｌ、ＣＰＵ−Ｂ２．・・・ＣＰ
Ｕ−Ｎ３は非同期に動作する中央処理装置、ＰＩ１０４
は全ＣＰＵに共通なプロセス入出力装置、ＩＮＴ−Ａ８
．ＩＮＴ−Ｂ９．・・・ＩＮＴ−Ｎ１０は割込入力装置
、メモリＡ・５．メモリＢ・６、・・・メモリＮ・７は
各ＣＰＵが個々に持つメモリである。In the figure, CPU-Al, CPU-B2. ...CP
U-N3 is a central processing unit that operates asynchronously, PI104
is the process input/output device common to all CPUs, INT-A8
．． INT-B9. ...INT-N10 is an interrupt input device, memory A/5. Memory B.6, . . . memory N.7 are memories that each CPU has individually.
各ＣＰＵＩ〜３は、ＣＰＵ単位のバスにより割込入力装
置ＩＮＴ８〜１０．及びメモリ５〜７をアクセスする。Each CPU I~3 is connected to an interrupt input device INT8~10. by a bus for each CPU. and accesses memories 5-7.
メモリ５〜７相互間は、ＣＰＵ系のバスとは別の共用転
送バス１１で結合され、バス制御装置１２によって、共
通のＰＩｌｏとサイクリックにデータの転送を行なう。The memories 5 to 7 are interconnected by a shared transfer bus 11 that is separate from the CPU system bus, and a bus control device 12 cyclically transfers data to a common PIlo.
また、割込入力装置８〜１０も、共用転送バス１１によ
り、ＰＩ１０４からの割込入力を受は付けている。Further, the interrupt input devices 8 to 10 also accept interrupt inputs from the PI 104 via the shared transfer bus 11.
第２図に、本発明の割込入力装置を示す。FIG. 2 shows an interrupt input device of the present invention.
割込入力装置８は、割込情報としたい入力データに対応
した入力アドレスを任意に設定できる割込アドレス設定
回路１３、割込アドレスコンベア回路１４、ＰＩ１０４
からの割込入力を検出する割込入力検出回路１５、割込
情報を記憶する割込レジスタ１６１割込マスクレジスタ
１７、およびＣＰＵとのインターフェイス回路から成る
。The interrupt input device 8 includes an interrupt address setting circuit 13, an interrupt address conveyor circuit 14, and a PI 104, which can arbitrarily set an input address corresponding to input data to be used as interrupt information.
It consists of an interrupt input detection circuit 15 that detects an interrupt input from the CPU, an interrupt register 161 that stores interrupt information, an interrupt mask register 17, and an interface circuit with the CPU.
常時は、ＰＩ１０４からの入力データは共通転送バス１
１を介してメモリ５に入力されるが、割込アドレス設定
回路１３により設定された特定アドレスに対応した入力
データは、メモリ５に入力されると共に、割込入力検出
回路１５に入力され、割込アドレスのデータに変化が生
じた場合（割込起動状Ｓ）は割込レジスタ１６の任意ビ
ットにフラグを立てる。つまり、通常のＰＩカードの情
報を割込信号として使うこととなり、専用の割込カード
は不要となる。そして、割込レジスタ１６のビットに対
応した割込マスクレジスタ１７のビットが割込許可され
ていれば１割込信号をＣＰＵＩに出し、ＣＰＵＩの割込
処理を起動する０割込マスクレジスタ１７のビットが割
込禁止状態であれば割込信号は出力されず、割込情報は
無視されるものとする。Normally, input data from PI104 is transferred to common transfer bus 1.
1, the input data corresponding to the specific address set by the interrupt address setting circuit 13 is input to the memory 5, and is also input to the interrupt input detection circuit 15, and is input to the interrupt input detection circuit 15. If a change occurs in the data of the interrupt address (interrupt activation status S), a flag is set in an arbitrary bit of the interrupt register 16. In other words, information on a normal PI card is used as an interrupt signal, and a dedicated interrupt card is not required. Then, if the bit of the interrupt mask register 17 corresponding to the bit of the interrupt register 16 is enabled, a 1 interrupt signal is sent to the CPUI, and the 0 interrupt mask register 17 starts the CPUI interrupt processing. If the bit is in the interrupt disabled state, no interrupt signal will be output and the interrupt information will be ignored.
動作を第３図により説明する。The operation will be explained with reference to FIG.
共用転送バス系のアドレスバスでは、サイクリックにア
ドレスが更新され、それに対応したＰＩ１０データがデ
ータバスにオンバスされる。前述の割込入力装置内の割
込アドレス設定回路によって設定した割込アドレスと、
アドレスバスからのアドレスが一致した時、割込アドレ
ス一致信号が出力され、その時のデータバス上の入力デ
ータを割込入力検出回路に入力する６そして、データの
変化を検出してＰＩＩ信号（割込入力信号）を割込レジ
スタに書込む６割込マスクレジスタが割込許可状態であ
れば、割込信号をＣＰＵに出す。In the address bus of the shared transfer bus system, addresses are cyclically updated, and corresponding PI10 data is placed on the data bus. The interrupt address set by the interrupt address setting circuit in the interrupt input device mentioned above,
When the addresses from the address bus match, an interrupt address match signal is output, and the input data on the data bus at that time is input to the interrupt input detection circuit6.Then, a change in data is detected and the PII signal (interrupt 6. If the interrupt mask register is in an interrupt enabled state, an interrupt signal is sent to the CPU.
ＣＰＵは、その割込信号により、ＣＰＵ系のアドレスバ
スに割込レジスタのアドレス、及び、読込信号ＲＥＱを
出力し、割込レジスタの割込情報、及び、応答信号ＡＣ
Ｋにより割込処理を行なう。In response to the interrupt signal, the CPU outputs the address of the interrupt register and the read signal REQ to the CPU system address bus, and outputs the interrupt information of the interrupt register and the response signal AC.
Interrupt processing is performed by K.
本発明によれば、複数のＣＰＵと共通のＰＩｌｏから構
成されるマルチコンピュータシステムにおいて、割込情
報を簡単なハード構成で複数のＣＰ’Ｕで共用すること
ができる６
また、専用の割込カードを用いることなく任意の入力デ
ータを割込信号として利用できる。According to the present invention, in a multi-computer system composed of a plurality of CPUs and a common PIlo, interrupt information can be shared by a plurality of CPU'Us with a simple hardware configuration6. Any input data can be used as an interrupt signal without using.
第１図は、本発明の一実施例のブロック図、第２図は、
本発明のハード構成図、第３図は実施例の動作説明図で
ある６
８・・・割込入力装置、１３・・・割込アドレス設定回
路、１４・・・割込アドレスコンベア回路、１５・・・
割込入力検出回路、１６・・・割込レジスタ、１７・・
・割込マスクレジスタ。FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
A hardware configuration diagram of the present invention, FIG. 3 is an explanatory diagram of the operation of the embodiment 6 8...Interrupt input device, 13...Interrupt address setting circuit, 14...Interrupt address conveyor circuit, 15 ...
Interrupt input detection circuit, 16... Interrupt register, 17...
- Interrupt mask register.
Claims (1)
出力装置とを共用転送バスを用いて結合したマルチコン
ピュータシステムにおいて、 割込アドレスを任意に設定できる割込アドレス設定回路
及び割込アドレスコンペア回路、割込を検出する割込入
力検出回路、割込情報を格納する割込レジスタ、割込の
許可あるいは禁止を設定する割込マスクレジスタから成
る割込入力装置を、複数の前記中央処理装置毎に設けた
ことを特徴とするマルチコンピュータシステムの割込入
力装置。[Claims] 1. An interrupt address setting circuit that can arbitrarily set an interrupt address in a multi-computer system in which a plurality of asynchronously operating central processing units and process input/output devices are coupled using a shared transfer bus. and an interrupt input device consisting of an interrupt address compare circuit, an interrupt input detection circuit to detect interrupts, an interrupt register to store interrupt information, and an interrupt mask register to enable or disable interrupts. An interrupt input device for a multi-computer system, characterized in that the interrupt input device is provided for each of the central processing units.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18058684A JPS6159565A (en) | 1984-08-31 | 1984-08-31 | Interrupt input device of multicomputer system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18058684A JPS6159565A (en) | 1984-08-31 | 1984-08-31 | Interrupt input device of multicomputer system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6159565A true JPS6159565A (en) | 1986-03-27 |
| JPH0114616B2 JPH0114616B2 (en) | 1989-03-13 |
Family
ID=16085851
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18058684A Granted JPS6159565A (en) | 1984-08-31 | 1984-08-31 | Interrupt input device of multicomputer system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6159565A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62243058A (en) * | 1986-04-15 | 1987-10-23 | Fanuc Ltd | Control method of interruption for multi-processor system |
| JPH04271434A (en) * | 1991-02-27 | 1992-09-28 | Fuji Electric Co Ltd | Interrupting input module for programmable controller |
| JP2007206955A (en) * | 2006-02-01 | 2007-08-16 | Sony Corp | Apparatus and method for information processing, program, and recording medium |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50115732A (en) * | 1974-02-22 | 1975-09-10 | ||
| JPS5534752A (en) * | 1978-09-01 | 1980-03-11 | Nec Corp | Common access unit |
-
1984
- 1984-08-31 JP JP18058684A patent/JPS6159565A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50115732A (en) * | 1974-02-22 | 1975-09-10 | ||
| JPS5534752A (en) * | 1978-09-01 | 1980-03-11 | Nec Corp | Common access unit |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62243058A (en) * | 1986-04-15 | 1987-10-23 | Fanuc Ltd | Control method of interruption for multi-processor system |
| US4930070A (en) * | 1986-04-15 | 1990-05-29 | Fanuc Ltd. | Interrupt control method for multiprocessor system |
| JPH04271434A (en) * | 1991-02-27 | 1992-09-28 | Fuji Electric Co Ltd | Interrupting input module for programmable controller |
| JP2007206955A (en) * | 2006-02-01 | 2007-08-16 | Sony Corp | Apparatus and method for information processing, program, and recording medium |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0114616B2 (en) | 1989-03-13 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |