JPS6159033B2 - - Google Patents

Info

Publication number
JPS6159033B2
JPS6159033B2 JP56181030A JP18103081A JPS6159033B2 JP S6159033 B2 JPS6159033 B2 JP S6159033B2 JP 56181030 A JP56181030 A JP 56181030A JP 18103081 A JP18103081 A JP 18103081A JP S6159033 B2 JPS6159033 B2 JP S6159033B2
Authority
JP
Japan
Prior art keywords
circuit
output
image signal
intermediate region
line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56181030A
Other languages
Japanese (ja)
Other versions
JPS5883471A (en
Inventor
Hideo Sato
Shigeaki Yamaguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP56181030A priority Critical patent/JPS5883471A/en
Publication of JPS5883471A publication Critical patent/JPS5883471A/en
Publication of JPS6159033B2 publication Critical patent/JPS6159033B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N1/00Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
    • H04N1/40Picture signal circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Image Input (AREA)
  • Facsimile Image Signal Circuits (AREA)

Description

【発明の詳細な説明】 本発明は画信号を読取る方式で画信号に中間領
域を設定した画信号読取り方式に関するものであ
る。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image signal reading method in which an intermediate region is set in the image signal.

従来の画信号読取り方式を第1図に示す。第1
図において0は反射光、1は光電変換器、2は比
較回路、3は直流電圧源、4は出力端子の如く構
成されており、パターン情報からの反射光0が光
電変換器1の中の光電変換素子により電気エネル
ギーに変換されて画信号として比較回路2の一方
の入力端子に入力される。他方の入力端子は直流
電圧源3からの直流電圧が入力され比較回路2の
出力には2値化された信号が出力される。第2図
は上述した画信号読取り方式における光電変換器
1の出力の画信号と直流電圧源3の電圧を変えた
ときの比較回路2の出力との関係を説明するため
の図でn1,n2,n3……は光電変換器1でサ
ンプルした光量に対する相対出力で、A,Bは直
流電圧源3の電圧を示す。直流電圧源3をAに選
択すると比較回路の出力はn4〜n7が「クロ」
となる。又Bに選択するとn6,n7が「クロ」
となる。このときn4,n5は直流電圧源3の電
圧をAにした場合は「クロ」でn6,n7と同じ
出力と看され、又Bにした場合は「シロ」でn1
〜n3,n8と同じ出力と看されてしまい、どの
ように直流電圧源3の電圧を選択しても、n4,
n5のレベルを他のサンプル点と区別出来ず分解
能が上がらない欠点があつた(つまりn4とn5
のレベルは、常に、n1〜n3のレベル又はn6
〜n7のレベルと同じになる)。
A conventional image signal reading system is shown in FIG. 1st
In the figure, 0 is a reflected light, 1 is a photoelectric converter, 2 is a comparison circuit, 3 is a DC voltage source, and 4 is an output terminal. The photoelectric conversion element converts it into electrical energy and inputs it to one input terminal of the comparator circuit 2 as an image signal. The other input terminal receives the DC voltage from the DC voltage source 3, and the comparator circuit 2 outputs a binary signal. FIG. 2 is a diagram for explaining the relationship between the image signal output from the photoelectric converter 1 and the output of the comparator circuit 2 when the voltage of the DC voltage source 3 is changed in the image signal reading method described above. , n3... are relative outputs with respect to the amount of light sampled by the photoelectric converter 1, and A and B indicate the voltage of the DC voltage source 3. When DC voltage source 3 is selected as A, the output of the comparator circuit is "black" for n4 to n7.
becomes. Also, if you select B, n6 and n7 will be "black"
becomes. At this time, when the voltage of the DC voltage source 3 is set to A, n4 and n5 are considered to be "black" and have the same output as n6 and n7, and when set to B, they are "white" and n1
~n3, n8 are considered to have the same output, and no matter how you select the voltage of DC voltage source 3, n4,
There was a drawback that the level of n5 could not be distinguished from other sample points and the resolution could not be improved (that is, the level of n4 and n5
The level of is always the level of n1 to n3 or n6
~ the same level as n7).

本発明は従来の技術の欠点を改善することを目
的とし、比較回路を2回路使用して中間領域を設
定し、画信号を中間領域内と中間領域外に判別し
中間領域内のときは前ラインの信号の極性を反転
して出力とし中間領域外のときは片方の比較回路
の出力を使用して画信号の中間領域の分解能を上
げるものである。
The present invention aims to improve the drawbacks of the conventional technology, and uses two comparison circuits to set an intermediate area, and distinguishes the image signal between inside and outside the intermediate area, and when it is within the intermediate area, the image signal is The polarity of the line signal is inverted and output, and when it is outside the intermediate area, the output of one of the comparison circuits is used to increase the resolution of the intermediate area of the image signal.

以下図面により実施例を説明する。 Examples will be described below with reference to the drawings.

第3図は本発明の第1の実施例であつて0は反
射光、1は光電変換器、5は比較回路A、6は比
較回路B、7は直流電圧源、8は中間領域判別回
路、9は切換スイツチ、10は記憶回路、11は
出力端子である。
FIG. 3 shows the first embodiment of the present invention, in which 0 is reflected light, 1 is a photoelectric converter, 5 is a comparison circuit A, 6 is a comparison circuit B, 7 is a DC voltage source, and 8 is an intermediate region discrimination circuit. , 9 is a changeover switch, 10 is a memory circuit, and 11 is an output terminal.

パターン情報からの反射光0が光電変換器1の
中の光電変換素子により電気エネルギーに変換さ
れて画信号として5の比較回路A及び6の比較回
路Bの各入力端子に入力される。5の比較回路A
の入力端子には直流電圧源7からの直流電圧A
が、又6の比較回路Bの入力端子には直流電圧B
が入力される。直流電圧源7の直流電圧のAとB
はA>Bの関係とする。画信号は各比較回路で直
流電圧A,Bと比較されて各出力には2値化され
た信号が出力して中間領域判別回路8に入る。こ
の判別回路では画信号が直流電圧源7の直流電圧
AとBの間にある場合、すなわち画信号が中間領
域内の場合と、画信号が直流電圧AとBの間にな
い場合、すなわち中間領域外の場合とを判別して
いる。例えばEXOR回路により構成する。つぎの
切換スイツチ9では中間領域判別回路8の判別に
したがつて信号を切換えてこの出力が出力端子1
1と記憶回路10に接続される。記憶回路10で
は常に現在読取つているラインの中の1サンプル
と同じ位置の1ライン遅延した1サンプルの信号
を極性を反転して出力している。したがつて中間
領域外の場合は5の比較回路Aの2値化された信
号が出力端子11へ、又中間領域内の場合は記憶
回路10で1ライン遅延した前ラインの信号が極
性が反転して出力端子11へ出力される。第4図
A,Bは上述した画信号読取り方式における光電
変換器1の出力と出力端子11の出力との関係を
説明するための図で、第4図Aは光電変換器1で
n1,n2,n3……とサンプルした光量の相対
出力を示し、A及びBは直流電圧源7から各比較
回路に入力している直流電圧を示す。(A>B)。
第4図Bは出力端子11の出力を示し、m1,m
2,m3……は各ライン、n1,n2,n3……
は各サンプルを示す。第4図Bの動作条件はライ
ンm1の前ラインはすべて「クロ」でラインm1
〜mまでのサンプルn1〜n8の相対出力はすべ
て同じとする。ラインm1ではn1〜n3は中間
領域外なので「シロ」、n4,n5は中間領域内
なので記憶回路10で記憶している前ラインの極
性を反転した信号が出力され「シロ」となり、n
6,n7,n8は中間領域外なのでn6,n7が
「クロ」、n8が「シロ」となる。ラインm2では
n1〜n3は中間領域外なので「シロ」、n4,
n5は中間領域内なので前ラインm1の極性を反
転した「クロ」となり、n6,n7,n8は中間
領域外なのでn6,n7が「クロ」、n8が「シ
ロ」となる。同じようにラインm3ではn1〜n
3,n6,n7,n8は中間領域外なのでライン
m2と変らないが、n4,n5は中間領域内なの
で前ラインm2の極性を反転した「シロ」とな
る。
Reflected light 0 from the pattern information is converted into electrical energy by the photoelectric conversion element in the photoelectric converter 1, and is input as an image signal to each input terminal of the comparison circuit A of 5 and the comparison circuit B of 6. Comparison circuit A of 5
DC voltage A from DC voltage source 7 is input to the input terminal of
However, the input terminal of comparator circuit B in No. 6 has DC voltage B.
is input. A and B of the DC voltage of the DC voltage source 7
is assumed to have the relationship A>B. The image signal is compared with DC voltages A and B in each comparison circuit, and a binarized signal is outputted to each output and enters the intermediate region discrimination circuit 8. In this discrimination circuit, when the image signal is between the DC voltages A and B of the DC voltage source 7, that is, the image signal is within the intermediate region, and when the image signal is not between the DC voltages A and B, that is, the intermediate region. It distinguishes between cases outside the area. For example, it is configured by an EXOR circuit. The next changeover switch 9 switches the signal according to the judgment of the intermediate region judgment circuit 8, and this output is sent to the output terminal 1.
1 and the memory circuit 10. The memory circuit 10 always outputs a signal of one sample delayed by one line at the same position as one sample in the line currently being read, with the polarity inverted. Therefore, if it is outside the intermediate region, the binarized signal of the comparator circuit A of 5 is sent to the output terminal 11, and if it is inside the intermediate region, the polarity of the previous line signal delayed by one line in the memory circuit 10 is reversed. and output to the output terminal 11. 4A and 4B are diagrams for explaining the relationship between the output of the photoelectric converter 1 and the output of the output terminal 11 in the above-mentioned image signal reading method. , n3 . . . indicate the relative output of the sampled light amount, and A and B indicate the DC voltages input from the DC voltage source 7 to each comparison circuit. (A>B).
Figure 4B shows the output of the output terminal 11, m1, m
2, m3... are each line, n1, n2, n3...
indicates each sample. The operating conditions in Figure 4B are that all lines before line m1 are "black" and line m1
It is assumed that the relative outputs of samples n1 to n8 from ~m are all the same. In line m1, n1 to n3 are outside the intermediate region, so they are "white", and since n4 and n5 are inside the intermediate region, a signal in which the polarity of the previous line stored in the storage circuit 10 is inverted is output and becomes "white", and n
6, n7, and n8 are outside the intermediate region, so n6, n7 are "black" and n8 is "white." In line m2, n1 to n3 are outside the intermediate area, so they are "white", n4,
Since n5 is within the intermediate region, it becomes "black" by reversing the polarity of the previous line m1, and since n6, n7, and n8 are outside the intermediate region, n6, n7 become "black" and n8 becomes "white." Similarly, on line m3, n1 to n
Lines 3, n6, n7, and n8 are outside the intermediate area and are therefore unchanged from line m2, but lines n4 and n5 are within the intermediate area, so they are "white" with the polarity of the previous line m2 reversed.

以上説明したように、第1の実施例ではライン
方向と直角な方向に対して中間領域判別回路8の
判別が中間領域外の場合は出力は「シロ」又は
「クロ」となり、中間領域内の場合には前ライン
の信号の極性を反転し出力しているため、中間領
域のセルのレベルが1ライン毎に反転し、疑似的
な3値信号となり、従来の2値信号より分解能を
上げることが出来る利点がある。
As explained above, in the first embodiment, when the intermediate area discrimination circuit 8 determines that the area is outside the intermediate area in the direction perpendicular to the line direction, the output becomes "white" or "black"; In some cases, the polarity of the signal from the previous line is inverted and output, so the level of the cells in the intermediate area is inverted for each line, resulting in a pseudo ternary signal, which improves the resolution compared to a conventional binary signal. It has the advantage of being able to

本発明では画信号に中間領域を設定してライン
方向と直角な方向に対して疑似的な3値信号にし
ているので従来の2値信号より分解能を上げるこ
とが出来る。
In the present invention, an intermediate region is set in the image signal to create a pseudo three-value signal in a direction perpendicular to the line direction, so that the resolution can be higher than that of a conventional binary signal.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の画信号読取り方式の構成図、第
2図A及びBは従来の画信号読取り方式における
光電変換器1の出力と比較回路2の出力の説明
図、第3図は本発明の一実施例の構成図、第4図
A及びBは本発明の光電変換器1の出力と出力端
子11の出力の説明図である。 0……パターン情報の反射光、1……光電変換
器、2……比較回路、3……直流電圧源、4……
出力端子、5……比較回路A、6……比較回路
B、7……直流電圧源、8……中間領域判別回
路、9……切換スイツチ、10……記憶回路、1
1……出力端子。
FIG. 1 is a configuration diagram of a conventional image signal reading system, FIGS. 2A and B are explanatory diagrams of the output of the photoelectric converter 1 and the output of the comparator circuit 2 in the conventional image signal reading system, and FIG. 3 is a diagram of the present invention. FIGS. 4A and 4B are diagrams illustrating the output of the photoelectric converter 1 and the output of the output terminal 11 of the present invention. 0... Reflected light of pattern information, 1... Photoelectric converter, 2... Comparison circuit, 3... DC voltage source, 4...
Output terminal, 5... Comparison circuit A, 6... Comparison circuit B, 7... DC voltage source, 8... Intermediate region discrimination circuit, 9... Selector switch, 10... Memory circuit, 1
1...Output terminal.

Claims (1)

【特許請求の範囲】[Claims] 1 光電変換器からの画信号を2つの比較回路で
直流電圧A及びB(A>B)と比較し、各々の比
較出力の一致又は不一致を中間領域判別回路で判
別し、出力端子に接続される1ラインの遅延回路
及び極性反転回路をもうけ、中間領域判別回路が
一致と判別したときは、直流電圧Aと比較した比
較回路の出力を出力端子に接続し、前記判別回路
が不一致と判別したときは遅延回路及び極性反転
回路の出力を出力端子に接続することを特徴とす
る画信号読取方式。
1 The image signal from the photoelectric converter is compared with DC voltages A and B (A>B) using two comparison circuits, and an intermediate region discrimination circuit determines whether the comparison outputs match or do not match. A one-line delay circuit and a polarity inverting circuit are provided, and when the intermediate region discriminating circuit determines that there is a match, the output of the comparison circuit that is compared with the DC voltage A is connected to the output terminal, and when the discriminating circuit determines that there is a mismatch. An image signal reading method characterized in that the outputs of a delay circuit and a polarity inversion circuit are connected to an output terminal.
JP56181030A 1981-11-13 1981-11-13 Picture signal reading system Granted JPS5883471A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56181030A JPS5883471A (en) 1981-11-13 1981-11-13 Picture signal reading system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56181030A JPS5883471A (en) 1981-11-13 1981-11-13 Picture signal reading system

Publications (2)

Publication Number Publication Date
JPS5883471A JPS5883471A (en) 1983-05-19
JPS6159033B2 true JPS6159033B2 (en) 1986-12-15

Family

ID=16093535

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56181030A Granted JPS5883471A (en) 1981-11-13 1981-11-13 Picture signal reading system

Country Status (1)

Country Link
JP (1) JPS5883471A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0634255B2 (en) * 1984-02-06 1994-05-02 住友電気工業株式会社 Optical reader
JPH0636202B2 (en) * 1984-08-09 1994-05-11 住友電気工業株式会社 Optical reader

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54127215A (en) * 1978-03-27 1979-10-03 Tamura Electric Works Ltd Picture signal processing system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54127215A (en) * 1978-03-27 1979-10-03 Tamura Electric Works Ltd Picture signal processing system

Also Published As

Publication number Publication date
JPS5883471A (en) 1983-05-19

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