JPS6156532A - Am stereo demodulation circuit - Google Patents
Am stereo demodulation circuitInfo
- Publication number
- JPS6156532A JPS6156532A JP17870184A JP17870184A JPS6156532A JP S6156532 A JPS6156532 A JP S6156532A JP 17870184 A JP17870184 A JP 17870184A JP 17870184 A JP17870184 A JP 17870184A JP S6156532 A JPS6156532 A JP S6156532A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- error
- offset voltage
- voltage
- amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04H—BROADCAST COMMUNICATION
- H04H20/00—Arrangements for broadcast or for distribution combined with broadcast
- H04H20/86—Arrangements characterised by the broadcast information itself
- H04H20/88—Stereophonic broadcast systems
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Stereo-Broadcasting Methods (AREA)
Abstract
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明はＡＭステレオ復調回路に関するものである。[Detailed description of the invention] (Industrial application field) The present invention relates to an AM stereo demodulation circuit.
（従来の技術） 従来のこの種の装置は第３図のよ５に構成されていた。(Conventional technology) A conventional device of this type was constructed as shown in FIG.
同図において、ｌは信号入力端子、２は同相検波回路（
以下、Ｉ−ｄａｔとする）、３は直交検波回路（以下、
Ｑ−ｄａｔとする）°、４はマトリクス回路、５は右チ
ヤンネル出力端子、６は左チヤンネル出力端子、７は誤
差増幅回路、７は電圧制御発振回路、９は１／２分周回
路、１０は１／２分周回路、１１は１／２分周回路であ
る。In the figure, l is a signal input terminal, and 2 is a common-mode detection circuit (
3 is a quadrature detection circuit (hereinafter referred to as I-dat), and 3 is a quadrature detection circuit (hereinafter referred to as I-dat).
4 is a matrix circuit, 5 is a right channel output terminal, 6 is a left channel output terminal, 7 is an error amplifier circuit, 7 is a voltage controlled oscillator circuit, 9 is a 1/2 frequency divider circuit, 10 is a 1/2 frequency divider circuit, and 11 is a 1/2 frequency divider circuit.
信号入力端子１４にＡＭステレオ信号により変調された
信号が入力されると、Ｉ −ｄｅｔ ２およびＱ−ｄｅ
ｔ ３は位相比較器として働き、それぞれ入力の同相成
分および直交成分を復調する。これらの復調出力はマト
リクス回路４に入力され、右および左チヤンネル出力端
子５および６にそれぞれ右チャンネルおよび左チャンネ
ルの復調信号が出力される。Ｑ−ｄａｔ３．誤差増幅回
路７、電圧制御発振回路８および１７２分周回路９〜１
１はＰＬＬを構成し、信号入力端子１からの入力と１／
２分周回路ＩＯおよび１１からの出力との位相差がそれ
ぞれ９０°および０°となるように動作する。この関係
が常に成り立っている場合には、ステレメ分離度は理論
上無限大となる。When a signal modulated by an AM stereo signal is input to the signal input terminal 14, I-det 2 and Q-de
t3 acts as a phase comparator and demodulates the in-phase and quadrature components of the input, respectively. These demodulated outputs are input to matrix circuit 4, and demodulated signals of the right and left channels are output to right and left channel output terminals 5 and 6, respectively. Q-dat3. Error amplifier circuit 7, voltage controlled oscillation circuit 8 and 172 frequency divider circuits 9 to 1
1 constitutes a PLL, and the input from signal input terminal 1 and 1/
It operates so that the phase difference with the outputs from the divide-by-2 circuits IO and 11 is 90° and 0°, respectively. If this relationship always holds, the degree of stereomete separation would theoretically be infinite.
しかしながら、実際の回路では１ン２分周回路１０およ
び１１の回路構成の違いなどによ）位相誤差が発生し、
分離度が低下する。これを改善するため）ＣＱ−ｄａｔ
３の出力でオフセット＊ｉを行なった！ｔ１ ＶＣＯｓ
のフリ−２ン周波数をずらしたシして位相誤差を打消す
という方法をとっていたが、これらの方法では、無人力
時のキャプチャレンジの中心がずれたシ、ＰＬＬの動作
が固定されなくなるという欠点があった〇
（発明が解決しようとする問題点）
本発明の目的は位相誤差による分離度の低下を防止し、
かつ無人力時のＰＬＬのキャプチャレンジの中心ズレを
なくしたＡＭステレオ復調回路を提供することに、ある
。However, in an actual circuit, a phase error occurs (due to the difference in the circuit configuration of the 1-2 frequency divider circuits 10 and 11, etc.).
The degree of separation decreases. To improve this) CQ-dat
Offset *i was performed on the output of 3! t1 VCOs
The method used was to offset the phase error by shifting the free-second frequency of the PLL, but with these methods, the center of the capture range during unmanned operation shifts, and the PLL operation becomes unfixed. (Problem to be solved by the invention) The purpose of the present invention is to prevent the degree of separation from decreasing due to phase errors,
Another object of the present invention is to provide an AM stereo demodulation circuit that eliminates center deviation of the PLL capture range when unmanned.
（問題点を解決するための手段）
本発明によれば、従来のＡＭステレオ復調回路に加えて
、誤差増幅回路のオフセット電圧調整回路、入力レベル
検出回路およびこの入力レベル検出回路により制御され
るスイッチ回路を具備したＡＭステレオ復調回路を得る
。(Means for Solving the Problems) According to the present invention, in addition to a conventional AM stereo demodulation circuit, an offset voltage adjustment circuit of an error amplifier circuit, an input level detection circuit, and a switch controlled by the input level detection circuit are provided. An AM stereo demodulation circuit equipped with a circuit is obtained.
（実施例） 次に１図面を参照して、本発明をよシ詳細に説明する。(Example) The invention will now be explained in more detail with reference to one drawing.
第１図は本発明の一実施例であって、１は信号入力端子
、２は同相検波回路、３は直交検波回路。FIG. 1 shows an embodiment of the present invention, in which 1 is a signal input terminal, 2 is an in-phase detection circuit, and 3 is a quadrature detection circuit.
４はマトリクス回路、５は右チャンネル出力端子、６は
左チヤンネル出力端子、７′は誤差増幅回路。4 is a matrix circuit, 5 is a right channel output terminal, 6 is a left channel output terminal, and 7' is an error amplifier circuit.
８は電圧制御発振回路、９は１ン２分周回路、１０は１
ン２分周回路、１１は１ン２分周回路、１２は誤差増幅
器のオフセット電圧調整回路、１３は比較器、１４はス
イッチ回路でおる。第２図は誤差増幅回路７′オフセク
ト電圧ｖ４！Ｉ回路１２、コンパレータ１３およびスイ
ッチ回路１４を含む部分の具体例でありて、１５〜１９
は抵抗、２０はボテンシ町メータ、２１は基準電圧源、
２２はコンデンサ、２３は反転増幅器でおる。すなわち
、誤差増幅回路７′は抵抗１６，１７ｔｌＬ：ｒ：／テ
ン′ｒ２２および反転増幅器２３ＩＣよ多構成されてお
シ、またオフセット電圧調整回路１２は抵抗１９、ボテ
ンシ璽メータ２０および基準電圧源２１によ多構成され
ている。8 is a voltage controlled oscillation circuit, 9 is a 1-2 frequency divider circuit, and 10 is a 1-2 frequency divider circuit.
11 is a 1-2 frequency divider circuit, 12 is an error amplifier offset voltage adjustment circuit, 13 is a comparator, and 14 is a switch circuit. FIG. 2 shows the error amplifier circuit 7' off-sect voltage v4! 15 to 19 are specific examples of the portion including the I circuit 12, the comparator 13, and the switch circuit 14.
is a resistor, 20 is a voltage meter, 21 is a reference voltage source,
22 is a capacitor, and 23 is an inverting amplifier. That is, the error amplification circuit 7' includes resistors 16, 17tlL:r:/ten'r22 and an inverting amplifier 23IC, and the offset voltage adjustment circuit 12 includes a resistor 19, a potentiometer 20, and a reference voltage source 21. It is composed of many parts.
第１図の回路は第３図の従来例と基本的には同じ動作を
行なう。いま位相誤差θｅがあったとすると誤差増幅回
路７′（すなわち反転増幅器２３）の出力にはそれに応
じたオフセット実圧が発生する。したがって基準電圧源
２１の電圧をボテンシ目メータ２０によ多分割し、抵抗
１９を通じて反転増幅器２３の反転入力端子に電流加算
を行ない、オフセット電圧が＠Ｏ＃になるようにボテン
シ冒メータ２０を調整すれば、結果的に位相誤差が１０
”になったことと等価であシ、分離度が改善される。The circuit shown in FIG. 1 basically operates in the same way as the conventional example shown in FIG. If there is a phase error θe, a corresponding offset actual pressure will be generated at the output of the error amplifier circuit 7' (ie, the inverting amplifier 23). Therefore, the voltage of the reference voltage source 21 is multi-divided by the potentiometer 20, current is added to the inverting input terminal of the inverting amplifier 23 through the resistor 19, and the potentiometer 20 is adjusted so that the offset voltage becomes @O#. As a result, the phase error becomes 10
”, and the degree of separation is improved.
また、Ｉ−ｄｅＬ２の出力直流電圧の変化は入力レベ／
Ｉ／に比例しているので、これを比較器１３によル検出
し、ある入力レベル以下でスイッチ回路１４がオンとな
るように構成すれば、無人力時の反転増幅器２３の出力
オフセット電圧は抵抗１９と１５との比で決まるため、
抵抗１５ｔ″抵抗１９の１／１００程度に設定すること
により、オフセット電圧は非常に小さくなシ、キャプチ
ャレンジの中心がずれるようなことはない。In addition, the change in the output DC voltage of I-deL2 is
Since it is proportional to I/, if this is detected by the comparator 13 and the switch circuit 14 is configured to turn on below a certain input level, the output offset voltage of the inverting amplifier 23 during unattended operation will be Since it is determined by the ratio of resistors 19 and 15,
By setting the resistor 15t'' to about 1/100 of the resistor 19, the offset voltage is extremely small and the center of the capture range will not shift.
（発明の効果）
以上述べたように従来のＡＭステレオ復調回路に誤差増
幅器のオフセット電圧調整回路、入力レベル検出回路お
よびスイッチ回路を追加することによ〕、無人力時のキ
ャプチャレンジの中心ｄｆｆれること中７リー２ンの調
整によるＰＬＬの動作の固定ができなくなることなどを
引き起こす事なしに分離度を改善できるといり利点があ
る。(Effect of the invention) As described above, by adding the offset voltage adjustment circuit of the error amplifier, the input level detection circuit, and the switch circuit to the conventional AM stereo demodulation circuit, the center dff of the capture range during unattended operation can be Among other things, there is an advantage in that the degree of separation can be improved without causing the PLL operation to become unfixed due to the adjustment of the 7-lead 2-line.
第１図は本発明の一実施例を示すブロック図、！２図は
第１図中の誤差増＠回路７ｆｃ中心とする部分のよシ詳
細なブロック図、第３図は従来のＡＭステレオ復調回路
のブロック図である。
ｌ・・・信号入力端子、２・・・同相検波回路、３・・
・直交検波回路、４・・・マドＩ）クス回路、５・・・
右チャンネル出力端子、６・・・左チヤンネル出力端子
、７・・・誤差増幅回路、８・・・電圧制御発振回路、
９・・・１／２分周回路、１０・・・１／２分周回路、
１１・・・１／２分周回路、１２・・・誤差増幅器のオ
フセラトル整回路、１３・・・比較器、１４・・・スイ
ッチ回路、１５・・・抵抗、１６・・・抵抗、１７・・
・抵抗、１８・・・抵抗、１９・・・抵抗、２０・・・
ボテンシ冒メータ、２１・・・基準電源、２２・・・コ
ンデンサ、２３・・・反転増幅器。
第２ 図FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a more detailed block diagram of a portion centered on the error increase circuit 7fc in FIG. 1, and FIG. 3 is a block diagram of a conventional AM stereo demodulation circuit. l...Signal input terminal, 2...In-phase detection circuit, 3...
・Quadrature detection circuit, 4...Madox circuit, 5...
Right channel output terminal, 6... Left channel output terminal, 7... Error amplifier circuit, 8... Voltage controlled oscillation circuit,
9...1/2 frequency divider circuit, 10...1/2 frequency divider circuit,
DESCRIPTION OF SYMBOLS 11... 1/2 frequency divider circuit, 12... Off cellat adjustment circuit of error amplifier, 13... Comparator, 14... Switch circuit, 15... Resistor, 16... Resistor, 17...・
・Resistance, 18...Resistance, 19...Resistance, 20...
Potentiometer, 21... Reference power supply, 22... Capacitor, 23... Inverting amplifier. Figure 2
Claims (1)
回路およびマトリクス回路により構成され、さらに入力
レベル検出回路および該検出回路により制御されるスイ
ッチ回路および前記誤差増幅器のオフセット電圧調整回
路を具備し、前記オフセット電圧調整回路は前記誤差増
幅器に加わる信号の位相誤差に応じて前記誤差増幅器の
比較基準電圧を調節することを特徴とするＡＭステレオ
復調回路。It is composed of an in-phase detection circuit, a quadrature detection circuit, a voltage controlled oscillation circuit, a frequency dividing circuit, and a matrix circuit, and further includes an input level detection circuit, a switch circuit controlled by the detection circuit, and an offset voltage adjustment circuit for the error amplifier. , wherein the offset voltage adjustment circuit adjusts a comparison reference voltage of the error amplifier according to a phase error of a signal applied to the error amplifier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17870184A JPS6156532A (en) | 1984-08-28 | 1984-08-28 | Am stereo demodulation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17870184A JPS6156532A (en) | 1984-08-28 | 1984-08-28 | Am stereo demodulation circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6156532A true JPS6156532A (en) | 1986-03-22 |
Family
ID=16053041
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17870184A Pending JPS6156532A (en) | 1984-08-28 | 1984-08-28 | Am stereo demodulation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6156532A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH055127U (en) * | 1990-12-25 | 1993-01-26 | 誠二 川崎 | Excretion treatment device |
-
1984
- 1984-08-28 JP JP17870184A patent/JPS6156532A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH055127U (en) * | 1990-12-25 | 1993-01-26 | 誠二 川崎 | Excretion treatment device |
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