JPS6155946A - Structure of package for semiconductors - Google Patents
Structure of package for semiconductorsInfo
- Publication number
- JPS6155946A JPS6155946A JP17768584A JP17768584A JPS6155946A JP S6155946 A JPS6155946 A JP S6155946A JP 17768584 A JP17768584 A JP 17768584A JP 17768584 A JP17768584 A JP 17768584A JP S6155946 A JPS6155946 A JP S6155946A
- Authority
- JP
- Japan
- Prior art keywords
- tab
- semiconductors
- lead frame
- projection
- molded shape
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は内部にダイオード、トランジスタのような半導
体素子や、これら半導体の集積回路（以下半導体類と称
す）を気密収納保持するキャピテイを有する熱可塑性樹
脂からなるパッケージ構造に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a heat generating device having a cavity for airtightly storing semiconductor elements such as diodes and transistors, and integrated circuits of these semiconductors (hereinafter referred to as semiconductors). It relates to a package structure made of plastic resin.
半導体類のパッケージ方式として現在主流となっている
プラスチックパッケージは半導体類を予め装着したリー
ドフレームを上下両金型間に配置するとともに両型面に
形成されるキャビティ内に溶融樹脂を注入する方法によ
り製されている。しかしながらこの方法では樹脂封入中
に半導体類が溶融樹脂と直接接触することにより高温高
圧の状態におかれるため場合によつてはリード端子と半
導体類の電極を結んだワイヤが切れたりする稟かめる。Plastic packaging, which is currently the mainstream packaging method for semiconductors, uses a method in which a lead frame with semiconductors pre-installed is placed between upper and lower molds, and molten resin is injected into cavities formed on both mold surfaces. Manufactured. However, in this method, the semiconductors come into direct contact with the molten resin during resin encapsulation and are exposed to high temperature and high pressure conditions, which may cause the wires connecting the lead terminals and the electrodes of the semiconductors to break.
このようなモールド法の欠点を改良するために半導体類
を装着したリードフレームを内部に空洞を形成する２個
の樹脂成形品で挟んで合体する方法（特開昭５１−９８
９６９号）が提案されている。しかしなからかへる方法
において放散が困難で６’）特に集積度の高い半導体類
の場合は熱抵抗が大きくなり問題があった。また半導体
類を固定するリードフレームのタブは第３図に示すよう
に通常２本のタブつり９によって支えられているに過ぎ
ないため熱サイクル試験においてタブつりの熱変形によ
り半導体数の電極とリード端子を結ぶワイヤが変形した
りあるいは切断するといった欠点が認められた。In order to improve the drawbacks of such a molding method, a method was proposed in which a lead frame with semiconductors mounted thereon is sandwiched between two resin molded products that form a cavity inside.
No. 969) has been proposed. However, it is difficult to dissipate heat in the method of dipping from the inside, and 6'), especially in the case of highly integrated semiconductors, the thermal resistance becomes large, which poses a problem. In addition, since the tabs of the lead frame that fix the semiconductors are normally supported by only two tab hangers 9 as shown in Figure 3, thermal deformation of the tab hangers during thermal cycle tests caused the number of electrodes and leads of the semiconductors to deteriorate. Disadvantages were observed, such as the wires connecting the terminals deforming or breaking.
本発明はかへる状況に鑑みなされたものであって熱放散
にすぐれたワイヤの変形や断線のない信頼性にすぐれた
半導体通のパッケージ方式を提供することを目的とする
。The present invention has been made in view of the current situation, and it is an object of the present invention to provide a highly reliable semiconductor packaging system that has excellent heat dissipation and is free from wire deformation and disconnection.
かＸる目的は本発明によれば半導体類を収納する窪みを
有する２個一組からなる熱可塑性樹脂板状成形品の一方
の板状成形品の窪みにリードフレームのタブに当接する
突起を設げ、板状成形品とリードフレームを加熱融合合
体せしめる際に前記タブを突起を固着することにより達
成される。According to the present invention, the purpose of this invention is to provide a protrusion that abuts the tab of the lead frame in the recess of one of the two thermoplastic resin plate-shaped molded products each having a recess for accommodating the semiconductor. This is accomplished by fixing the tab to the protrusion when the plate-shaped molded product and the lead frame are heated and fused together.
以下本発明を実施例を示す図面を参照しながら説明すれ
ば、第２図は本発明で用いる板状成形品の内の一方を示
したもので８って中央部には半導体類を収納するための
窪み４が形成されており、さらにこの１み４には突起５
が形成されている。突起の個数、大きさ、形状および位
置はリードフレームタブの大きさに見合って設計される
。また、深さｊはタブのオフセット量に見合って設計さ
れる。The present invention will be described below with reference to drawings showing embodiments. Fig. 2 shows one of the plate-shaped molded products used in the present invention, and the central part is 8, which houses semiconductors. A recess 4 is formed for this purpose, and a protrusion 5 is formed in this recess 4.
is formed. The number, size, shape, and position of the protrusions are designed to match the size of the lead frame tab. Further, the depth j is designed in accordance with the amount of offset of the tab.
かかる板状成形品を用いて半導体類を装着したリードフ
レームを加圧一体化した半導体スーのパッケージの一部
横断面図を示したものが第１図である。第２図において
加圧一体化時に板状成形品２０半導体類を収納するため
の窪み４にある突起は、第３図に示すように加圧一体化
後、突起の一部の樹脂が溶融しリードフレームのタブ３
に溶着する。従って、該突起６がタブ５ＶＣ溶着してい
るため熱放散がよくなり、加圧一体化時にタブ５に突起
の一部の溶融軟化した樹脂が溶着するため、ワイヤ８が
変形したり、切断したりする程の変形をタブに与えない
。また加圧一体化後は一部の樹脂が溶融した突起６ＩＣ
よっても支えられるため、熱サイクル試論におけるタブ
つり９の熱変形によってワイヤ８が変形したりあるいは
切断するといった欠点が解消され、信頼性を向上させた
パッケージシングが可能となる。FIG. 1 shows a partial cross-sectional view of a semiconductor package in which a lead frame on which semiconductors are mounted is integrated under pressure using such a plate-shaped molded product. In FIG. 2, the projections in the recesses 4 for housing the plate-shaped molded products 20 and semiconductors during pressure integration are melted after the pressure integration, as shown in FIG. 3. Lead frame tab 3
Weld to. Therefore, since the protrusion 6 is welded to the tab 5VC, heat dissipation is improved, and the melted and softened resin of a part of the protrusion is welded to the tab 5 during pressurization and integration, so the wire 8 will not be deformed or cut. Do not deform the tab to the extent that it causes In addition, after pressurizing and integrating, some of the resin melted into the protrusion 6IC.
Therefore, the disadvantage that the wire 8 is deformed or broken due to thermal deformation of the tab hanger 9 during thermal cycle testing is eliminated, and packaging with improved reliability is made possible.
本発明に用いられる合体装置は加熱された板状成形品で
リードフレームをはさみ加圧一体化（ｒ
させることができさえずれびどのようなものであっても
よい。The combining device used in the present invention may be any type of device capable of sandwiching and pressurizing a lead frame between heated plate-shaped molded products and integrating them under pressure.
本発明に用いられる板状成形品用熱可塑性樹脂としては
それぞれの半導体類のパッケージに対する要求特性に応
じて徨々の融類のものが用いられる、が高い耐熱性（耐
熱変形性及び耐熱劣化性）と低い透湿性及び一定水準以
上の電気、機械特性に加え更に一定水準以上の成形性を
有することが必要である。As the thermoplastic resin for the plate-shaped molded product used in the present invention, a wide range of fusion resins are used depending on the required characteristics for each semiconductor package. ), low moisture permeability, electrical and mechanical properties of a certain level or higher, and moldability of a certain level or higher.
代表例としてはポリフェニレンオキサイドや、ポリエー
テルサルフオン、ポリスルフォン、フェノキシ樹脂、ポ
リアセタール等のエーテル系８４ｋ、ポリエチレンテレ
フタレート、ポリブチレンテレフタレート、ボリアリレ
ート等のエステル系樹脂、ポリカーボネート等の炭酸エ
ステル系樹脂、ポリアミド系樹脂の中でも吸水率の低い
グレード、ボリフエニレンサルフ１イド等の樹脂及びこ
れら樹脂の一部とガラス繊維を中心とした各種充填剤と
の組み合わせ等をあげることが出来る。Typical examples include polyphenylene oxide, ether 84k such as polyether sulfone, polysulfone, phenoxy resin, and polyacetal, ester resins such as polyethylene terephthalate, polybutylene terephthalate, and polyarylate, carbonate ester resins such as polycarbonate, and polyamide. Among the resins, examples include grades with low water absorption, resins such as polyphenylene sulfide, and combinations of some of these resins with various fillers, mainly glass fibers.
以下実施例により更に本発明を説明する。The present invention will be further explained below with reference to Examples.
実施例
熱変形温度（ＡＳＴＭ Ｄ−６４８，１ａ６ｋｇ／ａ
１１Ｉ荷Ｍ）が２６０°Ｃ以上のボリア ｙ−二１／
７サルフアイド樹脂により第２図に示すような中央部に
窪みを有し、この窪みに栗さＪ＝１２０μｍ、φ３（關
）の円柱状の突起を設けた板状成形品（１４Ｘ３２ｍｌ
！ｌ角）の合体面温度を５００℃に加熱するとともに、
半導体類が装着され、第３図に示すごとき２４ビンの５
運の構成単位よりなるリードフレームを予熱して加圧一
体化させた。Example heat distortion temperature (ASTM D-648, 1a6kg/a
11I load M) is 260°C or higher Boria y-21/
7 A plate-shaped molded product (14 x 32 ml) made of sulfide resin and having a depression in the center as shown in Fig. 2, and a cylindrical projection of chestnut size J = 120 μm and diameter 3 (diameter) in this depression.
! While heating the combined surface temperature of the l-angle) to 500℃,
Semiconductors are installed, and 5 of 24 bins as shown in Figure 3 are installed.
The lead frame, which consists of the structural units of luck, was preheated and integrated under pressure.
加圧一体化後のＩＣ接合部の熱抵抗は１００”Ｃ，／Ｗ
と板状成形品として半導体類を収納するための窪みに突
起を有しないものを用いた場合よりも３０％以上低減さ
せることが出来た。このことは特に大容量の半導体類の
長寿命化に大きく寄与すること大である。また、加圧一
体化後、ワイヤを顕微鏡によつて調べた結果、タブに突
起の一部の溶融軟化した樹脂が溶着するため、いずれの
ワイヤにおいても変形や切断等が認められず、また、熱
サイクル試験においてタブの熱変形によるワイヤの変形
や切断等も認められず封止性も良好で６った。Thermal resistance of IC joint after pressure integration is 100”C,/W
This could be reduced by more than 30% compared to the case of using a plate-shaped molded product having no protrusions in the recess for accommodating semiconductors. This greatly contributes to extending the lifespan of large-capacity semiconductors in particular. In addition, when the wires were examined under a microscope after being integrated under pressure, it was found that no deformation or breakage was observed in any of the wires because the melted and softened resin from part of the protrusion was welded to the tab. In the thermal cycle test, no deformation or breakage of the wire due to thermal deformation of the tab was observed, and the sealing performance was good and was rated 6.
比較例１
仮状成形品として半導体類を収納するための窪みに突起
を有しないものを用いた以外は実施例と同条件で加圧一
体化した。かかる後のＩＣ接合部の熱抵抗は１５０’Ｃ
／Ｗと比較的大きい値でめった。また、加圧一体化後熱
サイクル試験においてワイヤを顕微鏡によりて調べた結
果タブのＪ！面が支えられていないため、タブの熱変形
によってワイヤのネイルヘッド部が剥離しているものが
あることが確認された。Comparative Example 1 Pressure integration was carried out under the same conditions as in the example except that a temporary molded product having no protrusion in the recess for storing semiconductors was used. The thermal resistance of the IC junction after this is 150'C.
/W, which is a relatively large value. In addition, as a result of examining the wire under a microscope during the heat cycle test after pressure integration, the J! Because the surface was not supported, it was confirmed that some of the nail heads of the wires were peeling off due to thermal deformation of the tabs.
参考例
板状成形品として半導体類を収納するための窪みの而と
タブの裏面の開に、第２図においてＪ＝５８０μｍにな
るようにφ５ｒｎｍの円筒状の金属を介在させて加圧一
体化した。かかる後に顕微鏡でワイヤを観察した結果、
金属がタブを変形させてワイヤが変形したつ切断すると
いった欠点が認められた。Reference example A cylindrical metal with a diameter of 5rnm is interposed between the recess for storing semiconductors as a plate-shaped molded product and the opening on the back of the tab so that J=580μm in Fig. 2, and is integrated under pressure. did. After observing the wire under a microscope, we found that
Disadvantages were noted, such as the metal deforming the tab and causing the wire to deform and break.
以上の説明から明らかなよ５に本発明によれば突起を介
してリードフレームのタブを支承するようにしたのでワ
イヤの変形および断線がなく、熱放散性並びに信頼性に
優れた半導体類のパッケージの提供が可能になった。As is clear from the above explanation, according to the present invention, the tab of the lead frame is supported through the protrusion, so there is no deformation or disconnection of the wire, and the semiconductor package has excellent heat dissipation and reliability. is now available.
第１図は本発明に係る半導体類のパッケージ構造を示す
断面囚、第２図は板状成形品の平面図（ａ）およびＦｒ
面図（ｂ）、第３図はリードフレームの一構成単位を示
す平面図でろる。
符号の説明
１ リードフレーム ２ 板状成形品３ タブ
４ 窪み
５ 突起 ６ 突起の溶着部７ 半導体類
８ ワイヤ
９ タブつり
代坤人弁理士 若 林 邦 並ｒ〒
く・
姑
第１図
第２図
第３図Fig. 1 is a cross-sectional view showing the package structure of semiconductors according to the present invention, and Fig. 2 is a plan view (a) of a plate-shaped molded product and Fr.
The top view (b) and FIG. 3 are plan views showing one structural unit of the lead frame. Explanation of symbols 1 Lead frame 2 Plate-shaped molded product 3 Tab
4 Hollow 5 Protrusion 6 Welded part of the protrusion 7 Semiconductors 8 Wire 9 Tab suspension agent Kuni Wakabayashi, patent attorney, Figure 1, Figure 2, Figure 3
Claims (1)
熱可塑性樹脂板状成形品により、半導体類を装着したリ
ードフレームを挟み加熱融合合体せしめてなる半導体類
のパッケージにおいて、一方の板状成形品の窪みにリー
ドフレームのタブに当接する突起を設けるとともに、前
記タブと突起を固着してなることを特徴とする半導体類
のパッケージ構造。1. In a package for semiconductors, in which a lead frame on which semiconductors are mounted is sandwiched between a set of two thermoplastic resin plate-shaped molded products each having a recess for storing semiconductors, and heated and fused together, one of the plate-shaped A package structure for semiconductors, characterized in that a protrusion that abuts a tab of a lead frame is provided in a recess of a molded product, and the tab and the protrusion are firmly attached.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17768584A JPS6155946A (en) | 1984-08-27 | 1984-08-27 | Structure of package for semiconductors |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17768584A JPS6155946A (en) | 1984-08-27 | 1984-08-27 | Structure of package for semiconductors |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6155946A true JPS6155946A (en) | 1986-03-20 |
Family
ID=16035310
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17768584A Pending JPS6155946A (en) | 1984-08-27 | 1984-08-27 | Structure of package for semiconductors |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6155946A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100567129B1 (en) * | 2001-04-13 | 2006-03-31 | 앰코 테크놀로지 코리아 주식회사 | Molding die for manufacturing semiconductor package and method for molding semiconductor package using the same |
| US8766430B2 (en) | 2012-06-14 | 2014-07-01 | Infineon Technologies Ag | Semiconductor modules and methods of formation thereof |
| US9041460B2 (en) | 2013-08-12 | 2015-05-26 | Infineon Technologies Ag | Packaged power transistors and power packages |
-
1984
- 1984-08-27 JP JP17768584A patent/JPS6155946A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100567129B1 (en) * | 2001-04-13 | 2006-03-31 | 앰코 테크놀로지 코리아 주식회사 | Molding die for manufacturing semiconductor package and method for molding semiconductor package using the same |
| US8766430B2 (en) | 2012-06-14 | 2014-07-01 | Infineon Technologies Ag | Semiconductor modules and methods of formation thereof |
| US9041460B2 (en) | 2013-08-12 | 2015-05-26 | Infineon Technologies Ag | Packaged power transistors and power packages |
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