JPS615563A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS615563A JPS615563A JP12524684A JP12524684A JPS615563A JP S615563 A JPS615563 A JP S615563A JP 12524684 A JP12524684 A JP 12524684A JP 12524684 A JP12524684 A JP 12524684A JP S615563 A JPS615563 A JP S615563A
- Authority
- JP
- Japan
- Prior art keywords
- film
- electrodes
- elements
- electrode
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 10
- 229920001721 polyimide Polymers 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 239000009719 polyimide resin Substances 0.000 claims description 3
- 239000011347 resin Substances 0.000 claims description 3
- 229920005989 resin Polymers 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 12
- 238000000034 method Methods 0.000 abstract description 5
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 5
- 229910052681 coesite Inorganic materials 0.000 abstract description 4
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 4
- 239000000377 silicon dioxide Substances 0.000 abstract description 4
- 229910052682 stishovite Inorganic materials 0.000 abstract description 4
- 229910052905 tridymite Inorganic materials 0.000 abstract description 4
- 238000005530 etching Methods 0.000 abstract description 3
- 238000009434 installation Methods 0.000 abstract description 3
- 239000010453 quartz Substances 0.000 abstract 1
- 239000010408 film Substances 0.000 description 30
- 238000005516 engineering process Methods 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 239000005350 fused silica glass Substances 0.000 description 3
- 239000012528 membrane Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 238000005234 chemical deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 239000012808 vapor phase Substances 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- -1 for example Polymers 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 235000015067 sauces Nutrition 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は半導体装置の高集積化技術、特に半導体素子を
多段に形成して３次元化した半導体集積゛回路装置に関
する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a technology for highly integrating semiconductor devices, and particularly to a three-dimensional semiconductor integrated circuit device in which semiconductor elements are formed in multiple stages.
現在の半導体装置、たとえばＩＣの高集積化はテープ当
りの素子数をふやすことで２次元パターニングの微細化
の極限に達しようとしている。さらにこれを越えて高集
積化するため２次元ＩＣを多層に積み重ねる３次元ＩＣ
構造が提案されている。Current semiconductor devices, such as ICs, are becoming highly integrated, and by increasing the number of elements per tape, the miniaturization of two-dimensional patterning is reaching its limit. Furthermore, 3D ICs, in which 2D ICs are stacked in multiple layers, are used to achieve higher integration.
structure is proposed.
３次元ＩＣを実用化する一つの例として溶融石英などの
絶縁物の上に半導体シリコンを形成するＳＯＩ技術があ
る。（ｆｆ子材料１９８３年４月ｐ１０５〜１１０古川
静二部）
これはアモルファス半導体薄膜をたとえばＳｉへ膜上に
形成するもので、この半導体薄膜はたとえ゛ばシラン（
Ｓｊ＆）ガスをグロー放電で分解することにより、容易
ＫＳｉＯ＠膜上に牛導体膜を形成できる。この方法によ
れば現在の技術を使って薄膜化した複数のＭＯＳＦＥＴ
を基板上に多段に形成することが可能である。One example of putting three-dimensional ICs into practical use is SOI technology, in which semiconductor silicon is formed on an insulator such as fused silica. (FF Materials, April 1983, p. 105-110, Seiji Furukawa) This is a process in which an amorphous semiconductor thin film is formed on, for example, Si, and this semiconductor thin film is made of, for example, silane (
By decomposing Sj&) gas by glow discharge, a conductor film can be easily formed on the KSiO@ film. According to this method, multiple MOSFETs can be thinned using current technology.
can be formed in multiple stages on a substrate.
ところでこれまでの技術によれば、多段の素子間の絶縁
膜として無機材料、たとえばＣＶＤ（気相化学デポジッ
ト）法によるＳｉｎ、が用いられるが、その場合に下記
の問題が生じる。According to the conventional technology, an inorganic material such as Sin formed by CVD (vapor phase chemical deposition) is used as an insulating film between elements in multiple stages, but the following problems occur in this case.
すなわち、下層の素子の電極をアモルファスＳｉや金属
によって構成する場合、その部分の凹凸がｃｖＤ−ｓｔ
ｏ、膜の表面に凹凸となって生じ、と）め□）：範上層
の素子を形成することが困難である。That is, when the electrodes of the lower layer element are made of amorphous Si or metal, the unevenness of that part is cvD-st.
(o) Unevenness occurs on the surface of the film, and □): It is difficult to form an element in the upper layer.
とくに、薄膜化したＭＯＳＦＥＴの場合、設置場所が平
坦でないと凹凸段差のため上部配線の断線を生じたり、
ＭＯＳＦＥＴの特性的にばらつきを生じるおそれがあり
、このため上部素子の設置は平坦な部分を選ぶ必要があ
り、したがって集積化が充分に生かされないことになっ
た。In particular, in the case of thin-film MOSFETs, if the installation location is not flat, the upper wiring may break due to uneven steps.
There is a possibility that variations may occur in the characteristics of the MOSFET, and for this reason, it is necessary to select a flat area for installing the upper element, and therefore, integration is not fully utilized.
本発明は上記した問題を解決するためになされたもので
あり、その目的とするところ）言、一つの基板上に素子
を多段化する３次元デバイス構造において、段間に使わ
れる絶縁膜の上面を平坦化し、上部素子の設置を容易に
し、素子配置の自由度を増すことにある。The present invention has been made to solve the above-mentioned problems, and its purpose is to improve the upper surface of an insulating film used between stages in a three-dimensional device structure in which elements are multi-staged on one substrate. The objective is to flatten the structure, facilitate the installation of the upper element, and increase the degree of freedom in element arrangement.
本願において開示される発明のうち代表的なものの概要
を説明すれば下記のとおりである。A summary of typical inventions disclosed in this application is as follows.
すなわち、一つの基板上にアモルファスシリコンを用い
た半導体素子が絶縁膜を介して多段に形成された半導体
装置であって下段の半導体素子によって上記絶縁膜表面
に生じた凹凸が上記絶縁膜の一部であるポリイミド系樹
脂を介して平坦化され、その上に上段の半導体素子を形
成することにより、上段の素子の設置を容易とし、素子
配置の自由度を増加させて前記目的を達成できる。In other words, it is a semiconductor device in which semiconductor elements using amorphous silicon are formed in multiple stages on one substrate with an insulating film interposed therebetween, and the unevenness caused on the surface of the insulating film by the semiconductor elements in the lower stage is a part of the insulating film. By forming the upper semiconductor element on the flattened polyimide resin, the upper element can be easily installed and the degree of freedom in element arrangement can be increased to achieve the above object.
第１図乃至第１０図は本発明の一実施例を示すものであ
って、アモルファスシリコン（ａ−８４）を用いた３次
元インパーダ回洛の１ユニツトの製造プロセスの工程断
面図である。FIGS. 1 to 10 show an embodiment of the present invention, and are cross-sectional views of a manufacturing process for one unit of a three-dimensional impeller circuit using amorphous silicon (A-84).
以下各工程にそって具体的に述べる。Each process will be described in detail below.
（１」 第１図忙示すように溶融石英からなる基板１
を用意し、平坦化したその一生裏面上にＭｏ（モリブデ
ン）をメタライズし、ホトレジストを使用したエッチ処
理によりその一部をパターニングし １
てＭｏ電極２ａ 、２ｂ 、２ｃを形成する。このうち
、中央のＭＯ電極２ｂは図示されないが、前後方向に嶌
びて■。Ｇ電極として取り出される。(1) As shown in Figure 1, a substrate 1 made of fused silica
1, metallize Mo (molybdenum) on the flattened back surface, and pattern a part of it by etching using photoresist.
Then, Mo electrodes 2a, 2b, and 2c are formed. Of these, the central MO electrode 2b is not shown, but extends in the front-rear direction. It is taken out as a G electrode.
（２）全面に第２図に示すように、プラズマ、又はスパ
ッタ等によりＳｉＯ２を堆積し、ゲート絶縁膜としての
Ｓｉ’０２膜３を形成し、次いで５ｉＨ４（シラン）ガ
スをグロー放電中で分解することにより、Ｓｉｎ、膜３
上に、 ａ −Ｓｉ（アモルファス・シリコン）膜４を
形成する。なお、このａ−８ｉ膜４中九はＰ（リン）等
のドナをドープすることによりてｎ″″型導電導電性与
する。(2) As shown in Figure 2, SiO2 is deposited on the entire surface by plasma or sputtering to form a Si'02 film 3 as a gate insulating film, and then 5iH4 (silane) gas is decomposed in a glow discharge. By doing so, Sin, film 3
An a-Si (amorphous silicon) film 4 is formed thereon. The a-8i films 4 to 9 are doped with a donor such as P (phosphorus) to provide n'''' type conductivity.
（３） ホトレジストを使用したエッチ処理により、
中央のＭｏ電極２ｂ上のａ−８ｉ膜４ａを残して他を除
去し、さらに左右のＭｏ電極２ａ 、２ｂ上の一部Ｓｉ
ｎｇ膜３を除去する。このあと、ＡＬ（アルミニウム）
を蒸着又はスパッタし、ホトエッチすることによって、
Ａｎ電極５ａ 、５ｂ・・・を第３図のように形成する
。このうち、ａ−８ｉ膜４ａに接続されるＡｊｌ電極５
ｂ；５ｃをソース。(3) By etching using photoresist,
The a-8i film 4a on the central Mo electrode 2b is left and the rest is removed, and a part of the Si film on the left and right Mo electrodes 2a and 2b is removed.
NG film 3 is removed. After this, AL (aluminum)
By vapor depositing or sputtering and photoetching,
An electrodes 5a, 5b, . . . are formed as shown in FIG. Among these, the Ajl electrode 5 connected to the a-8i film 4a
b; Sauce 5c.
ドレインとして負荷ＭＯ８ＦＥＴが形成される（第１１
図参照）。A load MO8FET is formed as the drain (11th
(see figure).
１４ＪｃＶＤ（気相化学デポジット）法により５ｉｏｔ
を全面に堆積させ、第４図に示すように厚いＳｉへ膜６
を形成する。この５１０１膜６は同図に示すように、ａ
−８ｉ膜４ａ上の部分がその厚さ分だけ盛り上った状態
に形□成される。5iot by 14JcVD (vapor phase chemical deposition) method
is deposited on the entire surface, and as shown in FIG.
form. As shown in the figure, this 5101 film 6 has a
The portion on the -8i film 4a is formed in a raised state by the thickness thereof.
（５１再びＳｉＨ，をグロー放電中で分解するととによ
りａ−８ｉ膜をＳ１０．膜６上に形成し、さら忙その上
にＭｏ等をスパッタし、ホトエツチングを行うことによ
りて第５図忙示すように中央部の盛上った部分にａ−８
ｉ膜７と、その両端部に接続するＭｏ電極８を形成する
。なお、同図以降、Ｓｉｎ、膜６の下側の部分は省略し
てあられされる。(51 Again, by decomposing SiH in a glow discharge, an a-8i film is formed on the S10 film 6, and then Mo or the like is sputtered thereon and photoetched, as shown in Fig. 5). A-8 on the raised part in the center like this
An i film 7 and Mo electrodes 8 connected to both ends thereof are formed. Note that from the same figure onwards, the lower part of the Sin film 6 will be omitted.
（６１有機樹脂、例えばポリイミド系樹脂をフェス状で
全面にスピンナ塗□布し、そのあと熱処理硬化させるこ
とで第６図（示すようＫＳｉ０１膜 ６の凹部を埋める
ようにし、かつ上面が平坦になるポリイミド膜９を形成
する。(61 Organic resin, for example, polyimide resin, is applied with a spinner to the entire surface in the shape of a face, and then cured by heat treatment to fill the recesses of the KSi01 film 6 as shown in Figure 6, and to make the top surface flat. A polyimide film 9 is formed.
（７１ホトレジストによるマスン（図示されない）を使
用し、ポリイミド膜９の一部をエツチングして第７図に
示すように上部のａ−８ｉ膜７が露出する窓孔１０をあ
け邊とともに、Ｓ ｉ Ｏ！ Ｗｌｉ ６によりて埋め
込まれたアルミニウム電極５ｇ、５ｂに対応する部分に
窓孔１１をあける。(Using a mask (not shown) made of 71 photoresist, a part of the polyimide film 9 is etched to open a window 10 through which the upper A-8I film 7 is exposed as shown in FIG. A window hole 11 is made in a portion corresponding to the aluminum electrodes 5g and 5b embedded with O! Wli 6.
＋８１ 全面にプラズマ叉はスパッタによりＳｊＯｇ
を堆積し、第８図に示すようにＳｊＯ！１１１１２を形
成する。+81 SjOg on the entire surface by plasma or sputtering
is deposited, and SjO! is deposited as shown in FIG. 11112 is formed.
＋９７ ホトレジストを使用しＳｊＯｇを部分的にエ
ッチして第９図に示すようにゲート糖縁膜１２ａを残す
。なおこのとき、ポリイミド膜９の孔１１を通して８ｊ
Ｏ，膜６をエッチし、Ａ９電極５ａ。+97 Using photoresist, SjOg is partially etched to leave gate sugar border film 12a as shown in FIG. At this time, 8j is passed through the hole 11 of the polyimide film 9.
O, film 6 is etched, and A9 electrode 5a.
’ ５ｄを露出させる。’ Expose 5d.
■ さいごに、全面に人りを蒸着又はスパッタし、ホト
レジストを使用してエツチングを行うことにより、第１
０図に示すようにゲート絶縁ａｌ１２ａ上と、Ｍｏ電極
３、及び孔１１を通してアルミニウム電極５ａ、５ｄに
コンタクトするアルミニウム電極１３ａ、１３ｂ・・・
な形成し、３次元インバータ回路を完成する。このうち
、Ａｎ電極１３ａはＡ９電極５ａと一方（ＱＭｏ電極８
とを短絡するとともに■。ｕｔ（出力用）端子となる・
ゲート絶縁＠ １２ ａ上のＡｎ電極はｖｉｎ （入力
用）端子となる。他方のＭｏ’Ｈ１極８に接続されるＡ
ｊｌ電極はＧＮＤ（接地）ｆｓ子となる。ＡＡ’ｉｌ！
極５ｄに接続されるＡ９電極１３ｄはＶＤＤ （電源用
）端子となる。■ Finally, the first layer is deposited or sputtered on the entire surface and etched using photoresist.
As shown in Figure 0, aluminum electrodes 13a, 13b, .
and complete the three-dimensional inverter circuit. Among these, the An electrode 13a is connected to the A9 electrode 5a and one (QMo electrode 8
In addition to short-circuiting ■. It becomes the ut (output) terminal.
The An electrode on the gate insulation @12a becomes a vin (input) terminal. A connected to the other Mo'H1 pole 8
The jl electrode becomes a GND (ground) fs terminal. AA'il!
The A9 electrode 13d connected to the pole 5d becomes a VDD (power supply) terminal.
第１１図は第１θ図に示した３次元インバータの等価回
路図である。FIG. 11 is an equivalent circuit diagram of the three-dimensional inverter shown in FIG. 1θ.
実験によれば、チャネル長１０μｍで１段当りの遅延時
間６０μｓというデータが得られている。According to experiments, data has been obtained that the delay time per stage is 60 μs with a channel length of 10 μm.
以上実施例で述べた本発明忙よれば、工程１４１（第４
図）に示されるように下段の素子によるＳ ｉ Ｏ，膜
６の突出部分を埋め込むようにポリイミド膜９（第６図
）を形成して上面を平坦化するととにより、上段の素子
が設置しやすくなり、有効面積が増し、素子配置の自由
度が太ぎくなるとい５効来が得られる。According to the present invention described in the embodiments above, step 141 (fourth
As shown in Fig. 6, a polyimide film 9 (Fig. 6) is formed to bury the protruding portion of the SiO film 6 formed by the lower element, and the upper surface is flattened. Five advantages can be obtained: the device becomes easier to use, the effective area increases, and the degree of freedom in element arrangement increases.
以上本発明者によっズなされた発明の実施例圧もとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、その要旨を変更し −ない範
囲で種々変更可能・であることはいうまでもない。Although the invention has been specifically explained above based on the embodiments of the invention made by the present inventor, the present invention is not limited to the above embodiments, and can be modified in various ways without changing the gist thereof. It goes without saying that there is.
本発明は実施例に述べたような論理集積回路に適用して
もつとも有効である。The present invention is also effective when applied to logic integrated circuits such as those described in the embodiments.
本発嬰は上記以外にアモルファスシリコンを用゛。This product uses amorphous silicon in addition to the above.
いたイメージセンサ、電荷結合デバイ、ス・シ嘗ットキ
バリア及びＰｉＮダイオ−、ドを多段に形成する場合に
おいても同様に応用できる。 □ 、２The present invention can be similarly applied to the case where image sensors, charge coupled devices, switching barriers, and PiN diodes are formed in multiple stages. □ , 2
第１図乃至館１０図は本発明の一夾施例を示７す３次元
インバータ回路の１ユニツトの製造プロセスの工程断面
図である。
第１１図は第１０図に対応する等価回路図である。
ｌ・・・溶融石英基板、２・・・ＭＯ電極、３・・・Ｓ
ｉ０ｇ膜、４”−ａ−８ｊ膜、５・Ａｎ電極、５−８
ｉ Ｏ！膜、７−ａ−８ｉ膜、８ ＝−Ｍ ｏ を極、
９・・・ポリイミド膜、１０，１１・・・窓孔、１２・
・・Ｓ ｉ ＯＨ膜、１３・・・ＡＪ電極。
代理人 弁理士 高 橋−明 夫 □第１図
第 ２ 図
第 ３ 図
第 ４ 図
第 ６ 図
第 ７ 図
第 ８ 図
第 ９ 図FIGS. 1 to 10 are cross-sectional views of a manufacturing process for one unit of a three-dimensional inverter circuit showing one embodiment of the present invention. FIG. 11 is an equivalent circuit diagram corresponding to FIG. 10. l...Fused quartz substrate, 2...MO electrode, 3...S
i0g film, 4”-a-8j film, 5・An electrode, 5-8
i O! membrane, 7-a-8i membrane, 8 = -M o as pole,
9... Polyimide membrane, 10, 11... Window hole, 12.
...S i OH film, 13...AJ electrode. Agent Patent Attorney Akio Takahashi □Figure 1 Figure 2 Figure 3 Figure 4 Figure 6 Figure 7 Figure 8 Figure 9
Claims (1)
多段に形成された半導体装置であって、下段の半導体素
子によって上記絶縁膜表面に生じた凹凸が有機樹脂を介
して平坦化されその上に上段の半導体素子が形成されて
いることを特徴とする半導体装置。 ２、上記有機樹脂はポリイミド系樹脂からなる特許請求
の範囲第１項に記載の半導体装置。 ３、上記複数の半導体素子にはそれぞれ一部にアモルフ
ァスシリコンが用いられている特許請求の範囲第１項又
は第２項に記載の半導体装置。[Claims] 1. A semiconductor device in which a plurality of semiconductor elements are formed in multiple stages on one substrate with an insulating film interposed therebetween, wherein the unevenness caused on the surface of the insulating film by the semiconductor elements in the lower stage is made of an organic resin. What is claimed is: 1. A semiconductor device characterized in that the semiconductor device is planarized through the substrate and an upper semiconductor element is formed thereon. 2. The semiconductor device according to claim 1, wherein the organic resin is made of polyimide resin. 3. The semiconductor device according to claim 1 or 2, wherein amorphous silicon is used in a part of each of the plurality of semiconductor elements.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12524684A JPS615563A (en) | 1984-06-20 | 1984-06-20 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12524684A JPS615563A (en) | 1984-06-20 | 1984-06-20 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS615563A true JPS615563A (en) | 1986-01-11 |
Family
ID=14905383
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12524684A Pending JPS615563A (en) | 1984-06-20 | 1984-06-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS615563A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1070657C (en) * | 1995-10-06 | 2001-09-05 | 株式会社日立制作所 | Motor controller |
-
1984
- 1984-06-20 JP JP12524684A patent/JPS615563A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1070657C (en) * | 1995-10-06 | 2001-09-05 | 株式会社日立制作所 | Motor controller |
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