JPS6152818U - - Google Patents

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Publication number
JPS6152818U
JPS6152818U JP13684784U JP13684784U JPS6152818U JP S6152818 U JPS6152818 U JP S6152818U JP 13684784 U JP13684784 U JP 13684784U JP 13684784 U JP13684784 U JP 13684784U JP S6152818 U JPS6152818 U JP S6152818U
Authority
JP
Japan
Prior art keywords
fet
matching circuit
input
output matching
monolithic microwave
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13684784U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP13684784U priority Critical patent/JPS6152818U/ja
Publication of JPS6152818U publication Critical patent/JPS6152818U/ja
Pending legal-status Critical Current

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  • Microwave Amplifiers (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、従来のモノリシツク・マイクロ波F
ET増幅器の構造図、第2図はその実装法を示す
図、第3図および第4図はこの考案の一実施例に
よるモノリシツク・マイクロ波FET増幅器の構
造図、第5図はその実装法を示す図である。 1はFET、3はFETを構成するゲート電極
、4はドレイン電極、5は入力側整合回路、6は
出力側整合回路、7はGaAs等の半導体基板、
8は接地導体、9はバイア・ホールである。なお
、図中同一符号は同一、又は相当部分を示す。
Figure 1 shows a conventional monolithic microwave F
A structural diagram of an ET amplifier, FIG. 2 shows its mounting method, FIGS. 3 and 4 show a structural diagram of a monolithic microwave FET amplifier according to an embodiment of this invention, and FIG. 5 shows its mounting method. FIG. 1 is an FET, 3 is a gate electrode constituting the FET, 4 is a drain electrode, 5 is an input side matching circuit, 6 is an output side matching circuit, 7 is a semiconductor substrate such as GaAs,
8 is a ground conductor, and 9 is a via hole. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] FETおよび接地導体を半導体基板の同一面上
に形成し、この面と相対すを面に入出力整合回路
を形成し、前記FETのゲート電極・ドレイン電
極と入出力整合回路をバイア・ホールによつて導
通させたことを特徴とするモノリシツク・マイク
ロ波FET増幅器。
A FET and a ground conductor are formed on the same surface of a semiconductor substrate, an input/output matching circuit is formed on the opposite surface, and the gate electrode/drain electrode of the FET and the input/output matching circuit are connected by via holes. A monolithic microwave FET amplifier characterized in that it is conductive.
JP13684784U 1984-09-10 1984-09-10 Pending JPS6152818U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13684784U JPS6152818U (en) 1984-09-10 1984-09-10

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13684784U JPS6152818U (en) 1984-09-10 1984-09-10

Publications (1)

Publication Number Publication Date
JPS6152818U true JPS6152818U (en) 1986-04-09

Family

ID=30695280

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13684784U Pending JPS6152818U (en) 1984-09-10 1984-09-10

Country Status (1)

Country Link
JP (1) JPS6152818U (en)

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