JPS6151965A - Semiconductor memory device - Google Patents
Semiconductor memory deviceInfo
- Publication number
- JPS6151965A JPS6151965A JP59174652A JP17465284A JPS6151965A JP S6151965 A JPS6151965 A JP S6151965A JP 59174652 A JP59174652 A JP 59174652A JP 17465284 A JP17465284 A JP 17465284A JP S6151965 A JPS6151965 A JP S6151965A
- Authority
- JP
- Japan
- Prior art keywords
- film
- thin film
- semiconductor
- groove
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
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- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
（技術分野）
本発明は、半導体記憶装置にかかり、特に半導体を使用
してなるＩＣメモリの情報蓄積部の構造に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a semiconductor memory device, and particularly to the structure of an information storage section of an IC memory using a semiconductor.
（従来技術）
半導体基板、特にシリコン半導体基板上に形成する集積
回路は、高集積化、大容量化の方向をたどり、写真蝕刻
技術を使用した半導体表面の微細加工技術の開発が種々
になされている。このような中にあって、ＩＣメモリを
搭載した半導体ベレット法の縮小化の可能性及び大容量
化の可能性も（重々に追求されている。これ等の目的達
成のために、回路面からの情報蓄積方法の検討、又は製
造材料物質、情報蓄積部の構造からの拙々の情報蓄積方
法の検討が進められ、現在ダイナミックＲ，ＡＭのよう
なＩＣメそりに於いては、情報蓄積部（以下セルと称す
）を１個のトランジスタと１個の情−報蓄積餐分部で構
成するのが最も上記目的１こ適したものと考えられてい
る。該方法での情報蓄積方式では、該半６体ペレットの
大部分を占めるのは前記セル部の情報蓄積容量部面積で
ある。この理由からこの方式によるダイナミックＲＡＭ
のペレット面積の縮小化を計るためには、該情報蓄積容
量部面積を小さくすることが一番効果的となる。(Prior Art) Integrated circuits formed on semiconductor substrates, particularly silicon semiconductor substrates, are becoming more highly integrated and have larger capacities, and various microfabrication techniques for semiconductor surfaces using photolithographic techniques have been developed. There is. Under these circumstances, the possibility of downsizing and increasing the capacity of the semiconductor pellet method equipped with IC memory is also being actively pursued. Studies are progressing on information storage methods based on manufacturing materials and the structure of the information storage section, and currently in IC systems such as dynamic R and AM, the information storage section It is considered that a cell (hereinafter referred to as a cell) consisting of one transistor and one information storage section is most suitable for the above purpose.In the information storage method in this method, The area of the information storage capacity portion of the cell portion occupies most of the half-six-body pellet.For this reason, the dynamic RAM using this method
In order to reduce the area of the pellet, it is most effective to reduce the area of the information storage capacitor.
このような理由から、平面上での単位面積轟りの容量値
を大きくする方法として、信頼性の高い薄いシリコン酸
化膜を形成する方法、誘電率の高い誘電体簿膜の形成方
法、更には、半導体基板表面に溝を掘り溝の縦側面部も
容量部とした方法等穏々の方法が提案されている。しか
しダイナミックＲＡＭで容量が大容量化され、４メガビ
ット以上となったデバイスｌこ適用できる手法は未だ確
立されていない。For these reasons, as a method to increase the capacitance value per unit area on a plane, there are methods for forming a highly reliable thin silicon oxide film, a method for forming a dielectric film with a high dielectric constant, and a method for forming a dielectric film with a high dielectric constant. Mild methods have been proposed, such as a method in which a trench is dug in the surface of a semiconductor substrate and the vertical side surfaces of the trench are also used as a capacitive part. However, no method has yet been established that can be applied to devices in which the capacity of dynamic RAM has been increased to 4 megabits or more.
斯くなる大容量になると、１セル当りの平面積は１０μ
ｍ′以下となり、容量部のシリコン酸化膜で且つ信頼性
の高い膜の形成は不可能である。更に又、高竹電率膜の
形成ｉこ於いてもｇ電率が高いと膜中を流れる漏洩電流
が増加し易くなるという現象があり実現が容易でない。With such a large capacity, the flat area per cell is 10μ.
m' or less, and it is impossible to form a highly reliable silicon oxide film in the capacitive part. Furthermore, even in the formation of a film with a high electrical conductivity, there is a phenomenon in which the leakage current flowing through the film tends to increase when the electrical conductivity is high, making it difficult to realize this.
最後に半導体基板表面に溝を掘り溝の縦側面部も容量部
とした手法があるが、令息に提案された該方法では、セ
ル間の分離が困難となる。これは、各セル部に形成され
た溝間の電気的耐圧が、溝間距離の縮小と共に減少し、
あるセルの溝部に蓄えたｆ！を報が、該セルに隣接した
他のセルの溝部にあるｔｑ報で擾乱され易くなる。この
ため大容量ダイナミックＲＡＭに適した新規の情報蓄積
容量部の形成が望°まれる。Finally, there is a method in which trenches are dug in the surface of the semiconductor substrate and the vertical side surfaces of the trenches are also used as capacitors, but in this recently proposed method, it is difficult to separate cells. This is because the electrical breakdown voltage between the grooves formed in each cell part decreases as the distance between the grooves decreases.
f! stored in the groove of a certain cell. The signal is likely to be disturbed by the tq signal in the groove of another cell adjacent to the cell. Therefore, it is desired to form a new information storage capacity section suitable for large-capacity dynamic RAM.
（発明の目的）
本発明は、新規の情報蓄積部の形成及び構造を提供し、
大容量ダイナミックＲＡＭの実現を容易にぜんとしたも
のである。(Object of the invention) The present invention provides the formation and structure of a new information storage unit,
This makes it easy to realize a large-capacity dynamic RAM.
（発明の構成）
このために本発明に於いては、セル部の情報蓄積容量部
として半導体基板表面に溝を堀り、線溝の側面部に誘電
体範膜を形成し、該誘電体薄膜を被覆する姿態に半導体
薄膜を堆積し、該半導体薄膜が、セル部のトランジスタ
のノース／ドレイン領域となるようにする。斯くして蓄
積情報に対応する電荷は該半導体薄膜内に蓄えるように
する。(Structure of the Invention) For this purpose, in the present invention, a groove is dug in the surface of the semiconductor substrate as the information storage capacitor part of the cell part, a dielectric base film is formed on the side surface of the line groove, and the dielectric thin film is formed on the side surface of the line groove. A semiconductor thin film is deposited in such a manner as to cover the semiconductor thin film, and the semiconductor thin film becomes the north/drain region of the transistor in the cell portion. Charges corresponding to the stored information are thus stored within the semiconductor thin film.
麩（′こ又ＭＯＳトランジスタは該半導体薄膜層上に形
成する。A MOS transistor is formed on the semiconductor thin film layer.
本方式は、前述した既存の溝堀り容量と類似したところ
があるが、次の点で大きな相違かめる。Although this method is similar to the existing ditch digging capacity described above, there are major differences in the following points.
即ち、既存の溝堀り容量の場合には、蓄積情報に対応す
る電荷は、溝形成された半導体基板の表面領域に蓄えら
れるが、本発明に於いては、先述したように、溝側面又
は半導体基板表面の誹電体薄膜上に形成した半導体薄膜
層上に該電荷１ｒｉ：〃積される。That is, in the case of the existing grooved capacitor, the charge corresponding to the stored information is stored in the surface area of the semiconductor substrate where the groove is formed, but in the present invention, as described above, the charge corresponding to the stored information is stored in the groove side surface or The charges 1ri are accumulated on the semiconductor thin film layer formed on the dielectric thin film on the surface of the semiconductor substrate.
（発明の効果）
本発明に於いては、かくなる構造をもつため、通常の溝
掘り構造の場合に問題となった、セル間電気的耐圧の低
下に起因するセル間分配の困難が解消される。このため
溝間距離の近接は容易となり、高密度化はより容易とな
る。(Effects of the Invention) Since the present invention has such a structure, the difficulty in inter-cell distribution caused by a decrease in inter-cell electrical withstand voltage, which was a problem in the case of a normal grooved structure, is solved. Ru. Therefore, the distance between the grooves can be easily shortened, making it easier to increase the density.
（実施例）
次に実施例でもって本発明の詳細な説明を行う以下ｐ型
シリコン基板にセルを構成する場合について述べるが、
Ｌｆｆｉシリコン基板の場合でも、不純物の導冠氾が逆
になるだけで他は同様でめることに前身って言及してお
く。(Example) Next, the present invention will be explained in detail using an example. Below, a case will be described in which a cell is constructed on a p-type silicon substrate.
It should be mentioned that even in the case of Lffi silicon substrates, everything else is the same except that the impurity capacitance is reversed.
第１図に示すように導電製がｐ況のシリコン基板１０１
表面に公知のホトレジスト技術を使ってシリコン基板表
面蝕刻用のマスク材１０２に窓開けを施し弓１き（光い
てプラズマガス中でのドライエッチ又は化学薬品液での
ウェットエッチで該シリコン基板表面に溝１０３を形成
する。斯くした後第２図に示すようにマスク材１０２を
蝕刻し全部除去した後、？”９１０３の形成されたシリ
コン基板表面に膜厚が５０〜１ｏｏｏｆの泣いぴ電体ｖ
１０４を被着する。ここで当誘電体膜１０４は、例えば
シリコン酸化膜等の一層の絶縁膜、又はシリコン酸化膜
／シリコンｔ、５化願等の二層の絶縁膜で構成さｎる。As shown in FIG. 1, a silicon substrate 101 whose conductivity is p-state
A window is made on the surface of the mask material 102 for etching the surface of the silicon substrate using a known photoresist technique. A groove 103 is formed. After this, the mask material 102 is etched and completely removed as shown in FIG.
104 is applied. Here, the dielectric film 104 is composed of a single-layer insulating film such as a silicon oxide film, or a two-layer insulating film such as a silicon oxide film/silicon film.
斯くした後第３図に示すようＣ（：無定形又は多結晶の
４電呈がｎ型の有効不純物を含有する市１のシリコン薄
膜１０５−３シリコン半導体浩板而に堆積後、第４１に
示すようにｒ、ｉ Ｌ Ｏａ内に埋め込まれたシリコン
薄膜を残し、ｆｌ！ｌのシリコンｒｘ７１Ａは全面除去
する。ここで埋め込まれたシリコン薄膜はシリサイド、
旨融点笠Ｊｊｉでもよい。つぎに第５図に示すようにテ
ｉｆ報苺槓容に部となる領域の誘電体膜１０４−３残し
、油は除去す・５゜斯くしてｐ ４ｑの第２のシリコン
薄＋ｉ １０６ ；２−エピタキシャル又はＣＶＤ法に
て膜厚１０（ＪＱ〜５０００Ａ堆積する。After this, as shown in FIG. As shown, the silicon thin film embedded in r, i L Oa is left, and the silicon rx71A of fl!l is completely removed.The silicon thin film embedded here is made of silicide,
It may be the melting point Kasa Jji. Next, as shown in FIG. 5, the dielectric film 104-3 is left in the area that will become the contact area, and the oil is removed. 2 - A film thickness of 10 (JQ~5000A) is deposited by epitaxial or CVD method.
引き続いてイオン注入、熱拡散で４′厄型がｎ型の１効
不純物を選択的に該ｐ型の第２のシリコン薄膜層１０ｂ
の一台す開成に尋人しｒＮＪシリコン分膜１０７を形成
する。ＪＩＪｒ＜シだ仮象ｎ型シリコン薄膜１０７を公
知の蝕刻技術でエツチングし該ｎ型シリコン溌膜１０７
表面１こシリコン酸化膜等の絶縁膜で層間絶縁膜１０８
を形成する。Subsequently, by ion implantation and thermal diffusion, the 4' single-effect impurity, which is n-type, is selectively added to the p-type second silicon thin film layer 10b.
An RNJ silicon film 107 is formed by using one of the wafers. The virtual n-type silicon thin film 107 is etched using a known etching technique to form the n-type silicon exfoliated film 107.
An interlayer insulating film 108 is made of an insulating film such as a silicon oxide film on one surface.
form.
次に第７図に示すようにシリコン薄膜１０６表面を熱酸
化しｒ、４０Ｓトランジスタのゲート膜１０９を形成し
、ポリシリコン高融点金属、クリサイド等でゲート電極
１１０を形成する。続いて第８図に示すように層間膜１
１１を形成し、トランジスタのソース／ドレイン領域と
なる？領域１１２を作り、コンタクト開孔を施してアル
ミ配線１１３を行う。斯くして本発明のセル構造を具備
したＩＣメモリーのセル部が構成される。Next, as shown in FIG. 7, the surface of the silicon thin film 106 is thermally oxidized to form a gate film 109 of a 40S transistor, and a gate electrode 110 is formed of polysilicon, a high melting point metal, crystalide, or the like. Next, as shown in FIG.
11 and becomes the source/drain region of the transistor? A region 112 is created, a contact hole is formed, and an aluminum wiring 113 is formed. In this way, a cell portion of an IC memory having the cell structure of the present invention is constructed.
木刀式ｌこ於いては、情報の蓄積がｎ型シリコン？Ｌｔ
Ｘ膜１０７に行われるため情報電圧によって容量部の容
量値が変化する。これを防止する手法として
次に第９図乃至第１２図に示す方法をとると斯くなる問
題は解消する。第９図に示すようにシリコン基板２０１
表面に第１の実施例の場合と同様ｌこ溝２０２を形成後
、第１０図に示すように情報蓄積容量部となる領域のシ
リコン基板内に拡散用マスク材２０３をマスクにして選
択的にｐ型の不純物例えばボロンを拡散導入し、ｐ 領
域２０４を溝２０２周辺部に形成する（第１０図）。こ
こで該ｐ 領域表面の不純物濃度は１０１６〜１０１０
２０ａｔｏ ／（７ｄ と高濃度になる。斯くした後
拡散用マスク材２０３及び拡散時形成されたｐ型不純物
を含む酸化膜２０５を除去する。In the wooden sword style, is the information stored in n-type silicon? Lt.
Since this is applied to the X film 107, the capacitance value of the capacitor section changes depending on the information voltage. If the method shown in FIGS. 9 to 12 is adopted as a method for preventing this, the problem will be solved. As shown in FIG. 9, a silicon substrate 201
After forming the groove 202 on the surface as in the first embodiment, selectively depositing the diffusion mask material 203 into the silicon substrate in the area that will become the information storage capacitor, as shown in FIG. A p-type impurity, such as boron, is diffused and introduced to form a p-type region 204 around the groove 202 (FIG. 10). Here, the impurity concentration on the surface of the p region is 1016 to 1010
The concentration is as high as 20ato/(7d).After this, the diffusion mask material 203 and the oxide film 205 containing p-type impurities formed during the diffusion are removed.
このようにした後、第１１図に示すように先述した実施
例と同様、薄い誘電体膜２０６を形成し情報の蓄積され
る領域即ちｎ型シリコン薄膜２０７、ＭＯＳ）ランジス
タの形成されるシリコン薄膜２０８、層間絶縁膜２０９
を設け、更にゲート膜２１０、ゲート電極２１１を形成
する。引き続いて第１２図に示すように眉間膜２１２、
ＭＯＳトランジスタのソース／ドレイン領域となる層領
域２１３を作り、コンタクト開孔を施してアルミ配線２
１４を行う。After this, as shown in FIG. 11, a thin dielectric film 206 is formed in the same manner as in the previous embodiment, and an area where information is stored, that is, an n-type silicon thin film 207, a silicon thin film where MOS transistors are formed. 208, interlayer insulating film 209
A gate film 210 and a gate electrode 211 are further formed. Subsequently, as shown in FIG. 12, the glabellar membrane 212,
A layer region 213 that will become the source/drain region of the MOS transistor is created, contact holes are formed, and aluminum wiring 2 is formed.
Do step 14.
斯くして、先述した情報蓄積容量部の情報電圧による容
量値の変イヒは防止できる。これは、該情報蓄積容量部
のシリコン基板内に高濃度のｐｍ不純物が導入されるた
め、該領域のシリコン基板の表面電圧降下がほとんど生
じなくなるためである。In this way, the above-mentioned change in the capacitance value of the information storage capacitor section due to the information voltage can be prevented. This is because a high concentration of pm impurity is introduced into the silicon substrate of the information storage capacitor, so that almost no surface voltage drop occurs on the silicon substrate in this region.
このことについて第１３図をもとに説明する。This will be explained based on FIG. 13.
同図は、ｐ型シリコン基板３０１上に形成した１００Ａ
のシリコン酸化膜３０２上にアルミ電極３０３を形成し
ＭＯＳダイオードのゲート電圧ＶＯと容量（ｉｆ Ｃの
関係を示す。ここでＣｏは誘電体であるシリコン酸化膜
の単位面積当りの容量でありＣｄはシリコン基板表面電
圧降下による空乏層の容量で次式で表わされる。The figure shows a 100A film formed on a p-type silicon substrate 301.
An aluminum electrode 303 is formed on the silicon oxide film 302 of the MOS diode, and the relationship between the gate voltage VO and the capacitance (if C) is shown. The capacitance of the depletion layer due to the silicon substrate surface voltage drop is expressed by the following equation.
但し、ｑけ紫電荷量、＆ｓｉけＳｉの誘電率Ｎ入はｐ歴
不純物濃度、φＳけシリコン基板表面電圧を表わす。か
くすると
となる。図中Ａ、Ｂの曲線はシリコン基板Ｎ人が約５
Ｘ Ｉ Ｑ” ａｔｏｍｓ／ｄ、Ｉ Ｘ １０” ａｔ
ｏｍ３．／７の場合である。ｈｏ場合ゲー＋、３圧ＶＧ
がＯＶと５Ｖで容量値Ｃが大きく変化するが、シリコン
基板濃度が犬さく）上るとＢの様にゲート電圧；こ↓る
容量１直Ｃの変化は小さくなる。通常のダイナミックＲ
ＡＭで使用する蓄積清報電圧は５■以下であるため、シ
リコン基板濃度が〜１０ ” ａｉＯｒｎｓ ／Ｃｎｌ
Ｔあれば、はとんど情報電圧による容量値の変化ば
みられなくなる。However, q represents the violet charge amount, &si represents the dielectric constant of Si, N represents the p history impurity concentration, and φS represents the silicon substrate surface voltage. Thus, it becomes. The curves A and B in the figure are approximately 5
X I Q" atoms/d, I X 10" at
om3. /7 is the case. Ho case +, 3 pressure VG
The capacitance value C changes greatly between OV and 5V, but as the silicon substrate concentration increases, as shown in B, the change in the capacitance 1DC becomes smaller. normal dynamic R
Since the accumulation voltage used in AM is less than 5μ, the silicon substrate concentration is ~10” aiOrns/Cnl
If T is present, only the change in capacitance value due to the information voltage will be observed.
その他、該蓄積清報電圧による蓄積５咎量値の変化を防
止する方法としては、第９図乃至第２図に示したｐ 領
ｊ或２０４域に相当する領域をＮ産Ｈにしてし１つこと
も有効である。値しこの場合りこは、該Ｎ型層領域に直
流の一定電圧を印加することが必要である。In addition, as a method for preventing changes in the accumulated charge value due to the accumulated clearing voltage, the area corresponding to the p area j or the 204 area shown in FIGS. 9 to 2 is set to N output H. This is also effective. In this case, it is necessary to apply a constant DC voltage to the N-type layer region.
（発明の効果）
最後に本発明によれば、セル部に外部からアルファ線等
のイオンがおってもソフトエラーは生じない。これは、
債報蓄菫部が絶縁膜上に形成され空乏層が祇とんどない
ためである。このため本発明では、ベレット面積を犬き
くするよう；ケソフトエラ一対末が不要と７より高集積
化、犬容致化により適したものとなる。(Effects of the Invention) Finally, according to the present invention, soft errors do not occur even if ions such as alpha rays enter the cell portion from the outside. this is,
This is because the depletion layer is formed on the insulating film and there is almost no depletion layer. For this reason, in the present invention, the bullet area is reduced; a pair of ends of the Kesoftera is unnecessary, and the present invention is more suitable for high integration and for dog-friendly use than 7.
第１図〜第１２図は本発明の実施例を断面図で示したも
のであり、第１３図は、慣報蓄撰容量値を情報電圧の関
係を示す図でりる。
１０１・・・・・・シリコン基板、１０２・・・・・・
マスク材、１０３・・・・・・病、１０４・・・・・・
誘電体膜、１０５・・・・・・第１のシリコン薄膜、１
０６・・・・・・第２のシリコン薄膜、１０７・・・・
・・ｎｆｉシリコン薄膜、１０８・・・・・・層間絶縁
膜、１０９・・・・・・ゲートＪ漠、１１０・・・・・
・ゲ）’ｕｉ；Ｑ、１１１・・・・・・層間膜、１１２
・・・・・・計 領域、１１３・・・・・・アルミ配線
、２０１・・・・・・シリコン基板、２０２・・・・・
・溝、２０３・・・・・・波数用マスク材、２０４・・
・・・・ｐ゛８８領域０５・・・・・・ｐ型不純物を含
む酸化膜、２０６・・・・・・誘電体膜、２０７・・・
・・・ｎ型シリコン薄躾、２０８・・・・・・シリコン
＃Ｕ、２０９・・・・・・層間絶ｇ、膜、２１０・・・
・・・ゲート膜、２１１・・・・・・ゲート電極、 ２
１２・・・・・・Ｊ＠間ｊ換、２１３・・・・・・ｎ十
領域、２１４・・・・・・アルミ配線、３０１・・・・
・・シリコン基板、３０２・・・・・・シリコン絃化膜
、３０３・・・・・・アルミしを、Ｖｏ・・・・・ゲー
ト電圧、Ｃ・・・・・・容量値、Ｃｏ・−・・・シリコ
ン酸化膜８二、Ｃａ・・・・・・空乏層の容量。
筋１図 第、５１￥１
筋２し 第６図
ＩＡり
筋４図 筋６図
心７図
第ｎ図
第１ど図1 to 12 are cross-sectional views of an embodiment of the present invention, and FIG. 13 is a diagram showing the relationship between the accumulated storage capacity value and the information voltage. 101...Silicon substrate, 102...
Mask material, 103...disease, 104...
Dielectric film, 105...First silicon thin film, 1
06...Second silicon thin film, 107...
...NFI silicon thin film, 108...Interlayer insulating film, 109...Gate J desert, 110...
・Ge)'ui;Q, 111... Interlayer film, 112
...Total area, 113 ... Aluminum wiring, 201 ... Silicon substrate, 202 ...
・Groove, 203... Wave number mask material, 204...
... p'88 region 05 ... oxide film containing p-type impurity, 206 ... dielectric film, 207 ...
...N-type silicon thin film, 208...Silicon #U, 209...Interlayer separation g, film, 210...
... Gate film, 211 ... Gate electrode, 2
12...J@j exchange, 213...n ten area, 214...aluminum wiring, 301...
...Silicon substrate, 302...Silicon film, 303...Aluminum film, Vo...Gate voltage, C...Capacitance value, Co...- ...Silicon oxide film 82, Ca...Capacity of depletion layer. Line 1 Figure 51￥1 Line 2 Figure 6 IA Line 4 Figure 6 Center Center Figure 7 Figure n Figure 1
Claims (2)
と、容量部とを含んでなる半導体記憶装置において、半
導体基板の一主面から該半導体基板内部に延在して形成
された溝の側面及び底面と該半導体基板の一主面の一部
上に積層して絶縁膜が形成され、更に該絶縁膜上と半導
体基板表面を被覆して半導体薄膜が形成され該半導体薄
膜層に上記絶縁ゲート型電界効果トランジスタが形成さ
れることを特徴とした半導体記憶装置。(1) In a semiconductor memory device including an insulated gate field effect transistor of an information storage section and a capacitor section, a side surface of a trench formed extending from one main surface of a semiconductor substrate into the inside of the semiconductor substrate; An insulating film is laminated on the bottom surface and a part of the main surface of the semiconductor substrate, and a semiconductor thin film is formed to cover the insulating film and the surface of the semiconductor substrate, and the insulated gate type is formed on the semiconductor thin film layer. A semiconductor memory device characterized in that a field effect transistor is formed.
した絶縁膜上に形成した半導体薄膜に有効不純物が注入
され、該絶縁膜が前記容量部の誘電体膜、半導体基板が
容量電極半導体薄膜の有効不純物を注入した領域が、情
報の電荷蓄積部となっていることを特徴とした特許請求
範囲（１）頂記載の半導体記憶装置。(2) An effective impurity is injected into a semiconductor thin film formed on an insulating film laminated on at least the side and bottom surfaces of the groove, and the insulating film is a dielectric film of the capacitive part, and the semiconductor substrate is a capacitive electrode semiconductor. A semiconductor memory device according to claim 1, wherein the region of the thin film into which effective impurities are implanted serves as an information charge storage section.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59174652A JPS6151965A (en) | 1984-08-22 | 1984-08-22 | Semiconductor memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59174652A JPS6151965A (en) | 1984-08-22 | 1984-08-22 | Semiconductor memory device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6151965A true JPS6151965A (en) | 1986-03-14 |
Family
ID=15982333
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59174652A Pending JPS6151965A (en) | 1984-08-22 | 1984-08-22 | Semiconductor memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6151965A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56107571A (en) * | 1980-01-30 | 1981-08-26 | Fujitsu Ltd | Semiconductor memory storage device |
| JPS56133866A (en) * | 1980-03-21 | 1981-10-20 | Fujitsu Ltd | Manufacture of semiconductor memory |
| JPS58154256A (en) * | 1982-03-10 | 1983-09-13 | Hitachi Ltd | Semiconductor memory and preparation thereof |
| JPS5982761A (en) * | 1982-11-04 | 1984-05-12 | Hitachi Ltd | Semiconductor memory |
-
1984
- 1984-08-22 JP JP59174652A patent/JPS6151965A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56107571A (en) * | 1980-01-30 | 1981-08-26 | Fujitsu Ltd | Semiconductor memory storage device |
| JPS56133866A (en) * | 1980-03-21 | 1981-10-20 | Fujitsu Ltd | Manufacture of semiconductor memory |
| JPS58154256A (en) * | 1982-03-10 | 1983-09-13 | Hitachi Ltd | Semiconductor memory and preparation thereof |
| JPS5982761A (en) * | 1982-11-04 | 1984-05-12 | Hitachi Ltd | Semiconductor memory |
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