JPS6148282B2 - - Google Patents
Info
- Publication number
- JPS6148282B2 JPS6148282B2 JP4182379A JP4182379A JPS6148282B2 JP S6148282 B2 JPS6148282 B2 JP S6148282B2 JP 4182379 A JP4182379 A JP 4182379A JP 4182379 A JP4182379 A JP 4182379A JP S6148282 B2 JPS6148282 B2 JP S6148282B2
- Authority
- JP
- Japan
- Prior art keywords
- switch element
- capacitor
- oscillation
- frequency
- time
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000010355 oscillation Effects 0.000 claims description 37
- 239000003990 capacitor Substances 0.000 claims description 35
- 239000013078 crystal Substances 0.000 claims description 6
- 238000005513 bias potential Methods 0.000 description 12
- 238000010586 diagram Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 3
- 230000003321 amplification Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/30—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator
- H03B5/32—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator
Landscapes
- Oscillators With Electromechanical Resonators (AREA)
Description
【発明の詳細な説明】
本発明は水晶発振回路に於ける周波数調整に、
特に発振回路に於ける発振インバータの入出力端
に接続される容量を、スイツチ素子によつて、該
スイツチ素子のオン―オフ時間の割合を変化させ
る事により、容量値を時分割的に変化させて、周
波数の調整を行う方式に関したものであり、この
時に発生する問題点の解決にある。[Detailed Description of the Invention] The present invention provides frequency adjustment in a crystal oscillation circuit.
In particular, the capacitance value connected to the input and output terminals of the oscillation inverter in the oscillation circuit is changed in a time-sharing manner by using a switch element and changing the ratio of the on-off time of the switch element. The purpose of this invention is to solve the problems that occur when adjusting the frequency.
従来、電子時計に用いられる水晶発振回路の周
波数調整法の１つとして、第１図ａに示される様
な方式が考えられてきた。第１図ａに於いて、１
は時間基準となる水晶振動子、２は帰還抵抗、３
は発振インバータ、４は分周回路、５はスイツチ
素子、６は発振インバータ３の出力端に接続され
た容量体、７は発振インバータ３の入力端に接続
された容量体、８は周波数調整用の容量体であ
る。また９は、発振インバータ３の入力端、１０
はスイツチ素子５のオン―オフ時間を制御する信
号である。更にVddはこの一例に於ける最高電位
を示し、Vssは最低電位を示している。この方式
に於いて、スイツチ素子５を制御する信号１０に
よつて、スイツチ素子５がオフの時、発振インバ
ータ３の入力端９に接続される容量は、容量体７
の値となり、スイツチ素子５がオンの時、発振イ
ンバータ３の入力端９に接続される容量は、容量
体７と容量体８の和となる。ここで容量体７に於
ける発振周波数を１、容量体７と容量体８の和
に於ける発振周波数を２とすると、１及び
２は常に一定となる。この状態で、スイツチ素子
５を制御する信号１０のオン―オフ時間を変化さ
せると、１にて発振させる時間と、２にて発
振させる時間との比が変化し、次式に示す様な発
振周波数となる。 Conventionally, a method as shown in FIG. 1a has been considered as one method for adjusting the frequency of a crystal oscillation circuit used in an electronic timepiece. In Figure 1a, 1
is a crystal oscillator serving as a time reference, 2 is a feedback resistor, 3 is a
is an oscillation inverter, 4 is a frequency dividing circuit, 5 is a switch element, 6 is a capacitor connected to the output end of the oscillation inverter 3, 7 is a capacitor connected to the input end of the oscillation inverter 3, 8 is for frequency adjustment It is a capacitor. Further, 9 is the input terminal of the oscillation inverter 3, and 10
is a signal that controls the on-off time of the switch element 5. Further, Vdd indicates the highest potential in this example, and Vss indicates the lowest potential. In this system, when the switch element 5 is turned off by the signal 10 that controls the switch element 5, the capacitance connected to the input terminal 9 of the oscillation inverter 3 is changed to the capacitor 7.
When the switch element 5 is on, the capacitance connected to the input terminal 9 of the oscillation inverter 3 is the sum of the capacitor 7 and the capacitor 8. Here, if the oscillation frequency in the capacitor 7 is 1 , and the oscillation frequency in the sum of the capacitors 7 and 8 is 2 , then 1 and
2 is always constant. In this state, when the on-off time of the signal 10 that controls the switch element 5 is changed, the ratio of the oscillation time in 1 and the oscillation time in 2 changes, resulting in oscillation as shown in the following equation. becomes the frequency.
０＝（ａ−τ）１＋τ２ ここで ０…周波数調整された周波数。 0 = (a - τ) 1 + τ 2 where 0 ... Frequency adjusted frequency.
τ…スイツチ素子５がオンになる時間。 τ...Time during which the switch element 5 is turned on.
ａ…τが発生する周期。 a...Period in which τ occurs.
この時τ＝０であれば０＝ａ１となり、τ
＝ａであれば０＝τ２となる。この時仮にａ
がａ＝１であれば、τ＝０で０＝１、τ＝ａ
で０＝２となる。これにより、τの時間を変
化する事により、０は１から２まで変化す
る。またτの時間を一定間隔に０からａまで変化
したとすると、上式より、周波数調整量は、一定
量ずつ変化するため、従来よりある容量―周波数
特性が曲線であるのに対して、τ―周波数特性で
は直線となるすぐれた点がある。 At this time, if τ = 0, 0 = a 1 , and τ
If = a, then 0 = τ 2 . At this time, if a
If a=1, then τ=0 and 0 = 1 , τ=a
So 0 = 2 . As a result, by changing the time of τ, 0 changes from 1 to 2 . Also, if the time of τ is changed from 0 to a at regular intervals, then from the above equation, the frequency adjustment amount changes by a constant amount, so while the conventional capacity-frequency characteristic is a curve, τ -There is an excellent point where the frequency characteristics are a straight line.
しかし従来技術では、スイツチ素子５がオフの
時、容量体８は放電状態となり電位を持つていな
い。また容量体７は発振に関与しているため、あ
る値の電位状態となつている。この状態でスイツ
チ素子５をオフ状態からオン状態にすると、容量
体８は充電される。しかしこの時容量体８を充電
するために、容量体７の電荷が容量体８に流れ込
む。このため入力端９の電位は、変動する。第１
図ｂはこの状態を示したものである。第１図ｂに
於いてVdd，Vssは前記したと同様の電位。信号
１０は第１図ａに於ける制御信号で、電位がVss
側の時、スイツチ素子５はオフ、Vdd側の時、ス
イツチ素子５はオンを意味する。また信号９１
は、入力端９に於ける発振波形を示したもので、
スイツチ素子５がオフとオンの時で振幅が異る。
これは容量によつて、容量が小さいと振幅が大き
くなり、容量が大きいと振幅が小さくなる傾向を
示すからである。また信号９０ａは、入力端９に
於けるバイアス電位を示している。第１図ｂから
も明らかな如く、スイツチ素子５をオフからオン
にすると、容量体８は充電されるわけであるが、
この時バイアス電位９０ａは変動する。この後、
このバイアス電位９０ａの変動によつて発振イン
バータ３の出力電圧は変化し、帰還抵抗２を介し
て、再び元の電位状態に復帰していく。この復帰
する時間は、帰還抵抗２と、容量体７及び８の和
の時定数に等しい。このバイアス電位９０上を発
振波形９１が乗るため、バイアス電位９０の変動
が大きいと、分周回路４は動作可能な状態まで分
周機能を停止し、ミスカウントを発生する。また
このバイアス電位９０の変動は、容量値によつて
も異つてくる。すなわち容量体８が容量体７より
大きいと変動は大きい。これは、Ｑ＝CVより電
圧Ｖを一定として考えると、電荷Ｑは容量Ｃに比
例するため、容量体７にある電荷量Q7では、容
量体８を十分充電する事ができないため、変動が
大きい。また容量体８が容量体７より小さいと変
動も小さい。しかしこの状態では容量体７と容量
体７及び８の和との差が小さいため、周波数調整
量も少ない。このためある程度の調整量が必要な
時、容量体７を小さく、容量体８を大きくしなけ
ればならず、結果変動も大きい。このため第１図
ｂに示す様なバイアス電位９０の変動が大きく発
生し、結果ミスカウントを生ずる。 However, in the prior art, when the switch element 5 is off, the capacitor 8 is in a discharged state and has no potential. Further, since the capacitor 7 is involved in oscillation, it is in a potential state of a certain value. When the switch element 5 is turned on from the off state in this state, the capacitor 8 is charged. However, at this time, in order to charge the capacitor 8, the charge of the capacitor 7 flows into the capacitor 8. Therefore, the potential at the input terminal 9 fluctuates. 1st
Figure b shows this state. In FIG. 1b, Vdd and Vss are the same potentials as described above. Signal 10 is the control signal in Figure 1a, and the potential is Vss.
When the voltage is on the Vdd side, the switch element 5 is off, and when the voltage is on the Vdd side, the switch element 5 is on. Also signal 91
shows the oscillation waveform at the input terminal 9,
The amplitude differs when the switch element 5 is off and on.
This is because, depending on the capacitance, if the capacitance is small, the amplitude tends to be large, and if the capacitance is large, the amplitude tends to be small. Further, a signal 90a indicates the bias potential at the input terminal 9. As is clear from FIG. 1b, when the switch element 5 is turned on from off, the capacitor 8 is charged.
At this time, the bias potential 90a varies. After this,
The output voltage of the oscillation inverter 3 changes due to this variation in the bias potential 90a, and returns to the original potential state via the feedback resistor 2. This recovery time is equal to the time constant of the sum of the feedback resistor 2 and the capacitors 7 and 8. Since the oscillation waveform 91 rides on this bias potential 90, if the bias potential 90 fluctuates greatly, the frequency divider circuit 4 stops its frequency division function until it can operate, causing a miscount. Further, this variation in bias potential 90 also differs depending on the capacitance value. That is, if the capacitor 8 is larger than the capacitor 7, the fluctuation will be large. This is because if we assume that the voltage V is constant from Q=CV, the charge Q is proportional to the capacitance C, so the amount of charge Q7 in the capacitor 7 cannot sufficiently charge the capacitor 8, so there is no fluctuation. big. Further, if the capacitor 8 is smaller than the capacitor 7, the fluctuation is also small. However, in this state, since the difference between capacitor 7 and the sum of capacitors 7 and 8 is small, the amount of frequency adjustment is also small. For this reason, when a certain amount of adjustment is required, the capacitor 7 must be made smaller and the capacitor 8 must be made larger, resulting in large fluctuations. For this reason, a large fluctuation in the bias potential 90 as shown in FIG. 1b occurs, resulting in miscount.
本発明は上記従来技術に於ける欠点を除去せん
とするものであり、前記周波数調整用の容量体に
あらかじめある値の電位を供給する事により、上
記バイアス電位変動を回避したもので、以下本発
明を詳細に説明する。 The present invention aims to eliminate the drawbacks of the prior art described above, and avoids the bias potential fluctuation by supplying a potential of a certain value to the frequency adjustment capacitor in advance. The invention will be explained in detail.
第２図ａは本発明に於ける一実施例回路図であ
る。第２図ａに於ける１１は時間基準となる水晶
振動子、１２は帰還抵抗、１３は発振インバー
タ、１４は分周回路、１５はスイツチ素子、１６
は本発明に於ける比較的高抵抗の抵抗体、１７は
発振インバータ１３の出力端に接続された容量
体、１８は発振インバータ１３の入力端に接続さ
れた容量体、１９は周波数調整用の容量体であ
る。また２０は発振インバータ１３の入力端、２
１はスイツチ素子１５を制御する信号を示す。更
にVddは前記したと同様に最高電位を示し、Vss
は最低電位を示している。またスイツチ素子１５
を制御する信号２１は、前記従来技術で述べた信
号１０と同様の動作を示す。この状態でスイツチ
素子１５がオフの時、容量体１９は抵抗体１６を
介して常にある値の電位に保持されている。この
ためスイツチ素子１５がオフからオンの時、従来
の様にバイアス電位が変動する事はない。この状
態を第２図ｂに示す。第２図ｂに於いて２００
は、発振インバータ１３の入力端２０のバイアス
電位を示したもので、信号２０１は入力端２０に
於ける発振波形を示したものである。このよう
に、抵抗体１６によつてバイアス電位２００の変
動は回避される。これにより、安定な発振状態を
可能とするため、分周回路１４のミスカウントは
回避される。また抵抗体１６は、スイツチ素子１
５がオンの時、帰還抵抗１２と並列接続されるた
め、この時の並列抵抗値を10MΩ以上に設計する
と効果がある。これは従来より、帰還抵抗値が
10MΩ以下で、発振インバータの増幅率が減少
し、かつ消電が増加する傾向を示すからである。
また抵抗体１６のかわりに、高抵抗のスイツチ素
子を使用し、スイツチ素子１５がオフの時、高抵
抗スイツチ素子をオンにして、容量体１９にある
値の電位を供給し、スイツチ素子１５がオンの
時、高抵抗スイツチ素子をオフにすれば、前記並
列抵抗値の問題はなくなり、かつ効果も同様に表
われる。第３図は高抵抗スイツチ素子を使用した
他の一実施例で、１１〜１５、１７〜２１及び２
００〜２０１は、第２図と同様であり、第３図ａ
の２２が第２図ａの抵抗体１６にかわる高抵抗ス
イツチ素子、２３が、制御信号２１を反転するイ
ンバータ、２４が該インバータ２３の反転出力を
意味する。この一実施例を使用すれば、前記並列
抵抗値の問題はなく、かつ同様な効果を示すた
め、きわめて効果的である。またこの他に、第２
図ａに於ける抵抗体１６あるいは、第３図ａに於
ける高抵抗スイツチ素子２２を、スイツチ素子１
５と並列に接続する方法もあり、これまた有効な
手段である。 FIG. 2a is a circuit diagram of an embodiment of the present invention. In FIG. 2a, 11 is a crystal oscillator serving as a time reference, 12 is a feedback resistor, 13 is an oscillation inverter, 14 is a frequency dividing circuit, 15 is a switch element, 16
17 is a capacitor connected to the output end of the oscillation inverter 13, 18 is a capacitor connected to the input end of the oscillation inverter 13, and 19 is a resistor for frequency adjustment. It is a capacitor. 20 is an input terminal of the oscillation inverter 13;
1 indicates a signal that controls the switch element 15. Furthermore, Vdd shows the highest potential as described above, and Vss
indicates the lowest potential. Also, switch element 15
The signal 21 controlling the signal 21 exhibits the same operation as the signal 10 described in the prior art. In this state, when the switch element 15 is off, the capacitor 19 is always held at a certain potential through the resistor 16. Therefore, when the switch element 15 is turned from off to on, the bias potential does not fluctuate as in the conventional case. This state is shown in FIG. 2b. In Figure 2b, 200
indicates the bias potential of the input terminal 20 of the oscillation inverter 13, and the signal 201 indicates the oscillation waveform at the input terminal 20. In this way, fluctuations in the bias potential 200 are avoided by the resistor 16. This enables a stable oscillation state, thereby avoiding miscounts in the frequency divider circuit 14. Further, the resistor 16 is connected to the switch element 1
5 is on, it is connected in parallel with the feedback resistor 12, so it is effective to design the parallel resistance value at this time to be 10 MΩ or more. This is because the feedback resistance value is
This is because when the resistance is 10 MΩ or less, the amplification factor of the oscillation inverter tends to decrease and power dissipation tends to increase.
In addition, a high-resistance switch element is used instead of the resistor 16, and when the switch element 15 is off, the high-resistance switch element is turned on and a certain value of potential is supplied to the capacitor 19, and the switch element 15 is turned on. If the high resistance switch element is turned off when it is on, the parallel resistance problem will disappear and the effect will be the same. Figure 3 shows another example using high resistance switch elements, 11-15, 17-21 and 2.
00 to 201 are the same as in Fig. 2, and Fig. 3 a
22 is a high resistance switch element replacing the resistor 16 in FIG. If this embodiment is used, there is no problem with the parallel resistance value, and the same effect is obtained, so it is extremely effective. In addition to this, the second
The resistor 16 in Figure a or the high resistance switch element 22 in Figure 3a is connected to the switch element 1.
There is also a method of connecting in parallel with 5, which is also an effective means.
この様に本発明は、高抵抗の抵抗体あるいは、
スイツチ素子によつて、周波数調整用の容量体に
あらかじめある値の電位を供給する事によつて、
従来の様なバイアス電位の変動はなくなり、安定
な発振動作を可能とするため効果は大きい。 In this way, the present invention provides a high-resistance resistor or
By supplying a certain value of potential to the frequency adjustment capacitor using a switch element,
This is highly effective because it eliminates the bias potential fluctuations that occur in the prior art and enables stable oscillation operation.
第１図ａ，ｂは従来の発振回路図及び波形図、
第２図ａ，ｂは本発明の実施例を示す発振回路図
及び波形図、第３図ａ，ｂは第２図ａ，ｂの他の
実施例を示す発振回路図及び波形図である。
１３…発振インバータ、１５…スイツチ素子、
１６…高抵抗体、２２…高抵抗スイツチ素子、２
３…インバータ。
Figures 1a and 1b are conventional oscillation circuit diagrams and waveform diagrams,
2a and 2b are oscillation circuit diagrams and waveform diagrams showing an embodiment of the present invention, and FIGS. 3a and 3b are oscillation circuit diagrams and waveform diagrams showing another embodiment of FIGS. 2a and 2b. 13...Oscillation inverter, 15...Switch element,
16...High resistance element, 22...High resistance switch element, 2
3...Inverter.
Claims (1)
に、スイツチ素子の入力端を接続し、該スイツチ
素子の出力端に周波数調整用の容量体を接続し、
前記スイツチ素子のオン―オフ時間を変化する事
によつて、周波数を時分割的に調整する水晶発振
回路に於いて、前記スイツチ素子と前記周波数調
整用の容量体との接続点と、前記発振インバータ
の出力端との間に、比較的高抵抗の抵抗体あるい
は比較的高抵抗のスイツチ素子を接続した事を特
徴とする水晶発振回路。1 Connect the input end of the switch element to the input end of the oscillation inverter in the oscillation circuit, connect the capacitor for frequency adjustment to the output end of the switch element,
In a crystal oscillation circuit that adjusts the frequency in a time division manner by changing the on-off time of the switch element, the connection point between the switch element and the frequency adjustment capacitor and the oscillation A crystal oscillation circuit characterized in that a relatively high resistance resistor or a relatively high resistance switch element is connected between the output terminal of an inverter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4182379A JPS55134505A (en) | 1979-04-06 | 1979-04-06 | Crystal oscillating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4182379A JPS55134505A (en) | 1979-04-06 | 1979-04-06 | Crystal oscillating circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55134505A JPS55134505A (en) | 1980-10-20 |
| JPS6148282B2 true JPS6148282B2 (en) | 1986-10-23 |
Family
ID=12619001
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4182379A Granted JPS55134505A (en) | 1979-04-06 | 1979-04-06 | Crystal oscillating circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS55134505A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA2038967C (en) * | 1990-03-27 | 1996-03-05 | Motoyoshi Komoda | Crystal oscillator for use in timepiece of battery-powered portable apparatus |
-
1979
- 1979-04-06 JP JP4182379A patent/JPS55134505A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS55134505A (en) | 1980-10-20 |
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