JPS6147659A - Lsi multichip mounting structure - Google Patents
Lsi multichip mounting structureInfo
- Publication number
- JPS6147659A JPS6147659A JP59169352A JP16935284A JPS6147659A JP S6147659 A JPS6147659 A JP S6147659A JP 59169352 A JP59169352 A JP 59169352A JP 16935284 A JP16935284 A JP 16935284A JP S6147659 A JPS6147659 A JP S6147659A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- board
- multilayer wiring
- wiring board
- housing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/162—Disposition
- H01L2924/1627—Disposition stacked type assemblies, e.g. stacked multi-cavities
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は超大型コンピュータ本体の主要部を形成する論
理、記憶装置の高出力ＬＳＩマルチチップ実装構造に関
する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a high-output LSI multi-chip mounting structure for logic and storage devices forming the main part of a super-large computer main body.
近年、電子計算機は大容量化、高速化、小型化が要請さ
れ、その主要部を構成するＬＳＩは微細加工技術の改良
により一層高密度化が図られている。このため必然的に
チップｉｂの消費電力換言すれば、単位面積当りの発熱
量が急速に増している。そこでＬＳＩのマルチチップ実
装に際しては。In recent years, electronic computers have been required to have larger capacities, faster speeds, and smaller sizes, and the LSIs that constitute the main components thereof are becoming more dense due to improvements in microfabrication technology. For this reason, the power consumption of the chip ib, in other words, the amount of heat generated per unit area is inevitably increasing rapidly. Therefore, when implementing multi-chip LSI.
水冷方式が必須条件になシつつある。Water cooling is becoming an essential requirement.
第１図はＡｌｔｏｎ多層板１にＳｉチップ２をＣＣＢ
（Ｃｏｎｔｒｏｌｌｅｄ Ｃｏ１１ａｐｓｅ Ｂｏｎｄ
ｉｎｇ ）法で多数個接続したマルチチップモジュール
構造を示している。Ｓｉチップ２の裏面と冷却水通路６
をもつハウジング３とをはんだ４で接着し、水冷する方
式でおる（ Ｕ、５．ｐａｔｅｎｔ ４０８１８２５
、３゜２８．１９７８）。封止方式は金属ガスケット７
による機械的な圧着である。このマルチチップモジュー
ルの入出力ピン８は多層プリント板（図示せず）に接続
するため下側に取出す構造になっている。しかし、この
構造、基板材料ではよυ大容量、高速化を目的とした場
合のコンピュータの実装構造としては次のような問題が
ある。Figure 1 shows a CCB with a Si chip 2 mounted on an Alton multilayer board 1.
(Controlled Co11apse Bond
This figure shows a multi-chip module structure in which a large number of chips are connected using the ing method. Back side of Si chip 2 and cooling water passage 6
The housing 3 with the housing 3 is bonded with solder 4 and cooled with water (U, 5. patent 4081825
, 3°28.1978). Sealing method is metal gasket 7
This is mechanical crimping. The input/output pins 8 of this multichip module are designed to be taken out on the bottom side for connection to a multilayer printed board (not shown). However, this structure and board material have the following problems when it comes to mounting a computer for purposes of high capacity and high speed.
即ち、第１の問題点は、入出力ピン８をＡｌｔｏｓ多層
板１の裏面の主要部分から引き出して、多層プリント基
板のスルーホールにピン付、もしくはコネクタ接続され
る構造になっている。このため、この構造のマルチチッ
プモジュールを多段に重ねて組合せる構造とした場合、
ピンが邪魔になシ、実装できないという欠点がある第２
の問題点は、最も基本的であるが、Ａ７ｚＯａ多層板（
Ｗペースト、もしくはＭＯペースト導体使用）は誘電率
が高く（６キ９．３）、高速計算に不利であることであ
る。従って、大容量で小型構造の高速電算機用のＬＳＩ
実装構造としては不十分である。That is, the first problem is that the input/output pins 8 are pulled out from the main part of the back surface of the Altos multilayer board 1 and connected to through holes in the multilayer printed circuit board with pins or connectors. Therefore, when multi-chip modules with this structure are stacked and combined in multiple stages,
The second problem is that the pins get in the way and cannot be mounted.
The problem with A7zOa multilayer board (
W paste or MO paste conductor) has a high dielectric constant (6 x 9.3), which is disadvantageous for high-speed calculation. Therefore, LSIs for high-speed computers with large capacity and small structure
This is insufficient as a mounting structure.
本発明の目的屹上述の問題点を解決したＬＳＩマルチチ
ップ実装構造を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide an LSI multi-chip mounting structure that solves the above-mentioned problems.
本発明の特徴は、入出力ピンを多層板の周辺部のＬＳＩ
チップを載置する側に設ける点にある。The feature of the present invention is that the input/output pins are connected to the LSI on the periphery of the multilayer board.
The reason is that it is provided on the side where the chip is placed.
これによシ、各段のマルチチップモジュールを重ね合わ
すことが可能になシ、小型で立方体実装構造とすること
ができる。そして好ましい実施例では多層板を、低誘電
率の有機多層基板（例えば、ポリイミド、イソメラミン
系樹脂等）とＣｕ導体の組合せとすることによシ誘電率
（ε）を３．５まで下げることが可能となるため、高速
計算が期待できる。This allows the multi-chip modules of each stage to be stacked on top of each other, resulting in a compact cubic mounting structure. In a preferred embodiment, the dielectric constant (ε) can be lowered to 3.5 by making the multilayer board a combination of a low dielectric constant organic multilayer substrate (for example, polyimide, isomelamine resin, etc.) and a Cu conductor. Therefore, high-speed calculation can be expected.
この有機多層配線基板に１０ｗ０の高出力チップを７エ
ースダクン法で実装する上での問題点は、■有機多層板
の熱伝導率が著しく低いこと（Ａ４０ｇ 多層板に比べ
１１５０）である。このため、全面はんだバンプからの
熱伝導によシ、発熱量の１０〜２０チの熱が有機多層配
線基板側から放散される。この結果、有機多層配線基板
の温度上昇をもたらすため、基板の反シなどによシもた
らされるはんだバンプにかかる応力のため寿命低下の新
たな問題がでてくる。また、冷却効果を上げるためにも
基板側の冷却も必要である。The problem in mounting a 10W0 high output chip on this organic multilayer wiring board using the 7AceDakun method is that (1) the thermal conductivity of the organic multilayer board is extremely low (1150 compared to an A40g multilayer board). Therefore, 10 to 20 inches of heat is dissipated from the organic multilayer wiring board side due to heat conduction from the solder bumps all over the surface. As a result, the temperature of the organic multilayer wiring board increases, and a new problem arises in that the life of the solder bump is shortened due to the stress exerted on the solder bumps caused by the deformation of the board. Furthermore, cooling on the substrate side is also necessary to increase the cooling effect.
■ 有機多層基板は複合化（α＝０．７ Ｘ １０’−
’／Ｃのアラミドクロスファイバ入シ）シても、Ｃｕ導
体（α＝１７．５Ｘ１０−’／Ｃ）を用いるため、基板
の熱膨張係数が下がらず、１０ｍ”チップのはんだバン
プ寿命がコンピュータに要求されている寿免を満たすこ
とはできないこと。■ Organic multilayer substrates are composite (α = 0.7 x 10'-
Even if an aramid cross fiber of '/C is inserted, the thermal expansion coefficient of the board does not decrease because a Cu conductor (α = 17.5 It is impossible to meet the required longevity exemption.
■ 有機多層配線基板は吸湿性があるため、この基板だ
けでハウジング内部と外部を接することはできない。■ Because the organic multilayer wiring board is hygroscopic, it is not possible to connect the inside and outside of the housing with this board alone.
有機多層板を使用することによシ生ずる上記■■、■の
問題点を解決するためは、以下ａ）、（２）。In order to solve the above-mentioned problems (■) and (2) caused by using an organic multilayer board, the following steps a) and (2) are carried out.
（３）を施せばよい。Just apply (3).
（１）有機多層配線板よシも十分厚く、伸び剛性が犬で
、かつ熱伝導性に優れた３ｉＣ（特願５５−７５６０１
、熱伝導率０．７１Ｃａｔ／ｃｒｎ、 ｓ 、 Ｃｒ熱
膨張係数３．９ Ｘ １ｏ−’／Ｃ）板を有機多層配線
板の裏面に張り合わせた複合配線基板とする。（２）、
入出力端子は有機多層配線板の対向する２つの周囲の表
面層に出す。（３）冷却チップの素子側（全面バング−
有機配線板−８ｉＣ板）のＳｉＣ板長面と、３ｉチツプ
の裏面側に低融点はんだで接着したＳｉＣ板、との両側
で水冷する構造とする。(1) 3iC (patent application No. 55-75601
, a thermal conductivity of 0.71 Cat/crn, s, and a Cr thermal expansion coefficient of 3.9 X 1o-'/C) plate is laminated on the back surface of an organic multilayer wiring board to provide a composite wiring board. (2),
The input/output terminals are exposed to two opposing peripheral surface layers of the organic multilayer wiring board. (3) Element side of cooling chip (full-face bang)
The long side of the SiC board of the organic wiring board (8iC board) and the SiC board bonded to the back side of the 3i chip with low melting point solder are water-cooled on both sides.
これによシ有機多層配線板を用いても基板の反シ及び大
型チップのはんだバンプの信頼性低下等の問題を克服し
、有機多層配線基板の特徴を生かした大容量で高速計算
を可能にする高出力ＬＳＩマルチチップモジュール実装
を提供である。As a result, even when using an organic multilayer wiring board, problems such as board distortion and decreased reliability of solder bumps on large chips can be overcome, and high-capacity and high-speed calculations that take advantage of the characteristics of organic multilayer wiring boards are possible. We provide high-power LSI multi-chip module packaging.
第１図は、ε＝３．５の有機多層配線板９（例えばイソ
メラミン樹脂とアラミドクロスファイバ混入）に８ｉＣ
板］１を張合わせた複合基板上に、１０■０Ｓｉチツプ
２を搭載した断面図である。Figure 1 shows an organic multilayer wiring board 9 with ε=3.5 (e.g., isomelamine resin and aramid cross fiber mixed) with 8iC
1 is a cross-sectional view of a 100Si chip 2 mounted on a composite substrate laminated with a 100Si chip 2.
有機多層配線板は２０層で、スルーホール１２に接続さ
れたＣｕリード１３で連結されている。The organic multilayer wiring board has 20 layers connected by Cu leads 13 connected to through holes 12.
Ｓｉチップ２上のはんだパンダ７の接続端子チップは２
５０μｍで、はんだバンプ１６の径は１゛３０μｍφ、
有機多層配線板上のペデスタル１４の径ｔｉ１４０μｍ
φでおる。この複合基板は約１２０ＩｎＩ０で、チップ
温度が８００に達しても反シは無視できる程度に小さい
。複合基板は５〜６Ｘ１０’−’／Ｃで、ＳａＣ板１１
の熱膨張係数は３．９Ｘ１０−’／ｌ：ｌ’と両者は接
近している。The connection terminal chip of the solder panda 7 on the Si chip 2 is 2
50 μm, the diameter of the solder bump 16 is 1゛30 μmφ,
Diameter ti of pedestal 14 on organic multilayer wiring board 140 μm
It's φ. This composite substrate has approximately 120InI0, and even if the chip temperature reaches 800℃, the resistance is so small that it can be ignored. The composite substrate is 5~6X10'-'/C, SaC board 11
The coefficient of thermal expansion is 3.9X10-'/l:l', which is close to each other.
ＳｉＣ板１１の厚さは３■で十分である。複合基板の反
シの程度は、基板の熱膨張係数１寸法、両板の厚さの比
、温度差などで変る。また、ＳｔＣ。A thickness of 3 mm is sufficient for the SiC plate 11. The degree of warping of a composite substrate varies depending on the thermal expansion coefficient of the substrate, the ratio of the thicknesses of the two plates, the temperature difference, etc. Also, StC.
板と有機多層配線板とを接着した樹脂１０は塑性変形に
優れているため、最も応力のかかる基板周辺部において
もＳｉＣ板を破壊させることはない。Since the resin 10 used to bond the board and the organic multilayer wiring board has excellent plastic deformation, the SiC board will not be destroyed even at the periphery of the board, where the most stress is applied.
以下接続を中心とするプロセスについて示す。複合基板
上のＣｕペデスタル４（１２μｍ厚）上に、８１チツプ
の端子を位置決めして、２４０ｔ：’でボンディングし
た。はんだ組成はｐｂ−６０チＳｎである。ペデスタル
部以外ははんだ流出防止用のレジスト１５が形成されて
いる。このはんだバンプ７の接続と同時に複合基板と・
・ウジフグ側壁部の片面をｐｂ−６０’１８ｎで接合す
る。なお、ペデスタル端子はスルーホールを避けて、隣
接部に設けた。The following describes the process centered on connections. Terminals of 81 chips were positioned on the Cu pedestal 4 (12 μm thick) on the composite substrate and bonded at 240t:'. The solder composition is PB-60Sn. A resist 15 for preventing solder from flowing out is formed in areas other than the pedestal portion. At the same time as this solder bump 7 is connected, the composite board and
・Join one side of the Ujifugu side wall with pb-60'18n. Note that the pedestal terminal was placed adjacent to the through hole, avoiding the through hole.
第２図は水冷ヒートシンク２０へのＳｉテップ２の裏面
の接着部１９、封止部２２の接着部の断面図である。冷
却水路は対向する２辺の１つの側に設けである。対向す
る２辺の他の１つの周囲には封止部の外側において入出
力端子２７のピン接合部を設けである。第３図は第２図
と異なる側のハウジング側壁部の入出力端子のおる側の
断面を示す。ピンをＳｉチップを載置した側に設けた理
由はモジュールの両面を冷却し、多段構造にして小型化
するために障害とならないためである。プリント板上の
ＳｉＣ板２板端６端
４用するのは熱放散性を目的とするだけではなく、多層
板が直接外気に接しない防湿構造とすることを目的とし
ている、従って、ＳｉＣ板２板金４Ｃｒ−Ｃｕメタライ
ズ）の接続は、はんだバンプ接続、ハウジング側壁部の
多層配線板への接続と同時にＰｂ−６０チＳｎで取付け
られる。FIG. 2 is a sectional view of the adhesive portion 19 on the back surface of the Si tip 2 and the adhesive portion of the sealing portion 22 to the water-cooled heat sink 20. The cooling water channel is provided on one of the two opposing sides. A pin joint portion for the input/output terminal 27 is provided on the outside of the sealing portion around the other two opposing sides. FIG. 3 shows a cross section of the side wall of the housing, which is different from that in FIG. 2, on the side where the input/output terminals are located. The reason why the pins are provided on the side on which the Si chip is mounted is to cool both sides of the module so that it does not become an obstacle to miniaturization by forming a multi-stage structure. The use of the SiC board 2 on the printed board is not only for the purpose of heat dissipation, but also for the purpose of creating a moisture-proof structure where the multilayer board does not come into direct contact with the outside air. The connection of the sheet metal (4Cr-Cu metallized) is made by solder bump connection and the connection to the multilayer wiring board of the side wall of the housing, and is simultaneously attached with Pb-60chiSn.
入出力ピン２７は、あらかじめＳｉＣ板２６にスルーホ
ール導体３２、ランド部２８を設け、５ｎ−１８１Ｂｉ
−４５％Ｐｂはんだを用いＳｉＣ板２６にはんだ付され
る。ノ・ウジング内部のチップの端子はスルーホール導
体４１及び内部の配線４ｏを通して接続され、外部の人
出ピン２７′に接続される。入出力ピンはコネクターを
介して、上下各段のモジュールに接続される。このよう
にハウジング側壁部の空間を利用してピンを上向きに取
出すことよシ、小型で多段のマルチチップモジュール構
造を可能とした。第４図はモジュールを平面的に切断し
た断面である。入出力ピンは上下に、冷却水路は左右に
取付けた構造である。The input/output pin 27 is made by providing a through-hole conductor 32 and a land portion 28 on the SiC board 26 in advance, and using a 5n-181Bi
It is soldered to the SiC board 26 using -45% Pb solder. The terminals of the chip inside the housing are connected through the through-hole conductor 41 and the internal wiring 4o, and are connected to the external lead pin 27'. The input/output pins are connected to the upper and lower modules via connectors. In this way, by utilizing the space in the side wall of the housing to take out the pins upward, a compact and multi-stage multi-chip module structure has become possible. FIG. 4 is a cross section of the module cut in a plane. The input/output pins are installed on the top and bottom, and the cooling channels are installed on the left and right sides.
Ｓｉチップ近くのはんだ接続は、まず、Ｐｄ−６０チＳ
ｎのはんだバンプを接続後、あらかじめＳｉチップ裏面
にＣｒ （：：ｕ Ａｕ１８をメタライズされた層
の上に、約５００μｍ厚さの低融点はんだ８ｎ−１８＊
Ｂ１−４５＊Ｐｂ （特願昭５ ８−０１１２９３，同
相温度１３６Ｇ，液相温度１６８ｒ）箔を載せて溶融さ
せて接続した。また、同時に・・ウジング側壁部の最終
村上部にも、メタライズしたＳｉＣ板２板側２側壁材２
００μｍ厚さのはんだ箔を載せて接合した。低温はんだ
の接合条件はｍａｘ１７８Ｇである。接合時の雰囲気は
Ｈ２ 、 Ｈ ｅ ｒ Ｎ＊ ＋ Ａ ｒ等のいずれで
も可能である。For solder connections near the Si chip, first use Pd-60 chip S.
After connecting the n solder bumps, a low melting point solder 8n-18* with a thickness of about 500 μm is applied on the Cr(::u) Au18 metalized layer on the back side of the Si chip.
B1-45*Pb (Japanese Patent Application No. 58-011293, in-phase temperature 136G, liquidus temperature 168R) was placed on a foil and melted to connect. At the same time, 2 metalized SiC plates 2 plate side 2 side wall material 2
00 μm thick solder foil was placed and bonded. The low temperature solder bonding conditions are max 178G. The atmosphere during bonding may be H2, HerN*+Ar, or the like.
第５図はマルチチップモジュールの２段重ね構造を示す
。（ａ）は冷却水路を境に対称的に重ねる方式、（ｂ）
は同一方向に重ねる方式等を示したモデル図でおる。（
ａ） 構造では温度上昇が著しい水路と温度上昇の少
ない水路が交互にくるので、流量を調節する必要がちる
。（ｂ） 構造では各段とも同一温度上昇になる。FIG. 5 shows a two-tier stacked structure of multi-chip modules. (a) is a symmetrical stacking method with cooling channels as a boundary; (b)
is a model diagram showing a method of overlapping in the same direction, etc. (
a) In the structure, waterways with a significant temperature rise alternate with waterways with a small temperature rise, so it is often necessary to adjust the flow rate. (b) In the structure, the temperature rise is the same in each stage.
（ａ）、（ｂ）構造にはそれぞれ一長一短がある。Ｓｉ
Ｃのヒートシンク２０とヒートシンク２０の中間に設け
られている冷却水路には、流れに対して平行に、しかも
何列にも配置されているチップ列に沿ってＳｉＣフィン
３１が細かく、かつ長く設けられていて、流れやすく、
熱放散性を良くしである。Structures (a) and (b) each have advantages and disadvantages. Si
In the cooling channel provided between the heat sinks 20 of C, fine and long SiC fins 31 are provided parallel to the flow and along the chip rows arranged in many rows. Easy to flow,
This improves heat dissipation.
２９は冷却水入口、３８は冷却水出口で、３０は冷却水
の取付部である。第５図（Ｃ）は第５図（ａ）、 （ｂ
）において、ＡＢ断面で切断した場合の１段目と２段目
のマルチチップモジュールの冷却水路断面を示す。水路
はＳｉＣの板１１．２０で狭まれている。29 is a cooling water inlet, 38 is a cooling water outlet, and 30 is a cooling water attachment part. Figure 5(C) shows Figures 5(a) and (b).
) shows the cooling water cross section of the first and second stage multi-chip modules when cut along the AB cross section. The water channel is narrowed by a SiC plate 11.20.
第６図はチップの温度上昇が高い場合に、冷却層を多段
にした実施例である。第６図（ａ）は第５図（ａ）と同
じく対称構造を示し、温度上昇の著しいチップ裏面にお
いて、冷却効果を上げるため３層の冷却層を設け、はん
だバンプ側の冷却においては１層の冷却層を設けた断面
のモデルを示す。３層の中間層は両側の層と逆の流れに
することによシ各チップの温度上昇を均一化することが
できる。FIG. 6 shows an embodiment in which cooling layers are provided in multiple stages when the temperature rise of the chip is high. Figure 6(a) shows the same symmetrical structure as Figure 5(a), with three cooling layers provided on the back side of the chip where the temperature rises significantly to increase the cooling effect, and one layer for cooling the solder bump side. A cross-sectional model with a cooling layer is shown. By making the three intermediate layers flow in the opposite direction to the layers on both sides, it is possible to equalize the temperature rise of each chip.
第６図（ｂ）は同一方向チップ配置構造を示す。この構
造では各段共、水路方向を逆にした２層の冷却層を設け
た。FIG. 6(b) shows a structure in which chips are arranged in the same direction. In this structure, two cooling layers were provided in each stage with the direction of the waterways reversed.
前述の第１〜６図は、多層配線板と・・ウジング天井材
をＳｉチップを介して、はんだで接着する構造を示した
が、熱伝導性の優れた有機接着剤の使用も可能である。The above-mentioned Figures 1 to 6 show a structure in which the multilayer wiring board and the ceiling material are bonded by solder via a Si chip, but it is also possible to use an organic adhesive with excellent thermal conductivity. .
この接着構造は、・・ウジング上下の基板同志の熱膨張
係数がほぼ等しいことから、若干の熱膨張係数の差によ
り生じた接続部、封止部の応力、歪を融点に階層を設け
た伸び、絞シに優れた低融点はんだで緩和することを基
本にしたものである。This bonding structure...Since the coefficients of thermal expansion of the substrates on the upper and lower sides of the housing are almost the same, the stress and strain at the connection and sealing parts caused by slight differences in the coefficients of thermal expansion are caused by a layered elongation at the melting point. This is based on the use of low melting point solder, which has excellent shrinkage resistance.
しかし大型基板になると、寸法効果のため、歪量が大き
くなシ問題になってくることが予想される。However, when it comes to large substrates, it is expected that the amount of distortion will become a problem due to size effects.
この場合は、例えば第７図に示すよづにベローズ３７構
造（空気だめ３５付水銀３４人シ）にすれば、上下だけ
でなく、水平方向の変位に対しても解放できる。また、
ベローズの中にフィン３１を設けた水冷構造にすれば、
大型基板に対しても冷却効果を損なわず、本方式の構造
は有効である。In this case, for example, if the bellows 37 structure shown in FIG. 7 (mercury 34 cylinder with air reservoir 35) is used, it can be released not only against vertical displacement but also against horizontal displacement. Also,
If you use a water cooling structure with fins 31 inside the bellows,
The structure of this method is effective even for large substrates without impairing the cooling effect.
なお、封止部、チップ接合に融点の異なるはんだを用い
たのは、故障チップを修理するときに融点の高いはんだ
を溶かさないで、外し、再取付けするリペプ性を考慮し
ているためである。また、応力、歪緩和に対しても、低
融点はんだの使用の効果は大きい。The reason why we used solders with different melting points for the sealing part and chip joints was to take into consideration the repeatability of removing and reattaching a defective chip without melting the solder with a higher melting point. . Furthermore, the use of low melting point solder has a great effect on stress and strain relaxation.
なお、複合多層配線基板に使用しているＳｉＣ板、ハウ
ジング天井に使用しているＳｉＣ板等の代りに熱伝導性
に優れ、かつ熱膨張係数を８ｉ並みに合わすことができ
る銅・カーボン複合材を用いることも可能である。In addition, instead of the SiC board used in the composite multilayer wiring board and the SiC board used in the ceiling of the housing, a copper/carbon composite material with excellent thermal conductivity and a coefficient of thermal expansion that can be matched to 8i is used. It is also possible to use
多段モジュールの冷却構造として、各モジュールごとに
独立して両側に冷却層を設けてから、重ねて多段化する
方式は、取外し再取付けに優れている長所があるので当
然考えられる実装構造である。As a cooling structure for a multi-stage module, a method in which cooling layers are independently provided on both sides of each module and then stacked to form multiple stages is a natural mounting structure that can be considered because it has the advantage of being easy to remove and reinstall.
本発明によシ、計算゛速度の大幅な向上が期待できる有
機多層板上への、１０１ｏ１０の大型高出力チップ（２
ｏ−：４０Ｗ）の高密度実装を可能にしたことによシ、
従来にない小型構造で大容量・高速の超大型計算機が可
能になる。According to the present invention, a large high-power chip (101x10) (2
o-:40W), which enables high-density mounting.
This makes it possible to create ultra-large computers with large capacity and high speed with an unprecedentedly compact structure.
第１図は本発明に用いる多層配線基板の断面図、第２図
は本発明を適用したモジュールのハウジング部の断面図
、第３図は本発明モジュールの封止部及び入出力端子部
の拡大図、第４図は本発明モジュールの平面図、第５図
はマルチチップモジュールを２段に重ねた本発明の他の
実施例を示す断面図、第６図は冷却層を２〜３層にした
場合の実施例を示す断面図、第７図はベローズを用いた
冷却構造のチップ周辺の断面図、第８図は従来のマルチ
チップモジュールの断面図である。
２・・・Ｓｉチップ、９・・・有機多層配線板、１１・
・・ＳｉＣ板。Fig. 1 is a cross-sectional view of a multilayer wiring board used in the present invention, Fig. 2 is a cross-sectional view of the housing portion of a module to which the present invention is applied, and Fig. 3 is an enlarged view of the sealed portion and input/output terminal portion of the module of the present invention. 4 is a plan view of the module of the present invention, FIG. 5 is a sectional view showing another embodiment of the present invention in which multi-chip modules are stacked in two layers, and FIG. 6 is a cooling layer of 2 to 3 layers. FIG. 7 is a cross-sectional view of the periphery of a chip having a cooling structure using bellows, and FIG. 8 is a cross-sectional view of a conventional multi-chip module. 2...Si chip, 9...Organic multilayer wiring board, 11.
...SiC board.
Claims (1)
れてなる多数個の半導体チップを多層配線基板上にはん
だ接合したマルチチップモジュールにおいて、 多層配線基板上のチップが搭載された側とは反対側の面
及びチップを接着したハウジングの裏側面が液冷される
ように、多層配線基板、ヒートシンクを多段積層したこ
とを特徴とするＬＳＩマルチチップ実装構造。 ２、特許請求の範囲第１項において、多層配線基板は有
機多層配線板とＳｉＣ板とを接着した複合基板であるこ
とを特徴とするＬＳＩマルチチップ実装構造。 ３、特許請求の範囲第１項または第２項において、ハウ
ジングはＳｉＣであることを特徴とするＬＳＩマルチチ
ップ実装構造。 ４、特許請求の範囲第１項、第２項または第３項におい
て、入出力ピンはハウジング外部の多層配線基板の半導
体チップ側から取出したことを特徴とするＬＳＩマルチ
チップ実装構造。[Scope of Claims] 1. A multi-chip module in which a number of semiconductor chips each having a solder electrode terminal and having a number of element regions formed therein are soldered onto a multilayer wiring board, comprising: a chip on the multilayer wiring board; An LSI multi-chip mounting structure characterized by stacking multilayer wiring boards and heat sinks in multiple stages so that the side opposite to the side on which the chip is mounted and the back side of the housing to which the chip is bonded are liquid-cooled. 2. The LSI multi-chip mounting structure according to claim 1, wherein the multilayer wiring board is a composite board made by bonding an organic multilayer wiring board and a SiC board. 3. The LSI multi-chip mounting structure according to claim 1 or 2, wherein the housing is made of SiC. 4. The LSI multi-chip mounting structure according to claim 1, 2 or 3, characterized in that the input/output pins are taken out from the semiconductor chip side of the multilayer wiring board outside the housing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59169352A JPS6147659A (en) | 1984-08-15 | 1984-08-15 | Lsi multichip mounting structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59169352A JPS6147659A (en) | 1984-08-15 | 1984-08-15 | Lsi multichip mounting structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6147659A true JPS6147659A (en) | 1986-03-08 |
Family
ID=15884973
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59169352A Pending JPS6147659A (en) | 1984-08-15 | 1984-08-15 | Lsi multichip mounting structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6147659A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5315486A (en) * | 1991-12-16 | 1994-05-24 | General Electric Company | Hermetically packaged HDI electronic system |
| JP2007012719A (en) * | 2005-06-28 | 2007-01-18 | Honda Motor Co Ltd | Cooler and manufacturing method thereof |
-
1984
- 1984-08-15 JP JP59169352A patent/JPS6147659A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5315486A (en) * | 1991-12-16 | 1994-05-24 | General Electric Company | Hermetically packaged HDI electronic system |
| JP2007012719A (en) * | 2005-06-28 | 2007-01-18 | Honda Motor Co Ltd | Cooler and manufacturing method thereof |
| JP4721412B2 (en) * | 2005-06-28 | 2011-07-13 | 本田技研工業株式会社 | Cooler and manufacturing method thereof |
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