JPS6147658A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6147658A JPS6147658A JP16980884A JP16980884A JPS6147658A JP S6147658 A JPS6147658 A JP S6147658A JP 16980884 A JP16980884 A JP 16980884A JP 16980884 A JP16980884 A JP 16980884A JP S6147658 A JPS6147658 A JP S6147658A
- Authority
- JP
- Japan
- Prior art keywords
- tie
- rail
- bar
- tie bar
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 238000004519 manufacturing process Methods 0.000 title claims description 3
- 229920005989 resin Polymers 0.000 claims abstract description 27
- 239000011347 resin Substances 0.000 claims abstract description 27
- 239000000463 material Substances 0.000 claims abstract description 18
- 239000008188 pellet Substances 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 8
- 238000000465 moulding Methods 0.000 claims description 4
- 238000005452 bending Methods 0.000 claims 1
- 238000009413 insulation Methods 0.000 abstract description 2
- 238000007665 sagging Methods 0.000 abstract 2
- 230000006866 deterioration Effects 0.000 abstract 1
- 238000010008 shearing Methods 0.000 abstract 1
- 239000012634 fragment Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 239000004519 grease Substances 0.000 description 2
- 239000010445 mica Substances 0.000 description 2
- 229910052618 mica group Inorganic materials 0.000 description 2
- 229920001296 polysiloxane Polymers 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4842—Mechanical treatment, e.g. punching, cutting, deforming, cold welding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
主粟上皮机里光立
本発明は、電子機器等の被取付体にペレットマウント部
としての放熱板を絶縁して取付けるため放熱板の裏面ま
で外装樹脂材を被覆した完全樹脂封止型半導体装置のよ
うに樹脂封止成形後、外装樹脂材からリードフレームの
タイバー部が突出している半導体装置の該タイバー部を
樹脂封止成形後に切断する方法に関するものである。[Detailed Description of the Invention] The present invention covers the back side of the heat sink with an exterior resin material in order to insulate and attach the heat sink as a pellet mount to an object to be attached such as an electronic device. The present invention relates to a method of cutting the tie bar portion of a lead frame of a semiconductor device, such as a completely resin molded semiconductor device, in which the tie bar portion of a lead frame protrudes from an exterior resin material after resin molding.
止糸p且血
樹脂封止型半導体装置は一般にペレットマウント部とし
ての放熱板の非ペレット固着側裏面を露出させて樹脂外
装している。そして、その放熱板の裏面を、シャーシベ
ースや放熱器等の外部取付機器の平坦な面に密着させて
アースした状態で実装しているが、近年は例えば、コレ
クタ絶縁タイプのトランジスタのように、放熱板の裏面
を・外部取付機器に絶縁し、かつ熱的には接続させて取
付ける絶縁タイプのものが普及しつつある。この絶縁タ
イプの樹脂封止型半導体装置の実装は、従来のものが、
放熱板の露出した裏面にシリコングリスを塗着゛した薄
いマイカ板を敷設したり等して放熱板を外部取付機器か
ら絶縁していた技術に代わるものである。つまり、この
従来品の実装はマイカ板を敷設したりシリコングリスを
塗布する作業が難しい等の問題があるため、この問題を
解決したものとして、放熱板を裏面も含めて全面的に樹
脂封止したものが提案され実用化されている。A resin-sealed semiconductor device is generally packaged with a resin with the back surface of a heat sink serving as a pellet mount part on the non-pellet fixed side exposed. Then, the back side of the heat sink is mounted with the back side of the externally mounted equipment such as the chassis base or heat sink in close contact with the flat surface of the externally mounted device and grounded. Insulated type devices are becoming popular, where the back side of the heat sink is insulated from external equipment and connected thermally. The conventional method for mounting this insulating type resin-sealed semiconductor device is
This is an alternative to the technique of insulating the heat sink from external equipment by, for example, laying a thin mica plate coated with silicone grease on the exposed back side of the heat sink. In other words, the mounting of this conventional product has problems such as the difficulty of laying the mica board and applying silicone grease, so as a solution to this problem, the heat sink is completely sealed with resin, including the back side. have been proposed and put into practical use.
この完全樹脂封止型半導体装置の構造例を第4図及び第
5図に示すと、(1)はペレットマウント部としての放
熱板、(2)(2)−は放熱板(1)から外方に延びる
例えば3本のリードで、中央の1本の先端は放熱板(1
)と一体化され、両側の2本の先端は放熱板(1)の近
傍に位置する。(3)’は放熱板(1)上にマウントさ
れた半導体ペレット、(4)(4)は半導体ペレット(
3)の表面電極とリード(2)(2)の先端部とを電気
的に接続する金属細線、(5)は放熱板(1)とリード
先端部を含む要部を封止して成形されたエポキシ樹脂等
の外装樹脂材である。An example of the structure of this completely resin-sealed semiconductor device is shown in Figures 4 and 5. (1) is a heat sink as a pellet mount, (2) (2) - is an external part of the heat sink (1). For example, there are three leads extending in the direction, and the tip of the center one is attached to a heat sink (1
), and the two tips on both sides are located near the heat sink (1). (3)' is the semiconductor pellet mounted on the heat sink (1), (4) (4) is the semiconductor pellet (
(3) is a thin metal wire that electrically connects the surface electrode and the tip of the lead (2) (2), and (5) is formed by sealing the main parts including the heat sink (1) and the lead tip. Exterior resin material such as epoxy resin.
放熱板(1)の裏面に被着された外装樹脂材(5)の一
部は、放熱性を損なわない程度の薄い絶縁用樹脂膜(6
)として形成される。しかもこの膜の厚さが不均一の場
合、放熱板(1)からの熱放散性も不均一となって一部
に熱が集まり熱的破壊が起きることがあるため、絶縁用
樹脂膜(6)の厚さは均一にする必要がある。A part of the exterior resin material (5) adhered to the back surface of the heat sink (1) is covered with a thin insulating resin film (6) that does not impair heat dissipation performance.
) is formed as. Moreover, if the thickness of this film is uneven, the heat dissipation from the heat dissipation plate (1) will also be uneven, and heat may collect in some areas and cause thermal breakdown. ) must be uniform in thickness.
そこで、上記完全樹脂封止型半導体装置は、第6図に示
すように複数の半導体装置のリード(2)と放熱板(1
)をタイバー(7)−(8)で一体化したリードフレー
ム(9)を使い、タイバー(7)(8)により放熱板(
1)を両端支持した状態にし絶縁用樹脂膜(6)を均一
厚さにすべく形成する。そして、樹脂封止後、クイバー
(7)(8)を切断して個々の半導体装置に分割する。Therefore, in the completely resin-sealed semiconductor device, as shown in FIG.
) is integrated with tie bars (7)-(8) using a lead frame (9), and the heat sink (
1) is supported at both ends, and an insulating resin film (6) is formed to have a uniform thickness. After sealing with resin, the quivers (7) and (8) are cut and divided into individual semiconductor devices.
この時、タイバー(8)は本来、樹脂材で封止されて絶
縁されるべき放熱板(1)の一部が外部に突出したもの
であり、単に切断するだけでは絶縁不良を起こすため、
従来、次のようにして切断する。ます、第7図の左図に
示すように切断すべきタイバー(8)の両側の半導体装
置を、放熱板(1)と同じ形のレール(10)(10)
に載置し、更に押さえパッド(11) (11)で上
記各半導体装置を押圧固定する。その後、切断すべきタ
イバー(8)の上方からタイバー(8)の長さにほぼ等
しい幅を持つパンチ(12)を下降させれば、第7図の
右図に示すようにタイバー(8)が半導体装置の外装樹
脂材(5)の根元から引きちぎられる。At this time, the tie bar (8) is a part of the heat sink (1) that should originally be sealed and insulated with a resin material and protrudes to the outside, and simply cutting it will cause insulation failure.
Conventionally, cutting is performed as follows. First, as shown in the left diagram of FIG.
The above-mentioned semiconductor devices are further pressed and fixed using the holding pads (11) (11). After that, by lowering the punch (12) having a width approximately equal to the length of the tie bar (8) from above the tie bar (8) to be cut, the tie bar (8) is cut as shown in the right diagram of FIG. The exterior resin material (5) of the semiconductor device is torn off from the base.
光朋i’ −’ uIC口11月1皿点ところで、完全
樹脂封止型半導体装置の外装樹脂材から突出しているタ
イバー部(8)を切断する際、上述した従来のようにパ
ンチ(12)を用いて引きちぎった場合、第8図に示す
ように切断後にタイバー部(8)の断片(8°)が残る
。しかも、この断片(8゛)は先端部がパンチ(12)
の移動方向にダした状態になって歿る。By the way, when cutting the tie bar part (8) protruding from the exterior resin material of the fully resin-sealed semiconductor device, the punch (12) is used as in the conventional method described above. When the tie bar portion (8) is torn off using a saw blade, a fragment (8°) of the tie bar portion (8) remains after cutting, as shown in FIG. Moreover, this fragment (8゛) has a punch (12) at the tip.
It dies in a state where it is tilted in the direction of movement.
ところが、このように切断後のタイバー部断片(8’)
”先端がダしてくると、第9図に示すよ−Iに被取付面
に半導体装置を取付けた場合、被取付面(アース面)と
断片(8゛)の先端との間の距離が短くなり、しかも断
片(8゛)の先端は尖鋭になっているため放電し易く半
導体装置の絶縁耐圧が低下する危険性がある。However, after cutting the tie bar fragment (8')
``When the tip begins to dip, as shown in Figure 9, when a semiconductor device is mounted on the mounting surface (I), the distance between the mounting surface (ground surface) and the tip of the fragment (8゛) becomes smaller. Since it is short and the tip of the fragment (8°) is sharp, it is easy to discharge and there is a risk that the dielectric strength of the semiconductor device will decrease.
占 ゞ るための
本発明は、タイバー部により整列方向に直接連結された
各ペレットマウント部に半導体ペレットを固着すると共
にペレットマウント部近傍に位置するリード部と半導体
ペレットとを電気的に接続し、各半導体ペレットを含む
主要部を外装樹脂材にて樹脂封止成形した半導体装置に
おける上記タイバー部を切断する方法において、樹脂封
止成形後、外装樹脂材側方から突出しているタイバー部
を繰り返し折り曲げ応力を加えて、切断箇所に疲労スト
レスを与えてタイバー部を外装樹脂材から切断すること
により、切断後のタイバー部断片の先端にブレが生じな
いようにしたものである。In the present invention, a semiconductor pellet is fixed to each pellet mount part directly connected in the alignment direction by a tie bar part, and the semiconductor pellet is electrically connected to a lead part located near the pellet mount part. In a method for cutting the tie bar portion of a semiconductor device in which the main part including each semiconductor pellet is resin-sealed and molded with an exterior resin material, the tie bar portion protruding from the side of the exterior resin material is repeatedly bent after resin encapsulation molding. By applying stress and applying fatigue stress to the cut portion to cut the tie bar portion from the exterior resin material, wobbling is prevented from occurring at the tips of the cut tie bar portion fragments.
尖簾桝
本発明の一実施例を第1図を参照しながら以下説明する
。第1図(a)において、(13)と(14)は切断さ
れるタイバー部(8)の両端の半導体装置を載置するレ
ールAとレールB、(13’ )と(14’ )はレー
ルAとレールBにそれぞれ載置されている各半導体装置
を押圧して固定するレール八”とレールB”であり、レ
ールB(14)とレールB’ (14’ )は上下動可
能である。An embodiment of the present invention will be described below with reference to FIG. In FIG. 1(a), (13) and (14) are rails A and B on which semiconductor devices are placed at both ends of the tie bar section (8) to be cut, and (13') and (14') are rails. A rail 8'' and a rail B'' press and fix semiconductor devices placed on rails A and B, respectively, and rail B (14) and rail B'(14') are movable up and down.
即ち、まず第1図(a)に示すように切断されるクイバ
一部(8)の両端の半導体装置をレールA (13)と
レール八“(13′)、及びレールB (14)とレー
ルB’ (14”)によりチャックする。そして、第1
図(b)(C)に示すように上記各半導体装置をチャッ
クしたまま、レールB (14)とレールB’ (14
°)の方を数回上下動させる。そうすると、タイバー部
(8)の両端の根元の部分に疲労ストレスが加わる。そ
こで、第1図(d)に示すようにレールB (14)と
レールB’ (14’ )を元の位置に戻してから、従
来と同様にダメージの生じたタイバー部(8)の上方か
らタイバー部(8)の長さにほぼ等しい幅を持つパンチ
(15)を下降させタイバー部(8)に切断応力を加え
ると、第1図(e)に示すようにタイバー部(8)が外
装樹脂材(5)から切断される。That is, first, as shown in FIG. 1(a), the semiconductor devices at both ends of the quiver part (8) to be cut are connected to rail A (13) and rail 8''(13'), and rail B (14) and rail. Chuck by B'(14"). And the first
As shown in Figures (b) and (C), rail B (14) and rail B' (14) are kept chucked.
°) move up and down several times. As a result, fatigue stress is applied to the root portions of both ends of the tie bar portion (8). Therefore, as shown in Fig. 1(d), after returning the rail B (14) and rail B'(14') to their original positions, as before, from above the damaged tie bar part (8) When a punch (15) having a width approximately equal to the length of the tie bar portion (8) is lowered to apply cutting stress to the tie bar portion (8), the tie bar portion (8) will be exposed to the exterior as shown in Fig. 1(e). It is cut from the resin material (5).
このようにして切断されたタイバー部(8)の切断面は
シャープになり第2図及び第3図に示すようにその断片
(8゛)にダレが発生しない。The cut surface of the tie bar portion (8) thus cut is sharp, and no sag occurs in the fragment (8°) as shown in FIGS. 2 and 3.
又、上記切断工程において、半導体装置をチャックした
レールB (14)とレールB’ (14”)を上下動
させる回数を多くすれば、パンチ(15)を用いること
なくタイバー部(8)を切断することもできる。In addition, in the above cutting step, if the number of vertical movements of rail B (14) and rail B'(14") on which the semiconductor device is chucked is increased, the tie bar portion (8) can be cut without using the punch (15). You can also.
光肌例班果
本発明によれば、完全樹脂封止型半導体装置のように半
導体ペレットの樹脂封止成形後、外装樹脂材の側方から
リードフレームのタイバー部が突出している半導体装置
の上記タイバー部を樹脂封止成形後に切断する方法にお
いて、タイバー部を繰り返し折り曲げ疲労ストレスを与
えて切断するようにしたから、クイバ一部の切断面がシ
ャープになりその断片に切断によるダレが発生しなくな
って半導体装置の絶縁耐圧の低下を防止できる。According to the present invention, the above-mentioned semiconductor device, such as a completely resin-sealed semiconductor device, has a tie bar portion of a lead frame protruding from the side of an exterior resin material after a semiconductor pellet is resin-sealed and molded. In the method of cutting the tie bar part after resin molding, the tie bar part is repeatedly bent and subjected to fatigue stress, so the cut surface of a part of the quiver becomes sharp and no sag occurs in the pieces due to cutting. Therefore, it is possible to prevent a decrease in the dielectric strength voltage of the semiconductor device.
第1図は本発明に係る半導体装置の製造方法の−・実施
例の説明図、第2図は本発明の一実施例により製造され
た半導体装置の斜視図で、第3図はその側面図、第4図
は完全樹脂封止型半導体装置の部分断面平面図で、第5
図はその側断面図、第6図は第4図半導体装置のリード
フレームの部分平面図、第7図は第5図リードフレーム
のベレットマウント部’c a 結−t−ルタイバー部
を切断する従来の工程の説明図、第8図は第7図の工程
により製造された半導体装置の斜視図で、第9図はその
側面図である。
(1)−ベレットマウント部、(2)−リード部、(3
) −半導体ペレット、(5) −外装樹脂材、(8)
−・・タイバー部。FIG. 1 is an explanatory diagram of an embodiment of the method for manufacturing a semiconductor device according to the present invention, FIG. 2 is a perspective view of a semiconductor device manufactured according to an embodiment of the present invention, and FIG. 3 is a side view thereof. , FIG. 4 is a partial cross-sectional plan view of a completely resin-sealed semiconductor device, and FIG.
6 is a partial plan view of the lead frame of the semiconductor device shown in FIG. FIG. 8 is a perspective view of a semiconductor device manufactured by the process of FIG. 7, and FIG. 9 is a side view thereof. (1)-Bellet mount part, (2)-Lead part, (3
) - Semiconductor pellet, (5) - Exterior resin material, (8)
−・・Tie bar part.
Claims (1)
レットマウント部に半導体ペレットを固着すると共にペ
レットマウント部近傍に位置するリード部と半導体ペレ
ットとを電気的に接続し、各半導体ペレットを含む主要
部を外装樹脂材にて樹脂封止成形した半導体装置におけ
る上記タイバー部を切断する方法において、樹脂封止成
形後、外装樹脂材側方から突出しているタイバー部を繰
り返し折り曲げ応力を加えてて切断箇所に疲労ストレス
を与えてタイバー部を外装樹脂材から切断することを特
徴とする半導体装置の製造方法。(1) Semiconductor pellets are fixed to each pellet mount part that is directly connected in the alignment direction by a tie bar part, and the semiconductor pellets are electrically connected to the lead part located near the pellet mount part, and the main part containing each semiconductor pellet is In a method for cutting the tie bar portion of a semiconductor device whose portion is resin-sealed and molded with an exterior resin material, the tie bar portion protruding from the side of the exterior resin material is cut by repeatedly bending and applying stress after molding the exterior resin material. A method for manufacturing a semiconductor device, characterized in that a tie bar portion is cut from an exterior resin material by applying fatigue stress to the portion.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16980884A JPS6147658A (en) | 1984-08-14 | 1984-08-14 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16980884A JPS6147658A (en) | 1984-08-14 | 1984-08-14 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6147658A true JPS6147658A (en) | 1986-03-08 |
Family
ID=15893278
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16980884A Pending JPS6147658A (en) | 1984-08-14 | 1984-08-14 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6147658A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5690877A (en) * | 1991-09-30 | 1997-11-25 | Elliott; Alex | Method of processing a semiconductor chip package |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS52126587A (en) * | 1976-04-14 | 1977-10-24 | Bosch Gmbh Robert | Cutting method of strand or strip member and apparatus therefor |
-
1984
- 1984-08-14 JP JP16980884A patent/JPS6147658A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS52126587A (en) * | 1976-04-14 | 1977-10-24 | Bosch Gmbh Robert | Cutting method of strand or strip member and apparatus therefor |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5690877A (en) * | 1991-09-30 | 1997-11-25 | Elliott; Alex | Method of processing a semiconductor chip package |
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