JPS6147067B2 - - Google Patents
Info
- Publication number
- JPS6147067B2 JPS6147067B2 JP5181179A JP5181179A JPS6147067B2 JP S6147067 B2 JPS6147067 B2 JP S6147067B2 JP 5181179 A JP5181179 A JP 5181179A JP 5181179 A JP5181179 A JP 5181179A JP S6147067 B2 JPS6147067 B2 JP S6147067B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- voltage
- oscillation
- line
- lithium battery
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000010355 oscillation Effects 0.000 claims description 20
- 239000003990 capacitor Substances 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 4
- WHXSMMKQMYFTQS-UHFFFAOYSA-N Lithium Chemical compound [Li] WHXSMMKQMYFTQS-UHFFFAOYSA-N 0.000 description 21
- 229910052744 lithium Inorganic materials 0.000 description 21
- 238000010586 diagram Methods 0.000 description 5
- NDVLTYZPCACLMA-UHFFFAOYSA-N silver oxide Chemical compound [O-2].[Ag+].[Ag+] NDVLTYZPCACLMA-UHFFFAOYSA-N 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- PWHULOQIROXLJO-UHFFFAOYSA-N Manganese Chemical compound [Mn] PWHULOQIROXLJO-UHFFFAOYSA-N 0.000 description 2
- 229910052748 manganese Inorganic materials 0.000 description 2
- 239000011572 manganese Substances 0.000 description 2
- 229910001923 silver oxide Inorganic materials 0.000 description 2
- 230000005611 electricity Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G04—HOROLOGY
- G04G—ELECTRONIC TIME-PIECES
- G04G19/00—Electric power supply circuits specially adapted for use in electronic time-pieces
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Dc-Dc Converters (AREA)
Description
【発明の詳細な説明】
本発明は電池電圧と電池電圧よりも低い電圧で
駆動される回路の電源に用いられる降圧回路に関
し、特に液晶表示装置を用いた電子時計あるいは
卓上電子計算機に用いられる降圧回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a step-down circuit used as a power source for a battery voltage and a circuit driven at a voltage lower than the battery voltage. Regarding circuits.
一般に液晶表示装置を用いた電子時計あるいは
卓上電子計算機は電源に酸化銀電池あるいはマン
ガン電池を用いているが、電池電圧は1.5Vであ
るために昇圧回路を設け２倍の3.0Vを得て電圧
3.0V及び1.5Vの電圧を供給していた。しかし近
年酸化銀電池やマンガン電池より高エネルギー密
度で長寿命のリチウム電池が開発されており、こ
のリチウム電池を電子時計あるいは卓上電子計算
機に使用することは寿命の点で非常に有用であ
る。これら電子時計あるいは卓上電子計算機は
3.0Vで駆動される回路と、1.5Vで駆動される回
路とを有し、リチウム電池の超電力が3.0Vであ
るから、リチウム電池の電圧を1/2に降圧する必
要がある。降圧する手段には例えば抵抗に依つて
分割する方法があるが、この方法では常時抵抗に
電流が流れる為に消費電力の点で不利である。 Generally, electronic watches or desk computers using liquid crystal display devices use silver oxide batteries or manganese batteries as power sources, but since the battery voltage is 1.5V, a booster circuit is installed to double the voltage to 3.0V.
It supplied voltages of 3.0V and 1.5V. However, in recent years, lithium batteries have been developed that have a higher energy density and a longer lifespan than silver oxide batteries or manganese batteries, and the use of these lithium batteries in electronic watches or desktop computers is extremely useful in terms of longevity. These electronic clocks or desktop electronic calculators
It has a circuit driven at 3.0V and a circuit driven at 1.5V, and since the superpower of the lithium battery is 3.0V, it is necessary to reduce the voltage of the lithium battery to 1/2. For example, there is a method of dividing the voltage by using resistors, but this method is disadvantageous in terms of power consumption because current always flows through the resistors.
また上述の欠点を改善する手段として第１図に
示す方法がある。これは電子時計等の回路が集積
されたLSI１内部に設けられたゲートにコンデン
サ２，３が接続され、同様にLSI１内部に設けら
れた発振、分周回路からの制御信号に依つてゲー
トが開閉され、コンデンサ２，３の接続を直列と
並列とに交互に切換えて、ＶSS2に−1.5Vを発生
せしめるのである。従つて降圧がコンデンサ２，
３に依るために消費電力は少ないのであるが、発
振・分周回路は−1.5Vで駆動される為、リチウ
ム電池４の印加時に発振を開始させるには始めに
ＶSS2端子に電圧を印加する必要がある。よつて
第１図に於いてはリチウム電池４とＶSS2端子と
の間に高抵抗５を挿入していた。しかし発振が開
始した後には高抵抗５間には1.5Vの電位差が生
じる為に高抵抗５で無駄な電力が消費される。ま
た高抵抗５の抵抗値を更に高くすると、コンデン
サ３との時定数が大きくなり発振が開始されるま
での時間が長くなり好ましくない。 There is also a method shown in FIG. 1 as a means for improving the above-mentioned drawbacks. In this case, capacitors 2 and 3 are connected to gates provided inside LSI 1 in which circuits such as electronic clocks are integrated, and the gates are opened and closed depending on control signals from the oscillation and frequency dividing circuits also provided inside LSI 1. The connection of capacitors 2 and 3 is alternately switched between series and parallel to generate -1.5V at V SS2 . Therefore, the voltage drop is capacitor 2,
3, the power consumption is low, but since the oscillation/divider circuit is driven at -1.5V, to start oscillation when the lithium battery 4 is applied, voltage must first be applied to the V SS2 terminal. There is a need. Therefore, in FIG. 1, a high resistance 5 is inserted between the lithium battery 4 and the V SS2 terminal. However, after oscillation starts, a potential difference of 1.5V is generated between the high resistors 5, so power is wasted in the high resistors 5. Further, if the resistance value of the high resistor 5 is further increased, the time constant with the capacitor 3 becomes large and the time until oscillation starts becomes long, which is not preferable.
本発明は上述した点に鑑みて為されたものであ
り、従来の欠点を完全に除去した降圧回路を提供
するものである。以下図面を参照して本発明を詳
述する。 The present invention has been made in view of the above-mentioned points, and it is an object of the present invention to provide a voltage step-down circuit that completely eliminates the conventional drawbacks. The present invention will be described in detail below with reference to the drawings.
第２図は本発明の実施例を示す回路図であり、
電子時計の場合を示す。 FIG. 2 is a circuit diagram showing an embodiment of the present invention,
The case of an electronic clock is shown.
６は時計動作に必要な基準周波数を作る水晶発
振回路、７は基準周波数を適当な周波数に分周す
る分周回路、８は計数回路及び表示装置等から成
る時計回路、９，１０，１１，１２は制御信号φ
１，φ２に依つて開閉が制御されるゲート、１
３，１４は電圧を降圧するコンデンサ、１５はリ
チウム電池、１６は発振回路６の発振を開始させ
るために電圧を印加するＮ−MOS、１７はＮ−
MOS１６の開閉を制御するフリツプフロツプで
ある。 6 is a crystal oscillation circuit that creates a reference frequency necessary for clock operation; 7 is a frequency divider circuit that divides the reference frequency into an appropriate frequency; 8 is a clock circuit consisting of a counting circuit, a display device, etc.; 9, 10, 11, 12 is the control signal φ
1 , gate whose opening/closing is controlled by φ 2 , 1
3 and 14 are capacitors that step down the voltage, 15 is a lithium battery, 16 is an N-MOS that applies voltage to start oscillation of the oscillation circuit 6, and 17 is an N-
This is a flip-flop that controls the opening and closing of MOS16.
水晶発振回路６及び分周回路７は比較的高周波
で動作するので、消費電力をできるだけ減少させ
るために電源電圧は−1.5VのＶSS2が印加され
る。一方時計回路８は分周回路７で分周された比
較的低周波の信号に依つて時刻を計数し表示する
ため、あるいは表示装置が液晶を用いたものであ
れば液晶を駆動するために、電源電圧は−3.0V
のＶSS1が印加される。またフリツプフロツプ１
７の電源電圧もＶSS1である。コンデンサ１３の
一方の端子と接地及び−1.5VラインＶSS2との間
には各ゲート９，１２が接続され、コンデンサ１
３の他方の端子と−1.5VラインＶSS2及び−3.0V
ラインＶSS1との間には各々ゲート１０，１１が
接続される。またコンデンサ１４は−1.5Vライ
ンＶSS2と接地間に接続され、リチウム電池１５
は−3.0VラインＶSS1に接続される。ゲート９，
１０，１１，１２の開閉を制御する制御信号φ
１，φ２は−1.5VラインＶSS2で駆動される分周
回路７に依つて作られる。Ｎ−MOS１６は−
3.0VラインＶSS1と−1.5VラインＶSS2との間に接
続され、そのゲートにはフリツプフロツプ１７の
出力が印加されている。フリツプフロツプ１７
はリチウム電池１５を接続した時に出力される初
期設定信号INTに依つてセツト状態となり、分周
回路７から出力される信号ＳRによつてリセツト
状態となる。 Since the crystal oscillator circuit 6 and the frequency divider circuit 7 operate at a relatively high frequency, a power supply voltage of -1.5V V SS2 is applied to reduce power consumption as much as possible. On the other hand, the clock circuit 8 uses a relatively low frequency signal divided by the frequency dividing circuit 7 to count and display the time, or if the display device uses a liquid crystal, to drive the liquid crystal. Power supply voltage is -3.0V
V SS1 is applied. Also flipflop 1
The power supply voltage of 7 is also V SS1 . Each gate 9, 12 is connected between one terminal of the capacitor 13 and the ground and the -1.5V line V SS2 .
3 and the -1.5V line V SS2 and -3.0V
Gates 10 and 11 are connected to the line V SS1 , respectively. The capacitor 14 is also connected between the -1.5V line V SS2 and ground, and the lithium battery 15
is connected to the -3.0V line VSS1 . gate 9,
Control signal φ that controls opening and closing of 10, 11, and 12
1 and φ2 are created by a frequency divider circuit 7 driven by the -1.5V line V SS2 . N-MOS16 is -
It is connected between the 3.0V line VSS1 and the -1.5V line VSS2 , and the output of the flip-flop 17 is applied to its gate. flip flop 17
is set to the set state by the initial setting signal INT output when the lithium battery 15 is connected, and is set to the reset state by the signal S R output from the frequency divider circuit 7.
次に第３図を参照して降圧の動作原理を述べ
る。 Next, the operating principle of voltage reduction will be described with reference to FIG.
第３図ａに示す如く、分周回路から出力される
制御信号φ１及びφ２は互いに逆相な交番信号で
ある。先ず制御信号φ１が接地即ちＶDDレベルで
制御信号φ２がＶSS2レベルであるときゲート
９，１０は導通し、ゲート１１，１２は非導通と
なる。従つてコンデンサ１３，１４は第３図ｂに
示す如く直列に接続され更にリチウム電池１５が
接続される。このときコンデンサ１３，１４の静
電容量をＣとし、リチウム電池１５の起電力をＥ
とすると、コンデンサ１３，１４には各々Ｑ＝
ＣＥ／２の電気量が充電される。この状態で制御信号
φ１がＶSSレベル、制御信号φ２がＶDDレベルと
なると、ゲート９，１０は非導通となり、ゲート
１１，１２が導通する。従つてコンデンサ１３，
１４は第３図Ｃ示す如く並列に接続され、その端
子間電圧は2Q／2C＝２．ＣＥ／２／2C＝１／２Ｅとなる
。従
つて以上の動作を繰り返すことによつて−1.5V
ラインＶSS2には１／２Ｅ即ち−1.5Vの電圧が生じる。 As shown in FIG. 3a, the control signals φ 1 and φ 2 outputted from the frequency dividing circuit are alternating signals having mutually opposite phases. First, when the control signal φ 1 is grounded, that is, at the V DD level, and the control signal φ 2 is at the V SS2 level, gates 9 and 10 are conductive, and gates 11 and 12 are non-conductive. Therefore, the capacitors 13 and 14 are connected in series as shown in FIG. 3b, and the lithium battery 15 is further connected. At this time, the capacitance of the capacitors 13 and 14 is C, and the electromotive force of the lithium battery 15 is E.
Then, capacitors 13 and 14 each have Q=
CE/2 amount of electricity is charged. In this state, when the control signal φ 1 becomes the V SS level and the control signal φ 2 becomes the V DD level, the gates 9 and 10 become non-conductive, and the gates 11 and 12 become conductive. Therefore, the capacitor 13,
14 are connected in parallel as shown in FIG. 3C, and the voltage between their terminals is 2Q/2C=2. CE/2/2C=1/2E. Therefore, by repeating the above operation, -1.5V
A voltage of 1/2E or -1.5V appears on the line V SS2 .
この動作は発振回路６の発振が開始して定常状態
での動作である。This operation is an operation in a steady state after the oscillation circuit 6 starts oscillating.
一方、リチウム電池１５を接続した時は発振回
路６は発振していないので制御信号φ１及びφ２
が出力されず−1.5VラインＶSS2には電圧が生じ
ない。そこで本発明では−3.0VラインＶSS1と−
1.5VラインＶSS2との間に設けたＮ−MOS１６と
フリツプフロツプ１７の働きに依つて発振を開始
させる。以下その動作を説明する。 On the other hand, when the lithium battery 15 is connected, the oscillation circuit 6 is not oscillating, so the control signals φ 1 and φ 2
is not output and no voltage is generated on the -1.5V line V SS2 . Therefore, in the present invention, the −3.0V line V SS1 and −
Oscillation is started by the action of the N-MOS 16 and flip-flop 17 provided between the 1.5V line VSS2 . The operation will be explained below.
フリツプフロツプ１７は−3.0VラインＶSS1即
ちリチウム電池１５の電圧で駆動されるため、リ
チウム電池１５が接続された時点で動作可能な状
態になる。一方リチウム電池１５を接続すると電
子時計内のすべてをリセツトする初期設定信号
INTが初期設定回路（図示せず）から出力され
る。この初期設定信号INTは動作可能な状態にあ
るフリツプフロツプ１７のセツト端子Ｓに印加さ
れるのでフリツプフロツプ１７はセツト状態とな
り、出力には接地レベル即ちＶDDレベルの信号
が出力される。するとＮ−MOS１６は導通状態
になり、リチウム電池１５の電圧がＮ−MOS１
６を介して−1.5VラインＶSS2に印加される。従
つて−1.5VラインＶSS2で駆動される発振回路６
及び分周回路７には−3.0Vが印加され、発振回
路６の発振が開始し、その基準周波数は分周回路
７に依つて分周される。すると分周回路７からは
制御信号φ１及びφ２が出力されゲート９，１
０，１１，１２の開閉が為され、前述した如く降
圧動作が開始される。一方分周回路８からは発振
が開始したことに依つて信号ＳRが出力される。
信号ＳRはフリツプフロツプ１７のリセツト端子
Ｒに印加されるのでフリツプフロツプ１７はリセ
ツト状態となり、その出力はＶSS1レベルとな
る。従つてＮ−MOS１６のゲートにはＶSS1レベ
ルが印加されるためにＮ−MOS１６は遮断状態
になり、リチウム電池１５の電圧が−1.5Vライ
ンＶSS2に印加されなくなり、−1.5ラインＶSS2に
は降圧動作に依つて−1.5Vの電圧が生じ定常状
態となる。よつて降圧動作時は−3.0VラインＶS
Ｓ１と−1.5VラインＶSS2との間に電流が流れない
ので無駄な電力消費が無くなるのである。 Since the flip-flop 17 is driven by the -3.0V line V SS1 , that is, the voltage of the lithium battery 15, it becomes operational when the lithium battery 15 is connected. On the other hand, when the lithium battery 15 is connected, the initial setting signal resets everything in the electronic clock.
INT is output from an initialization circuit (not shown). Since this initial setting signal INT is applied to the set terminal S of the flip-flop 17 which is in an operable state, the flip-flop 17 is set to the set state, and a signal at the ground level, that is, the VDD level is outputted. Then, N-MOS16 becomes conductive, and the voltage of lithium battery 15 becomes N-MOS1.
6 to the -1.5V line VSS2 . Therefore, the oscillation circuit 6 driven by the -1.5V line V SS2
-3.0V is applied to the frequency divider circuit 7, the oscillation circuit 6 starts oscillating, and the reference frequency is divided by the frequency divider circuit 7. Then, control signals φ 1 and φ 2 are output from the frequency divider circuit 7 and the gates 9 and 1
0, 11, and 12 are opened and closed, and the step-down operation is started as described above. On the other hand, the frequency dividing circuit 8 outputs a signal S R due to the start of oscillation.
Since the signal S R is applied to the reset terminal R of the flip-flop 17, the flip-flop 17 is in the reset state and its output becomes the V SS1 level. Therefore, since the V SS1 level is applied to the gate of the N-MOS 16, the N-MOS 16 is cut off, and the voltage of the lithium battery 15 is no longer applied to the -1.5 V line V SS2 , and the voltage of the lithium battery 15 is no longer applied to the -1.5 V line V SS2. Due to step-down operation, a voltage of -1.5V is generated and becomes a steady state. Therefore, during buck operation, the -3.0V line V S
Since no current flows between S1 and the -1.5V line V SS2 , unnecessary power consumption is eliminated.
上述した如く本発明に依ればリチウム電池を接
続した時にＮ−MOSが導通して発振回路及び分
周回路に電圧を供給し、発振が開始した後にＮ−
MOSを遮断することに依つて、消費電力を極少
にすることができ、リチウム電池の特性を最大に
生かし、電子時計あるいは卓上電子計算機等の長
寿命化が図れるものである。 As described above, according to the present invention, when a lithium battery is connected, the N-MOS becomes conductive and supplies voltage to the oscillation circuit and the frequency dividing circuit, and after oscillation starts, the N-MOS becomes conductive.
By shutting off the MOS, power consumption can be minimized, making the most of the characteristics of lithium batteries, and extending the lifespan of electronic watches, desktop computers, etc.
第１図は従来例を示す回路図、第２図は本発明
の実施例を示す回路図、第３図は第２図に示した
実施例の動作を説明するための波形図ａ及び接続
図ｂ，ｃである。
６……水晶発振回路、７……分周回路、８……
時計回路、９，１０，１１，１２……ゲート、１
３，１４……コンデンサ、１５……リチウム電
池、１６……Ｎ−MOS、１７……フリツプフロ
ツプである。
Fig. 1 is a circuit diagram showing a conventional example, Fig. 2 is a circuit diagram showing an embodiment of the present invention, and Fig. 3 is a waveform diagram a and a connection diagram for explaining the operation of the embodiment shown in Fig. 2. b, c. 6... Crystal oscillation circuit, 7... Frequency dividing circuit, 8...
Clock circuit, 9, 10, 11, 12...gate, 1
3, 14... capacitor, 15... lithium battery, 16... N-MOS, 17... flip-flop.
Claims (1)
号に依つてコンデンサの接続方法がゲートで切換
えられ電池電圧の降圧が為される降圧回路に於い
て、降圧された電圧で駆動される前記発振及び分
周回路等の電源と前記電池電圧との間にスイツチ
ング素子を設け、該スイツチング素子は発振回路
の発振開始後オフ状態になることを特徴とする降
圧回路。1. In a step-down circuit in which the connection method of a capacitor is switched by a gate depending on a control signal output from an oscillation or frequency dividing circuit to step down the battery voltage, the oscillation and dividing circuit driven by the step-down voltage are used. 1. A step-down circuit characterized in that a switching element is provided between a power source such as a circuit and the battery voltage, and the switching element is turned off after the oscillation circuit starts oscillating.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5181179A JPS55144772A (en) | 1979-04-26 | 1979-04-26 | Step-down circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5181179A JPS55144772A (en) | 1979-04-26 | 1979-04-26 | Step-down circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55144772A JPS55144772A (en) | 1980-11-11 |
| JPS6147067B2 true JPS6147067B2 (en) | 1986-10-17 |
Family
ID=12897287
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5181179A Granted JPS55144772A (en) | 1979-04-26 | 1979-04-26 | Step-down circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS55144772A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5835613A (en) * | 1981-08-27 | 1983-03-02 | Toshiba Corp | Electronic circuit |
| US4433282A (en) * | 1981-12-08 | 1984-02-21 | Intersil | Monolithic voltage divider |
| FR2659507B1 (en) * | 1990-03-09 | 1995-03-31 | Sumitomo Metal Ind | DIRECT CURRENT TO DIRECT CURRENT CONVERTER. |
-
1979
- 1979-04-26 JP JP5181179A patent/JPS55144772A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS55144772A (en) | 1980-11-11 |
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