JPS6146633A - Circuit of intermittent reception - Google Patents

Circuit of intermittent reception

Info

Publication number
JPS6146633A
JPS6146633A JP59167655A JP16765584A JPS6146633A JP S6146633 A JPS6146633 A JP S6146633A JP 59167655 A JP59167655 A JP 59167655A JP 16765584 A JP16765584 A JP 16765584A JP S6146633 A JPS6146633 A JP S6146633A
Authority
JP
Japan
Prior art keywords
output
voltage
power
signal
reception circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59167655A
Other languages
Japanese (ja)
Other versions
JPH0317419B2 (en
Inventor
Keisuke Suwa
諏訪　敬祐
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP59167655A priority Critical patent/JPS6146633A/en
Publication of JPS6146633A publication Critical patent/JPS6146633A/en
Publication of JPH0317419B2 publication Critical patent/JPH0317419B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W52/00—Power management, e.g. TPC [Transmission Power Control], power saving or power classes
    • H04W52/02—Power saving arrangements
    • H04W52/0209—Power saving arrangements in terminal devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Circuits Of Receivers In General (AREA)
  • Mobile Radio Communication Systems (AREA)

Abstract

PURPOSE:To prevent a transient current from flowing to a coupling capacitor through the intermittent power supply by amplifying a difference between a reception circuit output and an output voltage of a voltage divider at a differential amplifier to output a signal eliminating a DC component from the output of the reception circuit. CONSTITUTION:A waveform of an output 21 of the reception circuit is a rectangular wave from C around a voltage V2 at a period when a power is fed to the reception circuit 1, is 0 at a period when no power is fed to the reception circuit 1. On the other hand, the potential at a voltage division output terminal 25 is also V2 when a power switch 4 is turned on and 0 when the power switch 4 is turned off. Thus, a differential amplifier 7 amplifies only a portion corresponding to a digital signal in an output signal of the reception circuit 1 when the power switch 4 is turned on. No DC component appears at an output terminal 26 of the differential amplifier 7 but only the digital signal portion D appears, and then no transient charge/discharge current flows to the coupling capacitor 2, a signal waveform at a load terminal 22 is a digital signal E without distortion and a zero cross comparator discriminates accurately a signal.

Description

【発明の詳細な説明】 発明の属する技術分野 本発明は、携帯形の移動無線機等の動作用の電力を間欠
的に供給することにより、待受は時におけるバッテリの
消費電力の節減を図るようにした間欠受信回路に関する
。DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention aims to reduce the power consumption of a battery during standby by intermittently supplying power for the operation of a portable mobile radio device, etc. The present invention relates to an intermittent reception circuit.

従来技術 第５図は、従来の間欠受信回路の一例を示す図であり、
受信回路１には電源スイッチ４を介して間欠的に動作電
源が供給される。電源スイッチ４は、制御端子２３から
入力される制御信号によって周期的にオン、オフ制御さ
れて、電源端子２４から入力される電源を間欠的に受信
回路ｌに供給する。受信回路ｌは、電源が供給されたと
き受信入力端子２０から入力された信号を受信して受信
回路の出力端子２１に出力し、該信号は結合コンデンサ
２および負荷抵抗３から構成されるコンデンサ結合回路
を介して負荷端子２２に出力される。すなわち、受信信
号は間欠的に負荷端子２２に出力される。負荷端子２２
の信号をモニタしていて、自己が呼ばれている場合は、
電源スイッチ４を連続的にオンとして受信回路ｌを連続
動作させて通信を行なう。上述の間欠受信回路は、待受
は時の消費電力が少なくてすむため、移動機等に使用さ
れている。Prior Art FIG. 5 is a diagram showing an example of a conventional intermittent reception circuit.
Operating power is intermittently supplied to the receiving circuit 1 via the power switch 4 . The power switch 4 is periodically controlled on and off by a control signal inputted from the control terminal 23, and intermittently supplies power inputted from the power supply terminal 24 to the receiving circuit l. The receiving circuit 1 receives a signal input from the receiving input terminal 20 when power is supplied, and outputs it to the output terminal 21 of the receiving circuit, and the signal is transmitted through a capacitor coupling composed of a coupling capacitor 2 and a load resistor 3. It is output to the load terminal 22 via the circuit. That is, the received signal is intermittently output to the load terminal 22. Load terminal 22
If you are monitoring the signal of and self is called,
Communication is performed by continuously turning on the power switch 4 and operating the receiving circuit 1 continuously. The above-mentioned intermittent reception circuit is used in mobile devices and the like because it consumes less power during standby.

しかし、上述の従来回路を、デジタル信号を受信する回
路に適用したときは、以下の述べるような欠点がある。However, when the above-described conventional circuit is applied to a circuit that receives digital signals, it has the following drawbacks.

今、受信入力端子２０に無変調の信号が入力されていて
、電源スイッチ４が第６図（Ａ）に示すようにオン、オ
フされたとき、受信回路１の出力端子２１の直流電圧波
形が同図（Ｂ）に示すように変化するものとすると、電
源オン時の受信回路の出力端子２１の電圧ｖ２と、電源
オフ時の受信回路の出力端子２１の電圧Ｖａ　　（通常
はＯである）との電圧差ｖ１によって結合コンデンサ２
が充電または放電される。従って、負荷端子２２の電圧
波形は同図（Ｃ）に示すようになる。すなわち、入力信
号が無変調であるにも拘らず、負荷端子２２には過渡的
な充放電波形が出力される。Now, when an unmodulated signal is input to the reception input terminal 20 and the power switch 4 is turned on and off as shown in FIG. 6(A), the DC voltage waveform at the output terminal 21 of the reception circuit 1 is Assuming that the voltage changes as shown in (B) of the same figure, the voltage v2 at the output terminal 21 of the receiving circuit when the power is on and the voltage Va at the output terminal 21 of the receiving circuit when the power is off (usually O) Coupling capacitor 2 due to the voltage difference v1 between
is charged or discharged. Therefore, the voltage waveform of the load terminal 22 becomes as shown in FIG. That is, even though the input signal is unmodulated, a transient charge/discharge waveform is output to the load terminal 22.

従って、第７図（Ａ）に示すようなデジタル波形によっ
て変調された信号が受信入力端子２０から入力され、電
源が同図ＣＢ）に示すようにオン。Therefore, a signal modulated by a digital waveform as shown in FIG. 7(A) is input from the receiving input terminal 20, and the power is turned on as shown in FIG. 7(CB).

オフされた場合は、受信回路の出力端子２１の信号電圧
波形は同図（Ｃ）に示すようになり、負荷端子２２の信
号電圧波形は同図（［１）に示すようになる。すなわち
、第６図（Ｃ）に示したような過渡的な充放電電圧波形
にデジタル信号が重畳された電圧波形となる。一方、デ
ジタル信号の検出器としては、一般にゼロクロスコンパ
レータが使用されている。すなわち、信号レベルが正の
とき“１゛′と判定し、信号レベルが負のとき“Ｏ”′
と判定する検出器である。従って、第７図（Ｄ）に示す
ような信号をゼロクロスコンパレータで検出したときは
、電源がオンされてから時間Ｔの間をすべて”　ｔ　”
と判定し、判定を誤ってしまうという欠点がある。また
、電源オフの期間はすべて“Ｏ”として判定する。この
ため、受信信号を正確に判定することができず、例えば
アドレス信号による呼出し等を検出することが困難とな
る。When it is turned off, the signal voltage waveform at the output terminal 21 of the receiving circuit becomes as shown in FIG. 2C, and the signal voltage waveform at the load terminal 22 becomes as shown in FIG. That is, the voltage waveform becomes a transient charging/discharging voltage waveform as shown in FIG. 6(C) with a digital signal superimposed thereon. On the other hand, a zero-cross comparator is generally used as a digital signal detector. In other words, when the signal level is positive, it is determined as "1", and when the signal level is negative, it is determined as "O"'.
This is a detector that determines that. Therefore, when the zero-cross comparator detects a signal like the one shown in FIG.
The disadvantage is that the judgment is incorrect. In addition, all periods in which the power is off are determined to be "O". Therefore, the received signal cannot be accurately determined, making it difficult to detect, for example, a call based on an address signal.

発明の目的 本発明の目的は、上述の従来の欠点を解決し、電源オン
時には直ちに正確に受信信号を検出することができる間
欠受信回路を提供することにある。OBJECTS OF THE INVENTION An object of the present invention is to solve the above-mentioned conventional drawbacks and to provide an intermittent reception circuit that can accurately detect a received signal immediately when the power is turned on.

発明の構成 本発明の間欠受信回路は、間欠的に電源が供給される受
信回路と、該受信回路に間欠的に電源を供給するための
電源スイッチとを備えて、前記受信回路の出力信号をコ
ンデンサ結合によって負荷に供給するようにした間欠受
信回路において、前記受信回路に供給される電圧を分圧
する分圧器と、該分圧器の出力電圧と前記受信回路の出
力との差を増幅する差動増幅器とを備えて、該差動増幅
器の出力をコンデンサ結合によって負荷に供給すること
を特徴とする。Structure of the Invention An intermittent receiving circuit of the present invention includes a receiving circuit to which power is intermittently supplied, and a power switch for intermittently supplying power to the receiving circuit, and a power switch that outputs an output signal of the receiving circuit. In an intermittent reception circuit configured to supply a load to a load through capacitor coupling, the voltage divider divides the voltage supplied to the reception circuit, and the differential voltage divider amplifies the difference between the output voltage of the voltage divider and the output of the reception circuit. and an amplifier, and the output of the differential amplifier is supplied to a load by capacitor coupling.

発明の実施例 次に、本発明について、図面を参照して詳細に説明する
。Embodiments of the Invention Next, the present invention will be described in detail with reference to the drawings.

第１図は、本発明の一実施例を示す回路図である。すな
わち、電源端子２４から電源スイッチ４を通して受信回
路１に電源を供給し、電源スイッチ４は制御端子２３か
ら入力される制御信号によって周期的にオン、オフ制御
される。受信回路１の出力端子２１は抵抗８を介して差
動増幅器７の十人力に入力させる。一方電源スイッチ４
の出力を抵抗１３と抵抗１２からなる分圧器に入力させ
、該分圧器の分圧出力端子２５を抵抗９を介して差動増
幅器７の一人力に入力させる。また、差動増幅器７の十
人力は抵抗１０によって接地され、差動増幅器７の一人
力は抵抗１１によって差動出力端子２８に接続されてい
る。抵抗８および９の抵抗値は、いずれもＲ１であり、
抵抗ｌＯと１１の抵抗値は、共にＲ２である。今、電源
オン時における受信回路１の出力電圧の直流分が■１で
あるとすれば、分圧出力端子２５の電圧がｖｌになるよ
うに分圧器を調整しておく。差動増幅器７は、受信回路
の出力端子２１と分圧出力端子２５の電圧差を増幅して
差動出力端子２６に出力する。そして、差動出力端子２
６を結合コンデンサ２と負荷抵抗３からなるコンデンサ
結合回路を介して負荷端子２２に出力させる。FIG. 1 is a circuit diagram showing one embodiment of the present invention. That is, power is supplied from the power terminal 24 to the receiving circuit 1 through the power switch 4, and the power switch 4 is periodically controlled on and off by a control signal input from the control terminal 23. The output terminal 21 of the receiving circuit 1 is input to the output terminal of the differential amplifier 7 via the resistor 8. On the other hand, power switch 4
The output is inputted to a voltage divider made up of resistors 13 and 12, and the divided voltage output terminal 25 of the voltage divider is inputted to the output of the differential amplifier 7 via the resistor 9. Further, the output terminal of the differential amplifier 7 is grounded by a resistor 10, and the output terminal of the differential amplifier 7 is connected to a differential output terminal 28 by a resistor 11. The resistance values of resistors 8 and 9 are both R1,
The resistance values of the resistors 10 and 11 are both R2. Now, assuming that the DC component of the output voltage of the receiving circuit 1 when the power is turned on is 1, the voltage divider is adjusted so that the voltage at the divided voltage output terminal 25 becomes vl. The differential amplifier 7 amplifies the voltage difference between the output terminal 21 of the receiving circuit and the voltage divided output terminal 25 and outputs it to the differential output terminal 26. And differential output terminal 2
6 is outputted to the load terminal 22 via a capacitor coupling circuit consisting of a coupling capacitor 2 and a load resistor 3.

次に、本実施例の動作について、第１図および第２図を
参照して説明する。第２図は、本実施例の各部信号を示
すタイムチャートである。今、受信入力端子２０から第
２図（Ａ）に示すようなデジタル信号が入力され、受信
回路１の電源が同図（Ｂ）に示すようにオン、オフされ
るものとする。°受信回路ｌに電源が供給される期間に
おいては、受信回路の出力端子２１の信号波形は同図（
Ｃ）に示すように、電圧ｖ２を中心とする矩形波の信号
となり、受信回路１に電源が供給されない期間の電圧は
通常Ｏとなる。一方、分圧出力端子２５の電位も電源ス
イッチ４がオンの期間はＶ２であり、電源スイッチ４が
オフの期間はＯとなる。従って、電源スイッチ４がオン
の期間では、受信回路の出力端子２１の中心電圧（直流
電圧成分）Ｖ２　と分圧出力端子２５の電圧差はなく、
差動増幅器７は受信回路ｌの出力信号中のデジタル信号
に対応する部分のみを増幅する。従って、差動出力端子
２６には、直流出力は現れず、同図（Ｄ）に示すように
デジタル信号部分のみが出現する。Next, the operation of this embodiment will be explained with reference to FIGS. 1 and 2. FIG. 2 is a time chart showing signals of various parts in this embodiment. Now, it is assumed that a digital signal as shown in FIG. 2(A) is inputted from the receiving input terminal 20, and the power of the receiving circuit 1 is turned on and off as shown in FIG. 2(B). °During the period when power is supplied to the receiving circuit l, the signal waveform at the output terminal 21 of the receiving circuit is as shown in the figure (
As shown in C), the signal becomes a rectangular wave centered on the voltage v2, and the voltage is normally O during a period when power is not supplied to the receiving circuit 1. On the other hand, the potential of the divided voltage output terminal 25 is also V2 during the period when the power switch 4 is on, and is O during the period when the power switch 4 is off. Therefore, while the power switch 4 is on, there is no voltage difference between the center voltage (DC voltage component) V2 of the output terminal 21 of the receiving circuit and the divided voltage output terminal 25.
The differential amplifier 7 amplifies only the portion of the output signal of the receiving circuit l that corresponds to the digital signal. Therefore, no DC output appears at the differential output terminal 26, and only a digital signal portion appears, as shown in FIG.

従って、結合コンデンサ２には過渡的な充放電電流は流
れず、負荷端子２２の信号波形は同図（Ｅ）に示すよう
に、歪のないデジタル信号となり、ゼロクロスコンパレ
ータによって正確に判定することが可能となる。Therefore, no transient charging/discharging current flows through the coupling capacitor 2, and the signal waveform at the load terminal 22 becomes an undistorted digital signal as shown in FIG. It becomes possible.

しかし、例えば、大地から浮いた電源から受信回路１に
電源を供給し、そのオン、オフ制御を片線のオン、オフ
で行なうような場合は、電源スイッチ４をオフした状態
で、受信回路の出力端子２１に一定の残留電圧ｖ３が出
力されることがある。However, for example, when power is supplied to the receiving circuit 1 from a power source floating above the ground, and its on/off control is performed by turning on and off one wire, the receiving circuit is A constant residual voltage v3 may be output to the output terminal 21.

このようなときは、電源オン時に分圧出力端子２５に出
力される電圧が、ｖ２−ｖ３　　（＝ｖ□）となるよう
に設定すれば、差動出力端子２６の直流電圧成分は電源
オン時にはｋＶａ（ただし、ｋは差動増幅器７の電圧利
得）となり、電源オフ時にもｋＶ３　となるから、上述
と同様に結合コンデンサ２に過渡的な充放電電流を流さ
ないで、負荷端子２２にはデジタル信号のみを取出すこ
とができる。In such a case, if you set the voltage output to the divided voltage output terminal 25 when the power is turned on to be v2-v3 (=v□), the DC voltage component of the differential output terminal 26 will be the same when the power is turned on. kVa (where k is the voltage gain of the differential amplifier 7), and is kV3 even when the power is off. Therefore, as described above, without passing transient charging/discharging current to the coupling capacitor 2, the load terminal 22 is connected to a digital Only the signal can be extracted.

第３図は、本発明の他の実施例を示す回路図であり、第
４図はその各部信号を示すタイムチャートである。この
場合は、電源端子２４から電源スイッチ４を通して受信
回路１および抵抗１３．１２からなる（第１の）分圧器
に電源を供給することは前述の実施例と同様であるが、
電源端子２４からスイッチング素子５を通して抵抗１５
と１４からなる第２の分圧器に接続し、制御端子２３か
ら入力される制御信号をインバータ６で反転させてスイ
ッチング素子５をオン、オフ制御させることにより、電
源スイッチ４とスイッチング素子５を相補的にオン、オ
フさせる。そして、上記第２の分圧器の出力を分圧出力
端子２５に接続し、受信回路ｌに電源を供給しない期間
に受信回路の出力端子２１に出力される残留電圧■３を
上記第２の分圧器の出力電圧によってキャンセルするよ
うに設定する。なお、前記第１の分圧器の出力は、電源
オン時の受信回路ｌの直流出力電圧■２に設定する。従
って、今、受信入力端子２０から第４図（Ａ）に示すよ
うなデジタル信号が入力され、受信回路ｌの電源が同図
（Ｂ）に示すようにオン、オフされるものとすると、受
信回路の出力端子２１の信号波形は同図（Ｃ）に示すよ
うに、受信回路ｌに電源が供給される期間においては電
圧ｖ２を中心とする矩形波の信号となり、受信回路ｌに
電源が供給されない期間には残留電圧■３となる。一方
、分圧出力端子２５の電位は、同図（Ｄ）に示すように
、電源スイッチ４がオンの期間は■２であり、電源スイ
ッチ４がオフの期間はｖ３となる。従って、電源ス石ツ
チ４がオンの期間では、受信回路の出力端子２１の中心
電圧（直流電圧）Ｖ２　と分圧出力端子２５の電圧差は
なく、差動増幅器７は受信回路ｌの出力信号中のデジタ
ル信号に対応する部分のみを増幅する。また、電源スイ
ッチ４のオフ期間には受信回路の出力端子２１と分圧出
力端子２５の電位差はなく、差動出力端子２６には、直
流出力は現れない。従って、差動出力端子２６の信号波
形は、同図（Ｅ）に示すように電源オン期間に直流成分
のないデジタル信号部分のみが出現する。従って、結合
コンデンサ２には過渡的な充放電電流は流れず、負荷端
子２２の信号波形は同図ＣＦ）に示すように、歪のない
デジタル信号となり、ゼロクロスコンパレータによって
正確に判定することが可能となる。すなわち、電源オフ
時に受信回路ｌの出力に残留電圧が発生するような場合
でも容易に入力デジタル信号を判定できる利点がある。FIG. 3 is a circuit diagram showing another embodiment of the present invention, and FIG. 4 is a time chart showing signals of each part thereof. In this case, power is supplied from the power terminal 24 through the power switch 4 to the receiving circuit 1 and the (first) voltage divider consisting of the resistors 13 and 12, as in the previous embodiment, but
A resistor 15 is connected from the power supply terminal 24 through the switching element 5.
and 14, and inverts the control signal input from the control terminal 23 with the inverter 6 to control the switching element 5 on and off, thereby making the power switch 4 and the switching element 5 complementary. Turn it on and off. Then, the output of the second voltage divider is connected to the divided voltage output terminal 25, and the residual voltage 3 outputted to the output terminal 21 of the receiving circuit during the period when power is not supplied to the receiving circuit 1 is outputted to the second voltage divider. Set to cancel by the output voltage of the voltage regulator. Note that the output of the first voltage divider is set to the DC output voltage 2 of the receiving circuit 1 when the power is turned on. Therefore, assuming that a digital signal as shown in FIG. 4(A) is input from the receiving input terminal 20 and the power of the receiving circuit l is turned on and off as shown in FIG. 4(B), the reception As shown in the same figure (C), the signal waveform of the output terminal 21 of the circuit becomes a rectangular wave signal centered on voltage v2 during the period when power is supplied to the receiving circuit l, and the signal waveform is a rectangular wave signal centered on the voltage v2. During the period when no voltage is applied, the residual voltage becomes ■3. On the other hand, as shown in FIG. 2D, the potential of the divided voltage output terminal 25 is ■2 during the period when the power switch 4 is on, and is v3 during the period when the power switch 4 is off. Therefore, during the period when the power supply switch 4 is on, there is no voltage difference between the center voltage (DC voltage) V2 of the output terminal 21 of the receiving circuit and the voltage divided output terminal 25, and the differential amplifier 7 uses the output signal of the receiving circuit l. Only the part corresponding to the digital signal inside is amplified. Further, during the off period of the power switch 4, there is no potential difference between the output terminal 21 of the receiving circuit and the voltage divided output terminal 25, and no DC output appears at the differential output terminal 26. Therefore, in the signal waveform of the differential output terminal 26, only a digital signal portion without a DC component appears during the power-on period, as shown in FIG. Therefore, no transient charging/discharging current flows through the coupling capacitor 2, and the signal waveform at the load terminal 22 becomes an undistorted digital signal as shown in CF), which can be accurately determined by the zero-cross comparator. becomes. That is, there is an advantage that the input digital signal can be easily determined even when a residual voltage is generated in the output of the receiving circuit 1 when the power is turned off.

発明の効果 以上のように、本発明においては、受信回路の出力電圧
の直流成分をキャンセルするための分圧器を備えて、前
記受信回路の出力と上記分圧器の出力電圧の差を差動増
幅器で増幅することによって受信回路の出力から直流成
分を除去した信号を出力するように構成したから、間欠
的電源供給によって結合コンデンサに過渡的な充放電電
流が流れることを防止し、入力デジタル信号を正確に判
定することが可能となるという効果を有する。Effects of the Invention As described above, the present invention includes a voltage divider for canceling the DC component of the output voltage of the receiving circuit, and converts the difference between the output voltage of the receiving circuit and the output voltage of the voltage divider into a differential amplifier. Since the configuration is configured to output a signal with the DC component removed from the output of the receiving circuit by amplifying it with This has the effect of making it possible to make accurate determinations.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例を示す回路図、第２図は上記
実施例の各部信号を示すタイムチャート、第３図は本発
明の他の実施例を示す回路図、第４図は上記実施例の各
部信号を示すタイムチヤード、第５図は従来の間欠受信
回路の一例を示す回路図、第６図は上記従来例の無変調
信号入力時の各部信号を示すタイムチャート、第７図は
上記従来例のデジタル信号入力時の各部信号を示すタイ
ムチャートである。 図において、ｌ：受信回路、２：結合コンデンサ、３：
負荷抵抗、４：電源スイッチ、５ニスイツチング素子、
６：インバータ、７：差動増幅器、８〜１５：抵抗、２
０：受信入力端子、２１：受信回路の出力端子、２２：
負荷端子、２３：制御端子、２４：電源端子、２５：分
圧出力端子、２６：差動出力端子。Fig. 1 is a circuit diagram showing one embodiment of the present invention, Fig. 2 is a time chart showing various signals of the above embodiment, Fig. 3 is a circuit diagram showing another embodiment of the invention, and Fig. 4 is a circuit diagram showing an embodiment of the present invention. 5 is a circuit diagram showing an example of a conventional intermittent reception circuit; FIG. 6 is a time chart showing various signals when an unmodulated signal is input in the conventional example; FIG. FIG. 7 is a time chart showing signals of various parts when digital signals are input in the conventional example. In the figure, l: receiving circuit, 2: coupling capacitor, 3:
Load resistance, 4: power switch, 5 switching element,
6: Inverter, 7: Differential amplifier, 8-15: Resistor, 2
0: Reception input terminal, 21: Reception circuit output terminal, 22:
Load terminal, 23: Control terminal, 24: Power supply terminal, 25: Voltage division output terminal, 26: Differential output terminal.

Claims (2)

【特許請求の範囲】[Claims] （１）間欠的に電源が供給される受信回路と、該受信回
路に間欠的に電源を供給するための電源スイッチとを備
えて、前記受信回路の出力信号をコンデンサ結合によつ
て負荷に供給するようにした間欠受信回路において、前
記受信回路に供給される電圧を分圧する分圧器と、該分
圧器の出力電圧と前記受信回路の出力との差を増幅する
差動増幅器とを備えて、該差動増幅器の出力をコンデン
サ結合によつて負荷に供給することを特徴とする間欠受
信回路。(1) A receiving circuit that is intermittently supplied with power, and a power switch for intermittently supplying power to the receiving circuit, and the output signal of the receiving circuit is supplied to a load through capacitor coupling. An intermittent reception circuit configured to include a voltage divider that divides the voltage supplied to the reception circuit, and a differential amplifier that amplifies the difference between the output voltage of the voltage divider and the output of the reception circuit, An intermittent reception circuit characterized in that the output of the differential amplifier is supplied to a load through capacitor coupling. （２）特許請求の範囲第１項記載の間欠受信回路におい
て、前記電源スイッチと相補的にオン、オフされるスイ
ッチング素子と、該スイッチング素子に接続された第２
の分圧器とを備えて、前記受信回路に電源を供給しない
期間は上記第２の分圧器の出力を前記差動増幅器に入力
させるように構成されたことを特徴とするもの。(2) In the intermittent receiving circuit according to claim 1, a switching element is turned on and off in a complementary manner to the power switch, and a second switching element is connected to the switching element.
and a voltage divider, and is configured such that the output of the second voltage divider is input to the differential amplifier during a period when power is not supplied to the receiving circuit.
JP59167655A 1984-08-10 1984-08-10 Circuit of intermittent reception Granted JPS6146633A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59167655A JPS6146633A (en) 1984-08-10 1984-08-10 Circuit of intermittent reception

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59167655A JPS6146633A (en) 1984-08-10 1984-08-10 Circuit of intermittent reception

Publications (2)

Publication Number Publication Date
JPS6146633A true JPS6146633A (en) 1986-03-06
JPH0317419B2 JPH0317419B2 (en) 1991-03-08

Family

ID=15853780

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59167655A Granted JPS6146633A (en) 1984-08-10 1984-08-10 Circuit of intermittent reception

Country Status (1)

Country Link
JP (1) JPS6146633A (en)

Also Published As

Publication number Publication date
JPH0317419B2 (en) 1991-03-08

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