JPS6143496A - Method of mounting printed board part - Google Patents

Method of mounting printed board part

Info

Publication number
JPS6143496A
JPS6143496A JP16486584A JP16486584A JPS6143496A JP S6143496 A JPS6143496 A JP S6143496A JP 16486584 A JP16486584 A JP 16486584A JP 16486584 A JP16486584 A JP 16486584A JP S6143496 A JPS6143496 A JP S6143496A
Authority
JP
Japan
Prior art keywords
package
printed circuit
circuit board
mounting
printed board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16486584A
Other languages
Japanese (ja)
Other versions
JPH0770800B2 (en
Inventor
伴野 治彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP59164865A priority Critical patent/JPH0770800B2/en
Publication of JPS6143496A publication Critical patent/JPS6143496A/en
Publication of JPH0770800B2 publication Critical patent/JPH0770800B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔発明の技術分野〕 −本発明はプリント基板へのパッケージ部品の実装に関
する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] - The present invention relates to mounting package components on printed circuit boards.

〔発明の技術的背景と問題点〕[Technical background and problems of the invention]

近年LSI容量の増大により、そのパッケージも大形化
し、引出しピンの数も増し100ピンを有するフラット
パッケージのものも普通になった。
In recent years, as the capacity of LSIs has increased, their packages have become larger and the number of lead-out pins has also increased, and flat packages with 100 pins have become commonplace.

しかし現在のところそれらのLSIは機能的には同じで
あっても、そのパッケージを見るとメーカ毎に大きさ、
ピンの配列、ピン間隔が異なるものが多く、これらをプ
リント基板上にマウントする側からすれば同じ機能のL
SIだからといって、どれでも取付は可能というわけに
行かす、1つの型のLSIだけを用いた基板へのマウン
ト設計では、この種LSIの受給不足の状況もあり、マ
ウント生産上に不都合があった。そのためプリント基板
上でパッケージの異なる同一機能部品のどちらもマウン
ト出来るよう、それぞれに対しマウント可能な専用スペ
ースを設はプリント配線の引廻しも行っていた。その結
果は機能上必要な1つのパッケージのために2つ分のス
ペースを占有され、プリント配線の引廻しにも多くのス
ペースを必要としプリント基板上のスペースの利用に無
駄が大きい欠点があった。
However, at present, even though these LSIs are functionally the same, when looking at their packages, they vary in size and size depending on the manufacturer.
Many have different pin arrangements and pin spacing, and from the perspective of mounting them on a printed circuit board, they have the same function.
Just because it's an SI, it doesn't mean that any type of LSI can be mounted.In designing a mount on a board using only one type of LSI, there was a shortage of supplies of this type of LSI, which caused problems in terms of mount production. Therefore, in order to be able to mount both of the same functional components in different packages on a printed circuit board, a dedicated mounting space was created for each, and the printed wiring was also routed. As a result, one functionally necessary package occupied two spaces, and a large amount of space was also required for running the printed wiring, resulting in a large waste of space on the printed circuit board. .

〔発明の目的〕[Purpose of the invention]

本発明は上記欠点を除去できる部品取付法を提供するこ
とを目的とする。
SUMMARY OF THE INVENTION It is an object of the present invention to provide a component mounting method that can eliminate the above-mentioned drawbacks.

〔発明の概要〕[Summary of the invention]

本発明においては椴゛能的に同じLSIの2つのパンケ
ージに対する取付用ランドをプリント基板の表と裏に別
々に設けて基板上のスペースを1パツケ一ジ分でよくし
、表裏の縦の接続も利用できて基板上での配線の引廻し
スペースの減少も可能としたものである。
In the present invention, the mounting lands for the two pancages of the same LSI are provided separately on the front and back sides of the printed circuit board, so that the space on the board is only needed for one package, and the vertical connection between the front and back sides is achieved. This also makes it possible to reduce the space required for wiring on the board.

〔発明の実施例〕[Embodiments of the invention]

第1図は本発明の一実施例を示す側面図、第2図はプリ
ン1一基板の一方の面にマウントされたパッケージの平
面図、第3図はプリント基板の他方の面にマウントされ
たパッケージの平面図である。
Fig. 1 is a side view showing an embodiment of the present invention, Fig. 2 is a plan view of the package mounted on one side of the printed circuit board, and Fig. 3 is a plan view of the package mounted on the other side of the printed circuit board. FIG. 3 is a plan view of the package.

これらの図に於て、(1)及び(2)はそれぞれ機能的
には同じでパッケージが異なるLSI、(3)はこれら
t、 S I (t)(2)が表裏両面に分けてマウン
トされるプリント基+&、(4)はパッケージ本体、(
5)は接続ピンである。これら両パッケージのピンから
入出力する信号の配置は第1のピンを基準にしてそれぞ
れが左右逆まわり、即ち、重力で透視した場合の同まわ
りになるようにしてプリント基板の表裏で同一信号の接
続を容易にすることにより配線の引廻しを少くするよう
ランドの配置を考慮することが望ましい。
In these figures, (1) and (2) are LSIs that are functionally the same but have different packages, and (3) are LSIs that are mounted separately on both the front and back sides. (4) is the package body, (
5) is a connection pin. The arrangement of the signals input and output from the pins of both packages is such that they rotate in opposite directions to the left and right with respect to the first pin, that is, they rotate in the same direction when viewed through with gravity, so that the same signals are transmitted on the front and back of the printed circuit board. It is desirable to consider the layout of lands so as to reduce the amount of wiring by facilitating connections.

〔発明の効果〕〔Effect of the invention〕

本発明は以上・のようになるものであって、LSI特に
1社の製品ついて部品欠品の対象となり易いものを機能
上採用した場合においても欠品の場合他社のLSIを使
用してマウント生産上の事故を回避でき、しかもプリン
ト基板上に格別のスペースを必要としない効果がある。
The present invention is as described above, and even if an LSI, especially one made by one company, is functionally adopted and is likely to be subject to parts shortage, in the event of a shortage, LSI of another company is used for mounting production. The above accident can be avoided, and there is an effect that no special space is required on the printed circuit board.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示す側面図、第2図及び第
3図はプリント基板のそれぞれ表裏にマウントされたパ
ッケージの平面図である。 1:第1のパッケージ部品、 2:第2のパッケージ部
品、3ニブリント基板、 4:パッケージ本体、 5:
接続ピン。
FIG. 1 is a side view showing one embodiment of the present invention, and FIGS. 2 and 3 are plan views of packages mounted on the front and back sides of a printed circuit board, respectively. 1: First package component, 2: Second package component, 3 Niblint board, 4: Package body, 5:
connection pin.

Claims (1)

【特許請求の範囲】[Claims] 機能的には互換性があるが構造的に互換性のない第1、
第2のパッケージ部品のいずれかを採用するパッケージ
部品のプリント基板への実装において、プリント基板の
表面と裏面に分けて第1又は第2のパッケージ取付用ラ
ンドを設けておき、採用したパッケージに応じて表面又
は裏面に実装することを特徴とするプリント基板部品取
付法。
The first, which is functionally compatible but structurally incompatible;
When mounting a package component that adopts one of the second package components onto a printed circuit board, a first or second package mounting land is provided separately on the front and back surfaces of the printed circuit board, depending on the package adopted. A printed circuit board component mounting method characterized by mounting on the front or back surface.
JP59164865A 1984-08-08 1984-08-08 PCB mounting method Expired - Lifetime JPH0770800B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59164865A JPH0770800B2 (en) 1984-08-08 1984-08-08 PCB mounting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59164865A JPH0770800B2 (en) 1984-08-08 1984-08-08 PCB mounting method

Publications (2)

Publication Number Publication Date
JPS6143496A true JPS6143496A (en) 1986-03-03
JPH0770800B2 JPH0770800B2 (en) 1995-07-31

Family

ID=15801388

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59164865A Expired - Lifetime JPH0770800B2 (en) 1984-08-08 1984-08-08 PCB mounting method

Country Status (1)

Country Link
JP (1) JPH0770800B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11709296B2 (en) 2021-07-27 2023-07-25 Racing Optics, Inc. Low reflectance removable lens stack
US11723420B2 (en) 2021-06-08 2023-08-15 Racing Optics, Inc. Low haze UV blocking removable lens stack
US11808952B1 (en) 2022-09-26 2023-11-07 Racing Optics, Inc. Low static optical removable lens stack
US11807078B2 (en) 2020-03-10 2023-11-07 Racing Optics, Inc. Protective barrier for safety glazing

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5522174U (en) * 1978-07-31 1980-02-13

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5522174U (en) * 1978-07-31 1980-02-13

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11807078B2 (en) 2020-03-10 2023-11-07 Racing Optics, Inc. Protective barrier for safety glazing
US11723420B2 (en) 2021-06-08 2023-08-15 Racing Optics, Inc. Low haze UV blocking removable lens stack
US11709296B2 (en) 2021-07-27 2023-07-25 Racing Optics, Inc. Low reflectance removable lens stack
US11808952B1 (en) 2022-09-26 2023-11-07 Racing Optics, Inc. Low static optical removable lens stack

Also Published As

Publication number Publication date
JPH0770800B2 (en) 1995-07-31

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