JPS6143021A - Phase synchronizing oscillating circuit - Google Patents

Abstract

PURPOSE:To quicken the minute change in a low-order digit frequency by modulating the single side band of an output frequency of a VCO with a frequency to be shifted and comparing the frequency-divided output of the output and a reference frequency in phase. CONSTITUTION:An output frequency 11 of the VCO11 is used as a carrier, which is fed to a single side band SSB generating circuit 3 together with an output frequency 21 of an oscillator 2 having a frequency to be shifted. A single tone 31 obtained by a applying SSB modulation to the frequency 11 by means of the frequency 21 is generated from the circuit 3, inputted to a frequency divider 4, where the signal is frequency-divided by a prescribed frequency division ratio, and the phase of the frequency 41 and that of the reference frequency 5 are compared by a phase comparator 6. The VCO1 is controlled by a signal 71 of a phase comparison output 61 through an LPF7 to generate a PLL oscillator output from the VCO. The frequency division ratio of the frequency divider 4 is fixed and the frequency of the oscillator 2 is changed in, e.g., 10Hz step, the oscillating frequency of the VCO1 is changed in 10Hz step.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は無線通信機の局部発振器に多く用いられる位
相同期（以下にはＰＬＬと略記する）発振器に関し、特
に下位桁周波数の変化に適する回路方式を提供するにあ
る。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a phase-locked (hereinafter abbreviated as PLL) oscillator that is often used as a local oscillator in wireless communication equipment, and particularly relates to a circuit that is suitable for changes in lower digit frequencies. There is a method to provide.

〔従来技術とその問題点〕[Prior art and its problems]

ＰＬＬ発振回路の原理と回路構成について拡極めて周知
であるゆえ詳細な・説明は省略するが、その電圧制御発
振器（以下にＨｖｃｏ’と略記する）の発振周波数の設
定は原則として制御ループ中の分局器の分局比を変える
ととｋよって行い、その変化ステッｆＦｉ基準周波数に
等しくなる。従って変化ステップを小さくするために基
準周波数を小さく取ると、位相比較器の出力する制御出
力中に基準周波数のリツｆルが含まれ易く、発振出力の
Ｃ／Ｉ（が悪化する問題が、りＪ）、また分周器の分局
比が大きくなって、制御ルーシダインの低下による安定
度の劣化がある。特に無線受信機の同調目的には発振の
ロ、クア、ｆタイムの問題があるので、基準周波数は１
・、Ｑ　ｋＨｚ程度までとし、それ以下の桁の周波数設
定のため炉は制御ループ中にミクサ段を設けてその局部
発振周波数を変化する手段や多重ＰＬＬ等の手段が用い
られているが、発振器相互の干渉中ミクサ段で発生し易
いスジリアスを除去するためには高度の設計と製作の技
術を必要とするものである〇 第４図に本発明に関連の深い従来技術による受信機の回
路構成例を示して概要を説明すると、アンテナに入力′
した０・〜３　Ｑ　Ｍ）！ｇ間の受信波は第１゜ミクサ
で約４０　ＭＨｚの第１中間周波となり、さらに第２ミ
クサで約９　ＭＨｚの第゛２中間周波となって検波器に
加えられる。第１局部発振器は約４０〜７０　ＭＨｚ間
を１０　ｋＨｚステップで変化するＰＬＬ発振器で、１
０　、ｋ）Ｉｚ以上の桁の受信周波数を設定し、第２局
部発振器は約３１〜３０．９９　ＭＨｚ間を１０Ｈ！ス
テツプで変化するＰＬＬ発振器であるが、可変周波数水
晶発振器（ＶＸＯ）等の安定なアナログ発振器で代用す
る場合もある。Since the principle and circuit configuration of the PLL oscillator circuit are well known, a detailed explanation will be omitted, but as a general rule, the setting of the oscillation frequency of the voltage controlled oscillator (hereinafter abbreviated as Hvco') is performed by branching in the control loop. When the division ratio of the device is changed, the change step fFi becomes equal to the reference frequency. Therefore, if the reference frequency is set small in order to reduce the change step, ripples in the reference frequency are likely to be included in the control output output from the phase comparator, and the problem of worsening C/I of the oscillation output becomes worse. J) Also, the division ratio of the frequency divider increases, and the stability deteriorates due to a decrease in control lucidine. In particular, for the purpose of tuning a radio receiver, there are problems with the oscillation b, qua, and f times, so the reference frequency is 1
・, up to about Q kHz, and in order to set the frequency in orders of magnitude lower than that, the furnace uses a mixer stage in the control loop to change the local oscillation frequency, a multiple PLL, etc. In order to eliminate streaks that tend to occur in the mixer stage during mutual interference, advanced design and manufacturing techniques are required. Figure 4 shows the circuit configuration of a receiver according to the prior art, which is closely related to the present invention. To give an example and give an overview, the input to the antenna is
0・~3 Q M)! The received wave between g is converted into a first intermediate frequency of approximately 40 MHz by the first mixer, and further converted into a second intermediate frequency of approximately 9 MHz by the second mixer, which is applied to the detector. The first local oscillator is a PLL oscillator that changes frequency between approximately 40 and 70 MHz in 10 kHz steps.
0, k) Set the reception frequency of digits higher than Iz, and the second local oscillator will transmit 10H between approximately 31 and 30.99 MHz! Although the PLL oscillator changes in steps, a stable analog oscillator such as a variable frequency crystal oscillator (VXO) may be substituted.

第１局部発振器の基準周波数は数ＭＨｚを分周した１　
０　ｋＨｚであシ、第２局部発振器はさらに分周した１
０Ｈｚとすれば簡単であるが、前述のロックアラブタイ
ムやＣ／Ｎの問題があシ、１０　ｋＨｚ基準で１０Ｈｚ
ステツプの変化を行うために種々の工夫がなされている
。しかしいづれにしても回路の複雑化等の難点がある。The reference frequency of the first local oscillator is 1, which is obtained by dividing several MHz.
0 kHz, the second local oscillator is further divided into 1
It would be easy to set it to 0Hz, but there are problems with the lock-on time and C/N as mentioned above, and 10Hz based on 10kHz.
Various methods have been used to change the steps. However, in either case, there are drawbacks such as the complexity of the circuit.

〔発明の目的〕[Purpose of the invention]

この発明は第４図例示の第２局部発振器として適当な、
下位桁周波数の微細な変化が迅速にでき、かつＣ／Ｎの
良好なＰＬＬ発振器を提供するにある。This invention is suitable for the second local oscillator illustrated in FIG.
It is an object of the present invention to provide a PLL oscillator that can quickly make minute changes in lower digit frequency and has a good C/N ratio.

〔発明の概要〕[Summary of the invention]

この発明は特許請求の範囲に記載し、第１図にその構成
を示すように、電圧制御発振器（以下にはｖＣＯと略記
する）ｌの出力周波数１１をキャリアとして、周波数偏
移すべき周波数の発振器２の出力周波数２１とを単側帯
波（以下にはＳＳＢと略記する）発生器３に加えて得た
シングルトーン３１を分周器４を通して分周した周波数
４１と基準周波数５とを位相比較器６にて位相比較し、
画周波数の位相差出力６１をＬＰＦを通して得た制御用
カフ１をＶＣＯ１に加えて発振周波数を制御するＰＬＬ
発振器である。This invention is described in the claims, and as shown in FIG. The output frequency 21 of the oscillator 2 is added to the single sideband (hereinafter abbreviated as SSB) generator 3, and the single tone 31 obtained is divided through the frequency divider 4, and the frequency 41 and the reference frequency 5 are phase-compared. Compare the phase with device 6,
A PLL that controls the oscillation frequency by adding the control cuff 1 obtained by passing the phase difference output 61 of the image frequency through the LPF to the VCO 1.
It is an oscillator.

上記の本発明の特徴とするところは、ｖＣＯｌの発振周
波数を制御するのに分局器４の分周比を変える代シに分
周器４に入力するループ周波数を偏移して行い、そのた
めに発振周波数１１をキャリアとし、偏移周波数２１に
てＳＳＢ変調して得たシングルトーンがキャリア周波数
に対して変調周波数だけ偏移していることを利用してい
る。従って第１図において分局器４の分周比は固定とし
、那波数調整用発振器２の発振周波数２１を例えば１０
Ｈｚステツプで変化すればＶＣｏ　、　１の発振周波数
１１も１０Ｈｚステツプで変、化するし、発振周波数２
１を連続変化とすれば発振周波数１１１も連続変化する
ことができ、第４図例示の第２局部発振器に用いる場合
は発振周波数１１の変化範囲は１０’ｋＨｚであるから
発振器２は１０・Ｈｚ〜ｌ　ＯｋＨｚの低、周波発振器
でよく、ＣＲ発振器等で周波数精度も安定度も十分なも
のが容易に得られる利点がある。The feature of the present invention described above is that the oscillation frequency of vCOl is controlled by shifting the loop frequency input to the frequency divider 4 instead of changing the frequency division ratio of the divider 4. It utilizes the fact that the single tone obtained by SSB modulation using the oscillation frequency 11 as a carrier and the shift frequency 21 is shifted by the modulation frequency with respect to the carrier frequency. Therefore, in FIG. 1, the frequency division ratio of the divider 4 is fixed, and the oscillation frequency 21 of the frequency adjustment oscillator 2 is set to 10, for example.
If it changes in Hz steps, the oscillation frequency 11 of VCo 1 will also change in 10Hz steps, and the oscillation frequency 2 will also change in 10Hz steps.
If 1 is made to change continuously, the oscillation frequency 111 can also be changed continuously, and when used in the second local oscillator shown in FIG. A low frequency oscillator of ~l OkHz is sufficient, and there is an advantage that a CR oscillator or the like with sufficient frequency accuracy and stability can be easily obtained.

〔発明の実施例〕[Embodiments of the invention]

本発明の一つの実施例を第２図に示して説明する。但し
本発明の基本回路と動作については「発明の概要」の項
にて述べて、あるので、本項で社主として本発明の構成
要素であるＳＳＢ発生器の回路構成部分について説明す
、る・ 第１図のｌはＰＬＬ発振器のＶＣＯ１の出力周波数１１
をキャリアとし、変調周波数２１にて６８Ｂ変調を行い
８ＳＢ波３１を発生、するＳＳＢ発生器部分であって変
調周波数２１がシングルトーンであれば出力３１も上側
帯波（Ｕ８Ｂ）ま、た杜下側帝波（ＬＩＩＩＢ）のシン
グルトーンが得られる。このＳＳＢ発生器としては大別
して位相シフト方式とフィルタ方式がアシ、前者は全自
作が可能なので初期時代には多く用いられたが、フィル
タが安価に入手可能となって現在では専らフィルタ方式
が用いられている。One embodiment of the present invention will be described with reference to FIG. However, since the basic circuit and operation of the present invention are described in the "Summary of the Invention" section, in this section I will explain the circuit components of the SSB generator, which is a component of the present invention. l in Figure 1 is the output frequency 11 of VCO1 of the PLL oscillator.
is the SSB generator part that uses 68B modulation at modulation frequency 21 to generate 8SB wave 31 using the carrier as carrier, and if modulation frequency 21 is a single tone, output 31 is also an upper sideband wave (U8B). A single tone of side wave (LIIIB) can be obtained. SSB generators can be roughly divided into phase shift type and filter type.The former was widely used in the early days because it was possible to make everything yourself, but now that filters are available at low cost, the filter type is used exclusively. It is being

然しなから、ＳＳＭ通信にお−ては変調周波数が約３０
０〜３，０００　Ｈｚであるのに対して、本発明の実施
例では１０〜１０，０　（１０Ｈｓが要求されるためキ
ャリア抑圧に問題があり、第２図１の部分は位相シフト
方式８８８発生器−を採用している。その原理は８８Ｂ
解説書には必らず詳述されているので簡単に述べると、
入力キャリア１１は高周波移相器３２によシ＋４５°と
一４５°の移相されてＢ　Ｍ、　（平衡変調器）　１　
（、Ｌ３　）と８Ｍ２（３４）に加え、また焚調周波数
２１は低周波移相器３５によシ＋４５゜と−４５°の移
相されてＢＭＩと８Ｍ２に加えて、それぞれ平衡変調を
行い、３３と３４の出力を出カドランス３６にて合成し
て（シングル長ツドでも可能）２次側にＥＢＢ出力３１
を取多出すのであって、一方の移相器のＢＭＩと８Ｍ２
への接続を逆とすることによって出力をＵＳＢでもＬＳ
Ｂでも任意に設定する仁とができる。第３図において、
ループ周波数３１は分局器４に入力する周波数であって
、分局比をＮ基準周波数を１０　ｋＨｚとすれば１０　
ｋＨｚ　Ｘ　Ｎで固定周波数（第４図の場合は３１ＭＨ
ｚとなる）である。ＶＣＯの発振周波数１１はこれから
−１０ｋＨｚ　（３０，９９’１Ｍ＊　）の変化が必要
なので、変調周波数２１を１０　ｋＨｚとしたときＶＣ
Ｏ１の出力周波数１１がループ周波数３１よシ１　’Ｏ
ｋＨｚ低くなシ、出力３１はキャリアに対してＵＳＢの
関係となる。この場合はＬＳＢ　線消去されるが、用途
によってはＬＳＢを利用することもある。However, in SSM communication, the modulation frequency is approximately 30
0 to 3,000 Hz, whereas in the embodiment of the present invention, 10 to 10,0 (10 Hs) is required, so there is a problem with carrier suppression. The principle is 88B.
It is always explained in detail in the manual, so I will briefly explain it.
The input carrier 11 is phase-shifted by +45° and -45° by the high-frequency phase shifter 32, resulting in B M (balanced modulator) 1
In addition to (,L3) and 8M2 (34), the firing frequency 21 is phase shifted by +45° and -45° by the low frequency phase shifter 35, and in addition to BMI and 8M2, balanced modulation is performed, respectively. , 33 and 34 are combined by the output transformer 36 (single length can also be used), and the EBB output 31 is output to the secondary side.
BMI of one phase shifter and 8M2
By reversing the connection to the USB or LS
B can also be set arbitrarily. In Figure 3,
The loop frequency 31 is the frequency input to the splitter 4, and the splitting ratio is 10 if the reference frequency is 10 kHz.
Fixed frequency in kHz x N (31MH in the case of Figure 4)
z). The oscillation frequency 11 of the VCO needs to change by -10kHz (30,99'1M*), so when the modulation frequency 21 is 10kHz, the VC
The output frequency 11 of O1 is higher than the loop frequency 31 'O
When the kHz is low, the output 31 has a USB relationship to the carrier. In this case, the LSB line is erased, but the LSB may be used depending on the purpose.

位相シフト方式のポイントは移相器の性能によ如決まる
ので、キャリア周波数が高過ぎる場合は前置分局器を設
けて周波数を低下してもよい。また移相器は通常ＣＲ回
路網構成であるが、デジタル移相方式によシ精度を向上
することが可能である。The point of the phase shift method depends on the performance of the phase shifter, so if the carrier frequency is too high, a pre-distributor may be provided to lower the frequency. Further, although the phase shifter normally has a CR circuit network configuration, it is possible to improve the accuracy by using a digital phase shift method.

）　　　　　　　〔他の実施例〕 前に本発明の適用目的にはキャリア周波数とループ周波
数が近接するためフィルタ方式ＳＯＢ発生器で拉困難で
あるとしたが、次にフィルタ方式に適する本発明の実施
例につき述べる。) [Other Embodiments] Previously, it was stated that the purpose of application of the present invention is that it is difficult to use a filter-type SOB generator because the carrier frequency and loop frequency are close to each other. I will explain about this.

第５図はフィルタ方式ＳＯＢ発生器を用いた本発明の実
施回路例である。３はＳＯＢ発生器であって、キャリア
１１をＢＭ３７’に偏移周波数２１で平衡変調し、その
出力中よシ所望の側帯波のみをフィルタ３８で分離して
取出すのであるが、ここでは偏移量・波数に周波数α（
この場合は基準周波数と等しい１０　ｋＨｚ　）を加え
て入力する。従ってループ周波数３９は基準周波数（１
０ｋＨｚ　）　Ｘ分周比（Ｎ）であるべきものが、１０
　ｋＨｚ　Ｘ　（Ｎ　＋　１　）となシ、偏移量ゼロで
既に１０　ｋＨｚの周波数差があシ、偏移に従って２０
　ｋＨｚ　ｔで離れてゆくので°あるから、ループ周波
数を中心とする比較的簡単なフィルタでＵＳＢのシング
ルトーン３９を取シ出すことが容易にできることは第６
図から明らかである。ただし、分局器４拡本来の分局比
Ｎを（Ｎ十１）とすることによシ、その他の回路の動作
は従来と全く同一である。FIG. 5 is an example of an implementation circuit of the present invention using a filter type SOB generator. 3 is an SOB generator, which performs balanced modulation on the carrier 11 to BM 37' at a shift frequency 21, and extracts only the desired sideband from the output by separating it with a filter 38; Frequency α (
In this case, 10 kHz, which is equal to the reference frequency, is added and input. Therefore, the loop frequency 39 is the reference frequency (1
0kHz) What should be the X frequency division ratio (N) is 10
kHz
The sixth point is that it is easy to extract the USB single tone 39 with a relatively simple filter centered around the loop frequency.
It is clear from the figure. However, the operation of the other circuits is exactly the same as the conventional one except that the division ratio N of the expansion part of the divider 4 is set to (N11).

周波数の表示は前の実施例では偏移発振器２の発振周波
数直読でありたが、本例でｆｉ　１０　ｋＨｚを差引い
て読む仁とになる。また、ＣＢ発振器としてＩｄ、　１
０　Ｈｚ−１０ｋＨｚよシも１０〜２−ＯｋＨｚ−の方
が製作が容易である。In the previous embodiment, the frequency was directly read as the oscillation frequency of the shift oscillator 2, but in this example, it is read after subtracting fi 10 kHz. Also, as a CB oscillator, Id, 1
It is easier to manufacture a frequency of 10 to 2 kHz than a frequency of 0 Hz to 10 kHz.

１Ｍ３７やフィルタ３８の都合で周波数を低下させたい
場合は前値分局器を使用し得ることは前例と同じである
◎ 〔発明の効果ゴ ＰＬＬ発振器の発−周波数を細かく変化する方法は従来
技術でも何種類もの方法があるが、受信機の局部発振器
としてスプリアスを含まず、Ｃ／Ｎ良、好でロックアツ
プタイムの短かいという条件を満足するためには複雑な
回路構成が必要でＴｏ−）−た。If you want to lower the frequency due to the 1M37 or filter 38, you can use the pre-value splitter as in the previous example. ◎ [Effects of the invention] The method of finely changing the oscillation frequency of the PLL oscillator is also available in the prior art. There are many methods, but in order to satisfy the requirements that the receiver's local oscillator does not contain spurious signals, has good C/N, and has a short lock-up time, a complex circuit configuration is required. -ta.

本発明は発振周波数の偏移設定のためにループ周波数の
分局比を変えることなく、またループ内にミクサを用い
ることも無いので、スプリアス発生の危険性が少なく、
基準周波数も高くて良いのでいおよび口、クアッグタイ
ムの点でも有利な４１Ｆ徴がある。その回路構成におい
ても実施例に見られるように極めて簡素でＴｏ−ｖて、
シングル・イズ・ペストを実現できる効果がある。The present invention does not change the division ratio of the loop frequency to set the deviation of the oscillation frequency, and does not use a mixer in the loop, so there is less risk of spurious generation.
Since the reference frequency may be high, there is a 41F characteristic that is advantageous in terms of sound, sound, and quag time. The circuit configuration is extremely simple as seen in the examples, and
It has the effect of making single is the plague a reality.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の基本構成図、第２図は本発明の実施回
路構成例、第３図は第２図回路の動作説明図、第４図は
本発明を適用する受信機回路構成例、第５図は本発明の
他の実施例、第６図は第５図回路の動作説明図である。 １・・・ＶＣｏ、２・・・偏移周波数発振器、互・・・
８８Ｂ発生回路、４・・・分周器、５・・・基準周波数
、６・・・位相比較器、７・・・ＬＰＦ、３２・・・高
周波移相器、３３゜３４．３７・・・平衡変調器、３８
・・・フィルタ。 特許出願人　　八重洲無線株式会社 第　　２　　図 第　　３　図FIG. 1 is a basic configuration diagram of the present invention, FIG. 2 is an example of an implementation circuit configuration of the present invention, FIG. 3 is an explanatory diagram of the operation of the circuit shown in FIG. 2, and FIG. 4 is an example of a receiver circuit configuration to which the present invention is applied. , FIG. 5 is another embodiment of the present invention, and FIG. 6 is an explanatory diagram of the operation of the circuit shown in FIG. 1... VCo, 2... Deviation frequency oscillator, mutual...
88B generation circuit, 4... Frequency divider, 5... Reference frequency, 6... Phase comparator, 7... LPF, 32... High frequency phase shifter, 33° 34.37... Balanced modulator, 38
···filter. Patent applicant Yaesu Musen Co., Ltd. Figure 2 Figure 3

Claims (1)

【特許請求の範囲】[Claims] 電圧制御発振器の出力周波数をキャリアとして、周波数
偏移すべき周波数にて単側帯波変調したシングルトーン
周波数を分周して基準周波数と位相比較することにより
、位相比較器の出力する制御出力を該電圧制御発振器に
加えて発振周波数を制御することを特徴とする、位相同
期発振回路By using the output frequency of the voltage controlled oscillator as a carrier and dividing the single tone frequency that is single-sideband modulated at the frequency to be shifted and comparing the phase with the reference frequency, the control output output from the phase comparator can be adjusted to the desired value. A phase-locked oscillator circuit that is characterized by controlling the oscillation frequency in addition to being a voltage-controlled oscillator.