JPS614265A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS614265A
JPS614265A JP59125763A JP12576384A JPS614265A JP S614265 A JPS614265 A JP S614265A JP 59125763 A JP59125763 A JP 59125763A JP 12576384 A JP12576384 A JP 12576384A JP S614265 A JPS614265 A JP S614265A
Authority
JP
Japan
Prior art keywords
oxide film
semiconductor substrate
semiconductor
wiring conductor
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59125763A
Other languages
Japanese (ja)
Other versions
JPH0345898B2 (en
Inventor
Kiyoshi Nishimura
清 西村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP59125763A priority Critical patent/JPS614265A/en
Publication of JPS614265A publication Critical patent/JPS614265A/en
Publication of JPH0345898B2 publication Critical patent/JPH0345898B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To decrease electrostatic capacity between a wiring conductor and a semiconductor substrate, to prevent damage of an oxide film at the time of bonding and to enhance adhering strength of the wiring conductor, by providing a polycrystalline insulating layer on the surface of the oxide film, and arranging the connecting part for wire bonding. CONSTITUTION:For example, N-channel and P-channel transistors are formed in a semiconductor integrated circuit. In this circuit, semiconductor regions 22 and 24 having the reverse conducting type with respect to a semiconductor substrate 20 are formed on the surface layer of the semiconductor substrate 20. The regions are coated by an oxide film 26. At a part, where N- and P-channel transistors 28 and 30 are to be formed, and at the oxide film 26 covering the semiconductor region 24 on the surface layer of the semiconductor substrate 20, polysilicon layers 40, 42 and 44 are provided as polycrystalline insulating layers. They are simultaneously formed in manufacturing. Owing to the resistance property, resilient property and high adherence property with the oxide film and a wiring conductor provided in the polycrystalline insulating layer, electrostatic capacity between the connecting part and the semiconductor substrate is decreased. The damage of the oxide film due to the shock of wire bonding is prevented. The bonding strength between the connecting part and the oxide film is enhanced.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、半導体集積回路装置のポンディングパッド
の構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a structure of a bonding pad of a semiconductor integrated circuit device.

〔従来の技術〕[Conventional technology]

従来、Ｃ−ＭＯ３１，Ｃなどの半導体集積回路装置では
、第３図および第４図に示すように、半導体基板２の表
面層に半導体基板２とは反対導電形の半導体領域４が形
成されており、この半導体領域４を覆って酸化膜（たと
えばＳｉｎ、膜）６が形成され、その表面にアルミニウ
ムなどの配線導体８が設置されている。Conventionally, in semiconductor integrated circuit devices such as C-MO31, C, as shown in FIGS. 3 and 4, a semiconductor region 4 of a conductivity type opposite to that of the semiconductor substrate 2 is formed in the surface layer of the semiconductor substrate 2. An oxide film (for example, a Sin film) 6 is formed covering the semiconductor region 4, and a wiring conductor 8 made of aluminum or the like is provided on the surface of the oxide film 6.

この配線導体８は絶縁層１０で覆われており、この配線
導体８と一体的にボンディング用パッド部１２が形成さ
れている。１４は絶縁層１０に形成された開口である。This wiring conductor 8 is covered with an insulating layer 10, and a bonding pad portion 12 is formed integrally with this wiring conductor 8. 14 is an opening formed in the insulating layer 10.

ボンディング用パッド部？には、図示していないピンを
電気的に接続するための金線などの導電性ワイ′＋１１
６が溶着されている。Bonding pad part? Conductive wires such as gold wires are used to electrically connect pins (not shown).
6 is welded.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

このようなポンディングパッド構造では、次のような問
題点がある。Such a bonding pad structure has the following problems.

■　配線導体８と半導体領域４との間の静電容量、ある
いは配線導体８と半導体基板２との間の静電容量が、半
導体集積回路の入出力部の寄生容量として作用−する。(2) The capacitance between the wiring conductor 8 and the semiconductor region 4 or the capacitance between the wiring conductor 8 and the semiconductor substrate 2 acts as a parasitic capacitance at the input/output portion of the semiconductor integrated circuit.

■　酸化膜６の表面に水分などの不純物が存在している
場合、酸化膜６と配線導体８との接合強度が低下するお
それがある。(2) If impurities such as moisture are present on the surface of the oxide film 6, the bonding strength between the oxide film 6 and the wiring conductor 8 may be reduced.

■　酸化膜６は非常に硬く、ワイヤボンディング時の衝
撃によって破損し、半導体基板２との絶縁性が低下する
おそれがある。(2) The oxide film 6 is very hard and may be damaged by impact during wire bonding, resulting in a decrease in insulation with the semiconductor substrate 2.

この発明は、このような不都合を除き、配線導体と半導
体基板との間の静電容量を低下させるとともに、ワイヤ
ボンディング時の衝撃による酸化膜の破損を防止し、さ
らに、配線導体の密着強度を高めようとするものである
。The present invention eliminates these disadvantages, reduces the capacitance between the wiring conductor and the semiconductor substrate, prevents damage to the oxide film due to impact during wire bonding, and further improves the adhesion strength of the wiring conductor. It is intended to increase.

〔問題点を解決するための手段〕[Means for solving problems]

この発明は、半導体基板の表面に設置された酸化膜の表
面に、多結晶絶縁層を介在させてワイヤボンディング用
接続部を設置したものである。In this invention, a connection portion for wire bonding is provided on the surface of an oxide film provided on the surface of a semiconductor substrate with a polycrystalline insulating layer interposed therebetween.

〔作　用〕[For production]

酸化膜の表面にポリシリコンなどの多結晶絶縁層を介在
させて配線導体を設置することにより、多結晶絶縁層が
有する抵抗性、弾力性、酸化膜や配線導体との高い密着
性などの特性を活用する。By installing a wiring conductor on the surface of an oxide film with a polycrystalline insulating layer such as polysilicon, the properties of the polycrystalline insulating layer such as resistance, elasticity, and high adhesion with the oxide film and the wiring conductor can be improved. Make use of it.

〔実施例〕〔Example〕

以下、この発明を図面に示した実施例を参照し−で詳細
に説明する。Hereinafter, the present invention will be described in detail with reference to embodiments shown in the drawings.

第１図はこの発明の半導体集積回路装置の実施例を示し
、この実施例はＮチャンネルおよびＰチャンネルトラン
ジスタを形成した半導体集積回路について示したもので
ある。FIG. 1 shows an embodiment of a semiconductor integrated circuit device of the present invention, and this embodiment shows a semiconductor integrated circuit in which N-channel and P-channel transistors are formed.

Ｎ形半導体またはＰ形半導体で形成された半導体基板２
０の表面層には、半導体基板２０とは反対導電形の半導
体領域２２．２４が形成されているとともに、酸化膜２
６で覆われてい、る。Semiconductor substrate 2 formed of an N-type semiconductor or a P-type semiconductor
A semiconductor region 22.24 having a conductivity type opposite to that of the semiconductor substrate 20 is formed in the surface layer of the semiconductor substrate 20, and an oxide film 22.
Covered by 6.

そして、半導体基板２０の表面層には、Ｎチャンネルト
ランジスタ２８およびＰチャンネルトランジスタ３０が
形成されている。すなわち、酸化ＷＡ２６に選択的に開
口を形成し、半導体基板２０とは反対導電形の半導体領
域３２．３４を形成するとともに、半導体領域２２には
半導体基板２０と同−導電形の半導体領域３６．３８が
Ｐ形不純物またはＮ形不純物の拡散によって形成されて
いる。An N-channel transistor 28 and a P-channel transistor 30 are formed on the surface layer of the semiconductor substrate 20. That is, openings are selectively formed in the oxidized WA 26 to form semiconductor regions 32 . 34 of the opposite conductivity type to that of the semiconductor substrate 20 , and semiconductor regions 36 . 38 is formed by diffusion of P-type impurities or N-type impurities.

また、各トランジスタ２８．３０のゲート形成部分およ
び半導体領域２４を覆う酸化膜２６の部分には、多結晶
絶縁層としてのポリシリコン層４０．４２．４４がそれ
ぞれ設置され、これらは製造上、同時に形成する。In addition, polysilicon layers 40, 42, and 44 as polycrystalline insulating layers are respectively provided on the gate forming portion of each transistor 28, 30 and the portion of the oxide film 26 that covers the semiconductor region 24. Form.

ポリシリコン層４０の上面にはトランジスタ２８のゲー
ト４６、ま゛た、ポリシリコン層４２の上面にはトラン
ジスタ３０のゲート４８がアルミニウムなどで形成され
るとともに、半導体領域３２には配線導体５０、半導体
領域３４．３６を接続する配線導体５２、半導体領域３
８には配線導体５４、ポリシリコン層４４を覆う位置に
はボンディング用接続部５６が形成される。接続部５６
は、各トランジスタ２８．３０の共通のゲート用パッド
を形成している。A gate 46 of a transistor 28 is formed on the upper surface of the polysilicon layer 40, and a gate 48 of a transistor 30 is formed of aluminum or the like on the upper surface of the polysilicon layer 42, and a wiring conductor 50 and a semiconductor are formed on the semiconductor region 32. Wiring conductor 52 connecting regions 34 and 36, semiconductor region 3
A wiring conductor 54 is formed at 8, and a bonding connection portion 56 is formed at a position covering the polysilicon layer 44. Connection part 56
forms a common gate pad for each transistor 28,30.

各ゲート４６．４８は、破線５８で示す配線導体によっ
て電気的に接続されているとともに、その上面部は絶縁
層６０で被覆されている。Each gate 46, 48 is electrically connected by a wiring conductor indicated by a broken line 58, and its upper surface portion is covered with an insulating layer 60.

そして１、絶縁層６０のポリシリコン層４４を覆う部分
に開口６２が形成され、ワイヤボンディング用接続部５
Ｇの表面が露出している。この接続部５６には、ビンと
の間を電気的に接続するための導電性ワイヤ６６が溶接
により固着されている。1. An opening 62 is formed in a portion of the insulating layer 60 that covers the polysilicon layer 44, and a connecting portion 5 for wire bonding is formed.
The surface of G is exposed. A conductive wire 66 for electrically connecting to the bottle is fixed to this connecting portion 56 by welding.

このように構成すれば、導電性ワイヤ６６を接続する接
続部５６と酸化膜２６との間に、ポリシリコン層４４に
よる抵抗体が設置される。このため、ポリシリコン層４
４を設置しない場合には、第２図の（Ａ）に示すように
、接続部５６と半導体領域２４との間に、酸化膜２６に
よる静電容量Ｃのみが作用するのに対して、ポリシリコ
ン層４４を設置した場合には、第２図の（Ｂ）に示すよ
うに、接続部５６と半導体領域２４との間に、酸化膜２
６による静電容量Ｃに直列にポリシリコン層４４による
抵抗体Ｒが作用し、通常のシリコンゲートＭＯＳトラン
ジスタにおいて、寄生容量の低減を図ることができる。With this configuration, a resistor made of the polysilicon layer 44 is installed between the connection portion 56 that connects the conductive wire 66 and the oxide film 26. Therefore, the polysilicon layer 4
4, as shown in FIG. When the silicon layer 44 is provided, an oxide film 2 is formed between the connection portion 56 and the semiconductor region 24, as shown in FIG.
A resistor R formed by the polysilicon layer 44 acts in series with the capacitance C formed by the capacitor 6, and it is possible to reduce the parasitic capacitance in a normal silicon gate MOS transistor.

ポリシリコン層４４をポリシリコンで形成する場合、ゲ
ート４６．４８の部分に設置するポリシリコン層と同時
に設置でき、特別な工程を必要としない。When the polysilicon layer 44 is formed of polysilicon, it can be formed at the same time as the polysilicon layer placed on the gates 46 and 48, and no special process is required.

また、ポリシリコン層４４は酸化膜２６を構成する酸化
シリコン（Ｓ　ｉ　Ｏｚ　）膜より弾力性に冨み、導電
性ワイヤ６６のボンディング時、その衝撃から酸化膜２
６を保護する緩衝体として機能し、酸化膜２６のクラン
キングなどの破損を防止できる。Further, the polysilicon layer 44 has more elasticity than the silicon oxide (S iOz ) film constituting the oxide film 26, and when the conductive wire 66 is bonded, the oxide film 2 is damaged by the impact.
6, and can prevent damage to the oxide film 26 due to cranking.

しかも、このようなポリシリコン層４４が設置された場
合、接続部５６−ポリシリコン層４４−酸化膜２６の層
構造となり、ポリシリコン層４４を設置しないで接続部
５６−酸化膜２６を接合した場合に比較してそれぞれの
密着性を高めることができるので、接続部５６を強固に
設置することができる。特に、接続部５６がアルミニウ
ム、酸化膜２Ｇが酸化シリコン膜である場合、アルミニ
ウムとポリシリコンとの接合はアロイ構造となり、その
密着性が高く、ポリシリコンと酸化シリコンは同種のも
のであり、その密着性は高くなる。Moreover, when such a polysilicon layer 44 is installed, the layer structure becomes a connection part 56 - polysilicon layer 44 - oxide film 26, and it is possible to bond the connection part 56 - oxide film 26 without providing the polysilicon layer 44. Since the adhesion of each can be improved compared to the case where the connecting portion 56 is firmly installed. In particular, when the connecting portion 56 is aluminum and the oxide film 2G is a silicon oxide film, the bond between aluminum and polysilicon has an alloy structure, and its adhesion is high, and polysilicon and silicon oxide are of the same type, and their Adhesion becomes higher.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、この発明によれば、次のような効
果が得られる。As explained above, according to the present invention, the following effects can be obtained.

■　多結晶絶縁層は抵抗体であるため、接続部−と半導
体基板間の静電容量に抵抗体を直列に接続したこととな
り、寄生容量を低減できる。(2) Since the polycrystalline insulating layer is a resistor, a resistor is connected in series to the capacitance between the connecting portion and the semiconductor substrate, and parasitic capacitance can be reduced.

■　多結晶絶縁層は、ワイヤボンディングの衝撃に対し
て緩衝体として機能し、ワイヤボンディングの衝撃によ
る酸化膜の破損を防止でき、接続部と半導体基板間の短
絡などの不都合を防止できる。(2) The polycrystalline insulating layer functions as a buffer against the impact of wire bonding, can prevent damage to the oxide film due to the impact of wire bonding, and can prevent problems such as short circuits between the connection part and the semiconductor substrate.

■　接続部と酸化膜との間に多結晶ｗＡ縁層を介在させ
ることにより、接続部と酸化膜との間の結合強度を高め
ることができる。(2) By interposing the polycrystalline WA edge layer between the connection part and the oxide film, the bonding strength between the connection part and the oxide film can be increased.

【図面の簡単な説明】[Brief explanation of drawings]

第１図はこの発明の半導体集積回路装置の実施例を示す
断面図、第２図は多結晶絶縁層の機能を示す説明図、第
３図は従来の半導体集積回路装置におけるボンディング
バンド部を示す平面図、第４図は第３図のＩＶ−■線に
沿う断面図である。 ２０・・・半導体基板、４４・・・多結晶絶縁層として
のポリシリコン層、５Ｇ・・・ボンディング用接続部、
６Ｇ・・・導電性ワイヤ。FIG. 1 is a sectional view showing an embodiment of a semiconductor integrated circuit device of the present invention, FIG. 2 is an explanatory diagram showing the function of a polycrystalline insulating layer, and FIG. 3 is a bonding band portion in a conventional semiconductor integrated circuit device. The plan view and FIG. 4 are sectional views taken along the line IV-■ in FIG. 3. 20... Semiconductor substrate, 44... Polysilicon layer as a polycrystalline insulating layer, 5G... Bonding connection part,
6G... Conductive wire.

Claims (2)

【特許請求の範囲】[Claims] （１）半導体基板の表面に設置された酸化膜の表面に、
多結晶絶縁層を介在させてワイヤボンディング用接続部
を設置した半導体集積回路装置。(1) On the surface of the oxide film installed on the surface of the semiconductor substrate,
A semiconductor integrated circuit device in which a wire bonding connection part is installed with a polycrystalline insulating layer interposed therebetween. （２）前記酸化膜はシリコン酸化膜で構成し、前記多結
晶絶縁層はポリシリコンで構成した特許請求の範囲第１
項に記載の半導体集積回路装置。(2) The oxide film is made of a silicon oxide film, and the polycrystalline insulating layer is made of polysilicon.
2. The semiconductor integrated circuit device described in 2.
JP59125763A 1984-06-19 1984-06-19 Semiconductor integrated circuit device Granted JPS614265A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59125763A JPS614265A (en) 1984-06-19 1984-06-19 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59125763A JPS614265A (en) 1984-06-19 1984-06-19 Semiconductor integrated circuit device

Publications (2)

Publication Number Publication Date
JPS614265A true JPS614265A (en) 1986-01-10
JPH0345898B2 JPH0345898B2 (en) 1991-07-12

Family

ID=14918216

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59125763A Granted JPS614265A (en) 1984-06-19 1984-06-19 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS614265A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56161923A (en) * 1980-05-06 1981-12-12 Ushio Electric Inc Sterilizer for film
JP2008168518A (en) * 2007-01-12 2008-07-24 Advanced Telecommunication Research Institute International Reminder apparatus

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5039470A (en) * 1973-08-09 1975-04-11
JPS5239378A (en) * 1975-09-23 1977-03-26 Seiko Epson Corp Silicon-gated mos type semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5039470A (en) * 1973-08-09 1975-04-11
JPS5239378A (en) * 1975-09-23 1977-03-26 Seiko Epson Corp Silicon-gated mos type semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56161923A (en) * 1980-05-06 1981-12-12 Ushio Electric Inc Sterilizer for film
JP2008168518A (en) * 2007-01-12 2008-07-24 Advanced Telecommunication Research Institute International Reminder apparatus

Also Published As

Publication number Publication date
JPH0345898B2 (en) 1991-07-12

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