JPS614249A - Package for semiconductor device - Google Patents

Package for semiconductor device

Info

Publication number
JPS614249A
JPS614249A JP59126063A JP12606384A JPS614249A JP S614249 A JPS614249 A JP S614249A JP 59126063 A JP59126063 A JP 59126063A JP 12606384 A JP12606384 A JP 12606384A JP S614249 A JPS614249 A JP S614249A
Authority
JP
Japan
Prior art keywords
package
semiconductor
radiation
alloy material
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59126063A
Other languages
Japanese (ja)
Inventor
Nobuo Ogasa
小笠　伸夫
Kazuhito Murakami
村上　一仁
Akira Otsuka
昭 大塚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP59126063A priority Critical patent/JPS614249A/en
Publication of JPS614249A publication Critical patent/JPS614249A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Ceramic Products (AREA)

Abstract

PURPOSE:To obtain a semiconductor device having excellent radiation resisting property and high sealing reliability, by using Cu-W alloy including W at a speccified rate as a tightly sealing material for a ceramic package. CONSTITUTION:Cu-W alloy materials 3 and 3 including 80-95wt% W are bonded to both upper and lower surfaces of a ceramic package 2. By said alloy material layers, radiation to a semiconductor element from the outside can be shielded.

Description

【発明の詳細な説明】 （１）産業上の利用分野 この発明は半導体装置内に搭載した半導体素子が放射線
の照射、貫通によって異常動作（誤動作）することを防
止した耐放射線性にすぐれた構造の半導体装置用パッケ
ージに関するものである。Detailed Description of the Invention (1) Industrial Application Field This invention provides a structure with excellent radiation resistance that prevents abnormal operation (malfunction) of semiconductor elements mounted in a semiconductor device due to irradiation or penetration of radiation. The present invention relates to a package for a semiconductor device.

（２）従来の技術 周知のように、マイクロコンピュータやメモリ等の半導
体回路素子はＰＮＰやＮＰＮ回路が複雑に配置されてお
り、結果的にＰＮＰＮ接合サイリスタ回路が構成される
ことがある。(2) Conventional Technology As is well known, semiconductor circuit elements such as microcomputers and memories have PNP and NPN circuits arranged in a complicated manner, and as a result, a PNPN junction thyristor circuit may be constructed.

この種の回路は中間のＮＰ接合のＮ側に正電位、Ｐ側に
負電位が印加されてキャリア空乏層が形成され、電気的
に非導通状態となっているため、通常動作中は問題とな
らない設計となっている。In this type of circuit, a positive potential is applied to the N side of the intermediate NP junction and a negative potential is applied to the P side, forming a carrier depletion layer and making it electrically non-conductive, which causes problems during normal operation. The design is such that it will not occur.

ところで、上記サイリスタ回路部分に宇宙線等の放射線
が貫通し、空乏層に電子、正孔対が多数創成されると、
これらのキャリアによりＰＮＰＮ接合部がサイリスク回
路として導通状態となり、回路がショートしてしまうこ
とがある。By the way, when radiation such as cosmic rays penetrates the thyristor circuit part and many pairs of electrons and holes are created in the depletion layer,
These carriers may cause the PNPN junction to become conductive as a silicon risk circuit, resulting in a short circuit.

またγ線やＸ線のような電離性放射線が入射すると、光
電効果やコンプトン効果などにより、Ｓｉ　　　’や絶
縁膜中に正孔と電子の正負荷電荷を発生させるほか、Ｓ
Ｌと５Ｌｏｅ膜の界面に放射線照射による界面単位が発
生するなど半導体素子の誤動作要因となるのである。Furthermore, when ionizing radiation such as γ-rays and
This can cause malfunctions of semiconductor devices, such as the generation of interface units at the interface between the L and 5Loe films due to radiation irradiation.

さらにＳＬデバイスへ局所的にα粒子やプロトンなどが
入射すると、その入射線に沿って電子−正孔対が生成さ
れ、一過性の誤動作が生じる。Furthermore, when alpha particles, protons, etc. are locally incident on the SL device, electron-hole pairs are generated along the line of incidence, causing temporary malfunction.

（３）発明が解決しようとする問題点 上記のように半導体素子によって放射線による損傷は大
きな問題で、今後ますます需要が増大するものと予想さ
れる宇宙空間、原子炉周辺で使用される半導体デバイス
にとって、耐放剣線の向上は、重要な技術課題といえる
。(3) Problems that the invention aims to solve As mentioned above, damage caused by radiation to semiconductor devices is a major problem, and the demand for semiconductor devices used in outer space and around nuclear reactors is expected to increase even more in the future. For this reason, improving the anti-sword line is an important technical issue.

このための方策として、これまでも半導体回路素子に対
策を加える方法や、デバイス全体を円やＷなどの高比重
材で被覆してしまうなどの検問が行われてきた。To this end, measures have been taken to date, such as adding countermeasures to semiconductor circuit elements and covering the entire device with a high-density material such as a circle or W.

しかしながら、前者の方法は当然のことながら半導体回
路そのものの設計、製造を複雑にし、特に高密度、高速
素子ではそれによる制約が大きい。However, the former method naturally complicates the design and manufacture of the semiconductor circuit itself, and is particularly restrictive for high-density, high-speed devices.

一方接者の方法は、半導体デバイス全体が大型化し、重
量も大きくなるなどの問題点を有している。On the other hand, the contact method has problems such as increasing the size and weight of the entire semiconductor device.

また、パッケージにｈやＷの如き材料を接合することは
、セラミックパッケージの主体部を構成するＮ、０．と
の熱膨張係数の不整合が大きいために困難である。In addition, bonding materials such as h and W to the package also makes it possible to bond materials such as h and tungsten to the package. This is difficult due to the large mismatch in thermal expansion coefficient with

（４）問題点を解決するための手段 この発明は上記の点に鑑みてなされたものでその目的と
するところは、放射線の照射さら、には貫通による半導
体素子の誤動作を防止すべく該半導体素子を搭載したパ
ッケージの改良をはかったものである。(4) Means for Solving the Problems This invention has been made in view of the above points, and its purpose is to prevent malfunctions of semiconductor elements due to radiation irradiation and even penetration. This is an attempt to improve the package in which the device is mounted.

即ち、この発明は半導体素子を搭載したセラミックパッ
ケージの下面と搭載半導体素子の上面にＷを８０〜９５
重量％含有するＣＩＬ−Ｗ合金材料を接合したことを特
徴とするものである。That is, the present invention provides W of 80 to 95 W on the lower surface of the ceramic package on which the semiconductor element is mounted and the upper surface of the mounted semiconductor element.
It is characterized by joining a CIL-W alloy material containing % by weight.

そして、これによって耐放射線性を著しく改善すること
が可能となったのである。This made it possible to significantly improve radiation resistance.

即ち、この発明を図面について説明すると、第１図にお
いて、１は半導体素子、２は積層セラミック材料よりな
るパッケージ、４はボンディングワイヤー、５はリード
線である。That is, the present invention will be explained with reference to the drawings. In FIG. 1, 1 is a semiconductor element, 2 is a package made of a laminated ceramic material, 4 is a bonding wire, and 5 is a lead wire.

そしてこの発明はセラミックパッケージ２の上下両面に
Ｗを８０〜９５重間％含有するｃｔｔ−ｗ合金材料３，
３を接合させたことが特徴であり、この合金材料層によ
って外界から半導体素子にまで至る放射線を遮蔽するこ
とができるのである。The present invention also includes a CTT-W alloy material 3 containing 80 to 95% W by weight on both the upper and lower surfaces of the ceramic package 2.
3 are bonded together, and this alloy material layer can shield radiation reaching the semiconductor element from the outside world.

（５）　　　作　　　用 ここでＣｕ−Ｗ合金材料におけるＷの■を８０〜９５重
量％と限定したのは、放射線遮蔽効果の面から比重を１
５．６＞Ｊ以上と大きくし、かつパッケージの主体をな
すセラミック（一般には／Ｖ　２０３が多く用いられる
）との熱膨張係数を近似させることにより、大型の遮蔽
板のパッケージ主体への取（＝ｔ　＆プを可能にすると
ともに、半導体素子の搭１ｔｌｉ組立後の熱サイクルに
よる信頼性低下をも防止するためである。(5) Effect The reason for limiting the amount of W in the Cu-W alloy material to 80 to 95% by weight is because the specific gravity is 1% from the viewpoint of radiation shielding effect.
By increasing the size to 5.6>J or more and approximating the coefficient of thermal expansion to the ceramic (generally /V 203 is often used) that forms the main body of the package, it is possible to attach a large shielding plate to the main body of the package ( This is to make it possible to reduce the temperature of the semiconductor element and to prevent a decrease in reliability due to thermal cycling after assembly of the semiconductor element.

ここでＣｕ−Ｗ合金材料を第１図のＪ：うにパッケージ
の上面および下面にのみ用いたのは、半導体素子搭載セ
ラミックパッケージの設計上、斜め方向からくる放射線
については、パッケージの主体をなすセラミック中での
透過距離が大きくなるため、比重の小さいセラミック材
料でも十分に放射線遮蔽効果が期待できるためである。The reason why the Cu-W alloy material was used only on the upper and lower surfaces of the package J in Figure 1 is because the ceramic package, which makes up the main body of the package, is This is because even a ceramic material with a small specific gravity can be expected to have a sufficient radiation shielding effect because the transmission distance inside the material is large.

なお、ここで用いるＣａ−Ｗ合金材料は、その効果より
Ｗと仮が夫々均一に分布していることが必要である。こ
のためには粉末冶金法によるのが最も好ましい。Note that the Ca--W alloy material used here requires that W and temporary be uniformly distributed in order to obtain the desired effect. Most preferably, powder metallurgy is used for this purpose.

なお、この発明で放射線の遮蔽を目的として用いるＷを
８０〜９５重量％含有するＣａ−Ｗ合金材料の形状につ
いては、半導体パッケージの全体設計に関連して、必ず
しも平板状のものを用いる必要はなく、各種の異形状の
ものを用いても差支えない。In addition, regarding the shape of the Ca-W alloy material containing 80 to 95% by weight of W used for the purpose of shielding radiation in this invention, it is not necessarily necessary to use a flat shape in relation to the overall design of the semiconductor package. There is no problem in using various shapes.

さらに、この発明のパッケージはシングルチップ型の積
層セラミックパッケージ、ガラス−セラミック封止型パ
ッケージ（ＣｅｒＤ　１ｔ））に適用できることは勿論
であるが、マルチツブ型のセラミックパッケージへの適
用も可能である。Furthermore, the package of the present invention can of course be applied to a single-chip type laminated ceramic package, a glass-ceramic sealed package (CerD 1t)), and can also be applied to a multitub type ceramic package.

また、この発明において、第１図はＣｕ−Ｗ合金材料を
半導体パッケージにおける上面の密閉封止用蓋材として
使用した例を示したが、上面での伍−Ｗ合金材料の使用
は、これに限定されるもので以上の結果からＷを８０〜
９５％含有するＣＬＬ−Ｗ合金をセラミックパッケージ
の密閉封止材として用いることにより耐放射峰性が良好
で、且つパッケージそのものの封止信頼性も良好な半導
体装置が得られることが認められた。In addition, in this invention, although FIG. 1 shows an example in which the Cu-W alloy material is used as a lid material for sealing the top surface of a semiconductor package, the use of the Go-W alloy material on the top surface is different from this. Based on the above results, W is limited to 80~
It has been found that by using a CLL-W alloy containing 95% as a hermetic sealing material for a ceramic package, a semiconductor device can be obtained which has good radiation resistance and also has good sealing reliability of the package itself.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図および第２図は８０〜９５％のＷを含有するＣｕ
−Ｗ合金材料を上、下面に接合したこの発明の実施例を
示す半導体パッケージの構造を示す断面図である。 １・・・半導体素子　　２，２′・・・セラミック材料
３・・・伍−Ｗ合金材料 ４・・・ボンディングワイヤ　　５・・・リード線特許
出願人　　住友電気工業株式会社 代　　理　　人　　　弁理士　　和　　１）　　昭第１
図 第２図Figures 1 and 2 show Cu containing 80-95% W.
1 is a cross-sectional view showing the structure of a semiconductor package showing an embodiment of the present invention in which -W alloy material is bonded to the upper and lower surfaces. 1... Semiconductor element 2, 2'... Ceramic material 3... 5-W alloy material 4... Bonding wire 5... Lead wire patent applicant Sumitomo Electric Industries Co., Ltd. Representative Patent attorney Kazu 1) Showa 1st
Figure 2

Claims (2)

【特許請求の範囲】[Claims] （１）半導体素子を搭載したセラミックパッケージにお
いて、該セラミックパッケージの下面と搭載半導体素子
の上面にＷを８０〜９５重量％含有するＣｕ−Ｗ合金材
料を接合したことを特徴とする耐放射線性にすぐれた半
導体装置用パッケージ。(1) In a ceramic package mounted with a semiconductor element, radiation resistance characterized by bonding a Cu-W alloy material containing 80 to 95% by weight of W to the lower surface of the ceramic package and the upper surface of the mounted semiconductor element. Excellent package for semiconductor devices. （２）Ｗを８０〜９５重量％含有するＣｕ−Ｗ合金材料
による搭載半導体素子上面への接合は、これを密閉封止
材料としてのセラミック材料を介して行なうことを特徴
とする特許請求の範囲第１項記載の耐放射線性にすぐれ
た半導体装置用パッケージ。(2) A claim characterized in that the Cu-W alloy material containing 80 to 95% by weight of W is bonded to the upper surface of the mounted semiconductor element through a ceramic material as a hermetic sealing material. 1. The package for a semiconductor device having excellent radiation resistance as described in item 1.
JP59126063A 1984-06-19 1984-06-19 Package for semiconductor device Pending JPS614249A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59126063A JPS614249A (en) 1984-06-19 1984-06-19 Package for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59126063A JPS614249A (en) 1984-06-19 1984-06-19 Package for semiconductor device

Publications (1)

Publication Number Publication Date
JPS614249A true JPS614249A (en) 1986-01-10

Family

ID=14925705

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59126063A Pending JPS614249A (en) 1984-06-19 1984-06-19 Package for semiconductor device

Country Status (1)

Country Link
JP (1) JPS614249A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996022669A2 (en) * 1995-01-13 1996-07-25 Space Electronics, Inc. Radiation shielding of integrated circuits and multi-chip modules in ceramic and metal packages
US6261508B1 (en) 1994-04-01 2001-07-17 Maxwell Electronic Components Group, Inc. Method for making a shielding composition
US6262362B1 (en) 1994-04-01 2001-07-17 Maxwell Electronic Components Group, Inc. Radiation shielding of three dimensional multi-chip modules
US6368899B1 (en) 2000-03-08 2002-04-09 Maxwell Electronic Components Group, Inc. Electronic device packaging
US6455864B1 (en) 1994-04-01 2002-09-24 Maxwell Electronic Components Group, Inc. Methods and compositions for ionizing radiation shielding
US6613978B2 (en) 1993-06-18 2003-09-02 Maxwell Technologies, Inc. Radiation shielding of three dimensional multi-chip modules
US6720493B1 (en) 1994-04-01 2004-04-13 Space Electronics, Inc. Radiation shielding of integrated circuits and multi-chip modules in ceramic and metal packages
US7382043B2 (en) 2002-09-25 2008-06-03 Maxwell Technologies, Inc. Method and apparatus for shielding an integrated circuit from radiation
US7696610B2 (en) 2003-07-16 2010-04-13 Maxwell Technologies, Inc. Apparatus for shielding integrated circuit devices

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6858795B2 (en) 1993-06-18 2005-02-22 Maxwell Technologies, Inc. Radiation shielding of three dimensional multi-chip modules
US6613978B2 (en) 1993-06-18 2003-09-02 Maxwell Technologies, Inc. Radiation shielding of three dimensional multi-chip modules
US6455864B1 (en) 1994-04-01 2002-09-24 Maxwell Electronic Components Group, Inc. Methods and compositions for ionizing radiation shielding
US5635754A (en) * 1994-04-01 1997-06-03 Space Electronics, Inc. Radiation shielding of integrated circuits and multi-chip modules in ceramic and metal packages
US6720493B1 (en) 1994-04-01 2004-04-13 Space Electronics, Inc. Radiation shielding of integrated circuits and multi-chip modules in ceramic and metal packages
US6261508B1 (en) 1994-04-01 2001-07-17 Maxwell Electronic Components Group, Inc. Method for making a shielding composition
US6262362B1 (en) 1994-04-01 2001-07-17 Maxwell Electronic Components Group, Inc. Radiation shielding of three dimensional multi-chip modules
EP0803174A4 (en) * 1995-01-13 1999-05-06 Space Electronics Inc Radiation shielding of integrated circuits and multi-chip modules in ceramic and metal packages
WO1996022669A2 (en) * 1995-01-13 1996-07-25 Space Electronics, Inc. Radiation shielding of integrated circuits and multi-chip modules in ceramic and metal packages
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