JPS6139615A - Reference voltage generating circuit - Google Patents

Abstract

PURPOSE:To enable to obtain stable reference voltage without increasing electric power consumption for variation of load by connecting an operational amlifier having connected inversion input end with an output end to the output end of a reference power source. CONSTITUTION:As the inversion input terminal and output terminal 21 of the operational amplifier 22 are connected directly, gain of this operational amplifier 22 becomes 1, and voltage of non-inversion input appears in the output end 21. Further, as output impedance of the operational amplifier 22 is as low as less than 1, potential of the output end 21 does not change even when load of the operational amplifier 22 changes. Accordingly, by using this circuit as the reference voltage generating circuit of switched capacitor integrators 23, 24, stable reference voltage is supplied and characteristic of the integrators 23, 24 becomes stable. As stable reference voltage is obtained even if large electric current is not let flow in resistances 18, 19, it is suitable also for an integrated circuit.

Description

【発明の詳細な説明】 （産業上の利用分野） 本発明は基準電圧発生回路、特にスイッチド・キャパシ
タ積分器用の基準電圧発生回路に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a reference voltage generation circuit, and more particularly to a reference voltage generation circuit for a switched capacitor integrator.

（従来技術） 従来、電子フィルタ、音声認識回路、音声合成回路等に
はスイッチド・キャパシタ積分器が用いられる。(Prior Art) Switched capacitor integrators are conventionally used in electronic filters, speech recognition circuits, speech synthesis circuits, and the like.

第２図は従来のスイッチド・キャパシタ積分器の一例の
回路図である。FIG. 2 is a circuit diagram of an example of a conventional switched capacitor integrator.

第２図において、切換スイッチＳＷの第１接点２は入力
端子１に、第２接点３は演算増幅器７の反転入力端に、
共通接点４はキャパシタＣＩを介して基準電圧端６に接
続され、演算増幅器７の非反転入力端は基準電圧端６に
接続され、該演算増幅器７の反転入力端はキャパシタＣ
２を介して出力端５に接続される。In FIG. 2, the first contact 2 of the changeover switch SW is connected to the input terminal 1, and the second contact 3 is connected to the inverting input terminal of the operational amplifier 7.
The common contact 4 is connected to a reference voltage terminal 6 via a capacitor CI, the non-inverting input terminal of an operational amplifier 7 is connected to the reference voltage terminal 6, and the inverting input terminal of the operational amplifier 7 is connected to a capacitor C.
2 to the output end 5.

今、入力端１に電圧ｖ１が加えられ、前記スイッチＳＷ
が周期Ｔ秒で切換わり、ｔ＝ｎＴ秒でスイッチＳＷが接
点２側に倒れて、キャパシタＣ１を充電し、ｔ　＝　（
ｎ　＋　１　／　２　）　Ｔ秒で、スイッチＳＷが接点
３側に倒れるとＣ１の電荷はＣ２に転送され、スイッチ
ＳＷでサンプルされた出力電圧■２が出力端５に出力さ
れる。このときの伝達関数はキャパシタＣ１及びＣ２の
比で決まり、これをＺ変換で表わすと となる。Now, a voltage v1 is applied to the input terminal 1, and the switch SW
switches at a period of T seconds, and at t = nT seconds, the switch SW falls to the contact 2 side, charging the capacitor C1, and t = (
n + 1 / 2 ) T seconds, when the switch SW falls to the contact 3 side, the charge of C1 is transferred to C2, and the output voltage 2 sampled by the switch SW is output to the output terminal 5. The transfer function at this time is determined by the ratio of capacitors C1 and C2, and is expressed by Z transformation.

第３図（ａ）　、　（ｂ）は従来のスイッチド・キャパ
シタ積分器の他の例の回路図で、（ａ）図と（ｂ）図は
スイッチの切換わり状態を示す。FIGS. 3(a) and 3(b) are circuit diagrams of other examples of conventional switched capacitor integrators, and FIGS. 3(a) and 3(b) show the switching states of the switches.

スイッチド・キャパシタ積分器を半導体素子で構成した
場合、スイッチに寄生容量を生ずる。この寄生容量がス
イッチング速度などに影響することが判ってきたので、
寄生容量の影響を受けないスイッチド・キャパシタ積分
器として第３図（ａ）。When a switched capacitor integrator is constructed from a semiconductor element, a parasitic capacitance is generated in the switch. It has become clear that this parasitic capacitance affects switching speed, etc.
Figure 3(a) shows a switched capacitor integrator that is not affected by parasitic capacitance.

（ｂ）に示すものが考案されたのである。What is shown in (b) was devised.

第３図（ａ）において、ｔ　＝　ｎ　Ｔ秒でスイッチ８
Ｗ１゜ＳＷ２がそれぞれ接点９．接点１０に接続され、
入力端子８に電圧ｖ１が加えられると、キャパシタＣ１
及びＣ２を介し、演算増幅器１５により出力端１３にＣ
１，Ｃ２の比で決まる出力電圧Ｖ２が現われる。次にｔ
＝（ｎ＋１７２）Ｔ秒で、第３図（ｂ）に示すように、
スイッチｓｗ１．ｓｗ２はそれぞれ接点１１．接点１２
に接続され、Ｃ１に充電された電荷は基準電圧端１４に
放電されＣ２の電荷は保持される。このときスイッチの
寄生容量の電荷も同時に放電されｖｌよりｖ２への電荷
転送には何ら影響を及はさない。In Fig. 3(a), switch 8 is turned on at t = n T seconds.
W1 and SW2 are the contacts 9. connected to contact 10,
When voltage v1 is applied to input terminal 8, capacitor C1
and C2 to the output terminal 13 by the operational amplifier 15.
An output voltage V2 determined by the ratio of C1 and C2 appears. Then t
=(n+172)T seconds, as shown in Figure 3(b),
Switch sw1. sw2 are contacts 11. Contact 12
The charge charged in C1 is discharged to the reference voltage terminal 14, and the charge in C2 is held. At this time, the charge of the parasitic capacitance of the switch is also discharged at the same time, and has no effect on the charge transfer from vl to v2.

（発明が解決しようとする問題点） ところで、第２図、第３図（ａ）　、　（ｂ）に示した
ように、スイッチド・キャパシタ積分器は、演算増幅器
用電源ｖＤＤ、Ｖｓｓのため２個の端子及び基準電源Ｖ
ｒｅｆ用の１個の端子を必要とする。従って、このよう
なスイッチド・キャパシタ積分器を二電源（ＶＤＤ　ｖ
　Ｖｓｓ　）使用形の通常のランダムロジックと混在さ
せるにはさらに電源を増やす必要がある。そこで、従来
性なわれて来たのは第４図に示すように、ＶＤＤ、７８
８間に２個の抵抗を直列に接続し、その接続点から基準
電圧ｖｒｅｆを得方法である。又一般に、半導体基板上
では拡散層等により形成される。ところが第４図のよう
な抵抗分割による基準電圧発生回路は、第３図で示した
電荷の放電を基準電圧Ｖｒｅｆに対して行なうと、集積
回路の様に、多数のスイッチドキャパシタ積分器を含む
と抵抗ＲＩ　、Ｒ２に流れる電流が時間的に変化し、か
つＲ１，Ｒ，の抵抗値が高い数にΩ〜数千１（Ωと基準
電圧Ｖｒｅｆの変動が大きくなシ、スイッチド・・キャ
パシタ積分器の特性に多大な影響を与える。又、変動を
小さくするために、抵抗値を小さくする（数Ω〜数十Ω
）と、消費電力が非常に大きくなり、特に集積回路にお
いては致命的であるという欠点がある。(Problems to be Solved by the Invention) By the way, as shown in FIGS. 2, 3(a) and 3(b), the switched capacitor integrator has two terminals and reference power supply V
Requires one terminal for ref. Therefore, such a switched capacitor integrator can be connected to two power supplies (VDD v
Vss) It is necessary to further increase the power supply in order to mix it with the normal random logic used. Therefore, as shown in Figure 4, what has been conventionally used is the VDD, 78
In this method, two resistors are connected in series between 8 and 8, and a reference voltage vref is obtained from the connection point. Further, it is generally formed by a diffusion layer or the like on a semiconductor substrate. However, the reference voltage generation circuit using resistance division as shown in FIG. 4 includes a large number of switched capacitor integrators like an integrated circuit when the charge shown in FIG. 3 is discharged to the reference voltage Vref. If the current flowing through the resistors RI and R2 changes over time, and the resistance values of R1 and R are high, the resistance value ranges from Ω to several thousand 1 (Ω and the reference voltage Vref vary greatly). It has a great effect on the characteristics of the integrator.In addition, to reduce the fluctuation, the resistance value should be small (several ohms to several tens of ohms).
), the power consumption becomes extremely large, which is particularly fatal for integrated circuits.

本発明の目的は、上記欠点を除去し、演算増幅器を用い
て１時間的に変動する負荷に対して消費電力を大きくす
ることなく安定した基準電位が得られるスイッチド・キ
ャパシタ積分器用の基準電圧発生回路を提供することに
ある。The object of the present invention is to provide a reference voltage for a switched capacitor integrator that eliminates the above-mentioned drawbacks and that uses an operational amplifier to obtain a stable reference potential for a load that changes hourly without increasing power consumption. The purpose of this invention is to provide a generating circuit.

（問題点を解決するだめの手段） 本発明のスイッチド・キャパシタ積分器用の基準電圧発
生回路は、二つの電源間に直列に接続された二つの抵抗
の接続点を演算増幅器の非反転入力端に接続し、演算増
幅器の反転入力端と、出力端を接続し、該出力端を複数
のスイッチド・キャパシタ積分器の基準電圧端へ接続す
ることによ多構成される。(Means for solving the problem) The reference voltage generation circuit for a switched capacitor integrator of the present invention connects the connection point of two resistors connected in series between two power supplies to the non-inverting input terminal of an operational amplifier. The inverting input terminal and the output terminal of the operational amplifier are connected to each other, and the output terminal is connected to reference voltage terminals of a plurality of switched capacitor integrators.

（作用） ５一 本発明の基準電圧発生回路において、二つの電源間に直
列に接続された二つの抵抗の接続点の電位は抵抗値の比
によって決まり、例えば抵抗値が等しければ−ｒ　（Ｖ
ＤＤ　−Ｖｓｓ　）の電位となる。演算増幅器の反転入
力端と出力端を接続することにより、該演算増幅器用電
源は１となり、非反転入力の電圧が出力端に表われる。(Function) 5. In the reference voltage generation circuit of the present invention, the potential at the connection point of two resistors connected in series between two power supplies is determined by the ratio of the resistance values. For example, if the resistance values are equal, -r (V
DD-Vss). By connecting the inverting input terminal and the output terminal of the operational amplifier, the power supply for the operational amplifier becomes 1, and the voltage at the non-inverting input appears at the output terminal.

さらに演算増幅器の出力インピーダンスは１０以下とな
り、時間的な負荷変動に対して安定した所定電位が得ら
れる。Furthermore, the output impedance of the operational amplifier is 10 or less, and a stable predetermined potential can be obtained against temporal load fluctuations.

（実施例） 次に、本発明の実施例について図面を用いて説明する。(Example) Next, embodiments of the present invention will be described using the drawings.

第１図は本発明の一実施例の回路図である。FIG. 1 is a circuit diagram of an embodiment of the present invention.

この実施例は、二つの電源ＶＤＤとＶＳＳとの間に直列
に接続された二つの抵抗１８．１９の接続点２０を演算
増幅器２２の非反転入力端に接続し、との演算増幅器２
２０反転入力端と出力端２１を接続し、演算増幅器の出
力端２１を複数のスイッチド・キャパシタ積分器の基準
電圧端へ接続することにより構成される。第１図におい
て番号２３゜２４は例えば第２図、第３図（ａ）　、　
（ｂ）に示したようなスイッチド・キャパシタ積分器で
ある。In this embodiment, a connection point 20 between two resistors 18 and 19 connected in series between two power supplies VDD and VSS is connected to a non-inverting input terminal of an operational amplifier 22.
20 inverting input terminal and output terminal 21 are connected, and the output terminal 21 of the operational amplifier is connected to the reference voltage terminal of a plurality of switched capacitor integrators. In Fig. 1, the numbers 23 and 24 are, for example, Fig. 2, Fig. 3 (a),
This is a switched capacitor integrator as shown in (b).

抵抗１８．１９は分割抵抗であり、通常その抵抗値は等
しくしておく。すると、接続点２０には一！−（ＶＤＤ
　　ＶＳＳ　）の電圧が得れる。演算増幅器２２の入力
は高インピーダンスであるので、抵抗１８゜１９の負荷
の時間的変動は皆無である。演算増幅器２２の反転入力
端は出力端に接続されているのでその出力インピーダン
スは１Ω以下である。Resistors 18 and 19 are divided resistors, and their resistance values are usually kept equal. Then, there is one at connection point 20! -(VDD
VSS) voltage can be obtained. Since the input of the operational amplifier 22 is of high impedance, there is no temporal variation in the load on the resistors 18 and 19. Since the inverting input terminal of the operational amplifier 22 is connected to the output terminal, its output impedance is 1Ω or less.

本実施例では２個のスイッチド・キャパシタ積分器を２
３．２４の様に示したが、もちろん３個以上であっても
よく、基準電圧端Ｖｒｅｆ　の全体の過渡電流が１ｍＡ
としてもその電位変動は１°×１ｍＡ−１ｍＶとなり１
ｍＶ以下となる。In this example, two switched capacitor integrators are used.
3.24, but of course there may be three or more, and the entire transient current of the reference voltage terminal Vref is 1 mA.
Even if the potential fluctuation is 1°×1mA-1mV, 1
mV or less.

（発明の効果） 以上説明した様に、本発明によれば、反転入力端と出力
端を接続した演算増幅器を用いて、時間的に変動する負
荷に対して、消費電力を大きくすることなく安定した基
準電源が得られる、スイッチド・キャパシタ積分器用の
基準電圧発生回路が得られる。(Effects of the Invention) As explained above, according to the present invention, by using an operational amplifier in which an inverting input terminal and an output terminal are connected, it is possible to stabilize loads that vary over time without increasing power consumption. A reference voltage generation circuit for a switched capacitor integrator is obtained, which can provide a reference power supply with a constant voltage.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例の回路図、第２図は従来のス
イッチド・キャパシタ積分器の一例の回路図、第３図（
ａ）　Ｉ　（ｂ）は従来のスイッチド・キャパシタ積分
器の他の例の回路図、第４図は従来の抵抗分割による基
準電圧発生回路を示す回路図である。 １・・・・・・入力端子、２，３．４・・・・・・接点
、５・・・・・・出力端、６・・・・・・基準電圧端、
７・・・・・・演算増幅器、８・・・・・・入力端子、
９．１０．１１．１２・・・・・・接点、１３・・・・
・・出力端、１４・・・・・・基準電圧端、１５・・・
・・・演算増幅器、１６．１７．１８．１９パ・・°抵
抗、２０・・・・・・接続点、２１・・・・・出力端、
２２・・・・・・演算増幅器、２３．２４・・・・パス
イッチド・キャパシタ積分器。FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a circuit diagram of an example of a conventional switched capacitor integrator, and FIG.
a) I (b) is a circuit diagram of another example of a conventional switched capacitor integrator, and FIG. 4 is a circuit diagram showing a conventional reference voltage generation circuit using resistance division. 1...Input terminal, 2, 3.4...Contact, 5...Output terminal, 6...Reference voltage terminal,
7... operational amplifier, 8... input terminal,
9.10.11.12... Contact, 13...
...Output end, 14...Reference voltage end, 15...
...Operation amplifier, 16.17.18.19 resistor, 20...Connection point, 21...Output end,
22... operational amplifier, 23.24... path switched capacitor integrator.

Claims (1)

【特許請求の範囲】[Claims] 二つの電源間に直列に接続された二つの抵抗の接続点を
演算増幅器の非反転入力端に接続し、該演算増幅器の反
転入力端と出力端を接続し、該演算増幅器の出力端を複
数のスイッチドキャパシタ積分器の基準電圧端へ接続し
たことを特徴とする基準電圧発生回路。A connection point between two resistors connected in series between two power supplies is connected to a non-inverting input terminal of an operational amplifier, an inverting input terminal and an output terminal of the operational amplifier are connected, and a plurality of output terminals of the operational amplifier are connected. A reference voltage generation circuit characterized in that the circuit is connected to a reference voltage terminal of a switched capacitor integrator.