JPS6138863B2 - - Google Patents
Info
- Publication number
- JPS6138863B2 JPS6138863B2 JP13657080A JP13657080A JPS6138863B2 JP S6138863 B2 JPS6138863 B2 JP S6138863B2 JP 13657080 A JP13657080 A JP 13657080A JP 13657080 A JP13657080 A JP 13657080A JP S6138863 B2 JPS6138863 B2 JP S6138863B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- conductor layer
- ceramic layer
- substrate
- epoxy resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000919 ceramic Substances 0.000 claims description 26
- 239000004020 conductor Substances 0.000 claims description 24
- 239000000758 substrate Substances 0.000 claims description 21
- 239000004065 semiconductor Substances 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 8
- 239000011148 porous material Substances 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 239000000203 mixture Substances 0.000 claims description 5
- 238000007751 thermal spraying Methods 0.000 claims description 5
- 230000017525 heat dissipation Effects 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 229920001187 thermosetting polymer Polymers 0.000 claims description 3
- 239000003822 epoxy resin Substances 0.000 description 17
- 229920000647 polyepoxide Polymers 0.000 description 17
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 10
- 229920005989 resin Polymers 0.000 description 9
- 239000011347 resin Substances 0.000 description 9
- 229910052802 copper Inorganic materials 0.000 description 8
- 239000010949 copper Substances 0.000 description 8
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 239000011521 glass Substances 0.000 description 5
- LTPBRCUWZOMYOC-UHFFFAOYSA-N Beryllium oxide Chemical compound O=[Be] LTPBRCUWZOMYOC-UHFFFAOYSA-N 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000007750 plasma spraying Methods 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 238000009413 insulation Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 239000006071 cream Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 2
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 1
- 229920000178 Acrylic resin Polymers 0.000 description 1
- 239000004925 Acrylic resin Substances 0.000 description 1
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 239000004641 Diallyl-phthalate Substances 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 1
- CPLXHLVBOLITMK-UHFFFAOYSA-N Magnesium oxide Chemical compound [Mg]=O CPLXHLVBOLITMK-UHFFFAOYSA-N 0.000 description 1
- 239000005062 Polybutadiene Substances 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- QUDWYFHPNIMBFC-UHFFFAOYSA-N bis(prop-2-enyl) benzene-1,2-dicarboxylate Chemical compound C=CCOC(=O)C1=CC=CC=C1C(=O)OCC=C QUDWYFHPNIMBFC-UHFFFAOYSA-N 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010891 electric arc Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- LNEPOXFFQSENCJ-UHFFFAOYSA-N haloperidol Chemical compound C1CC(O)(C=2C=CC(Cl)=CC=2)CCN1CCCC(=O)C1=CC=C(F)C=C1 LNEPOXFFQSENCJ-UHFFFAOYSA-N 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000178 monomer Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229920003192 poly(bis maleimide) Polymers 0.000 description 1
- 229920002857 polybutadiene Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 229920005749 polyurethane resin Polymers 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 230000001131 transforming effect Effects 0.000 description 1
Landscapes
- Insulated Metal Substrates For Printed Circuits (AREA)
Description
【発明の詳細な説明】
この発明は発熱量の大きい半導体素子を組込ん
だ半導体装置およびその製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device incorporating a semiconductor element that generates a large amount of heat, and a method for manufacturing the same.
半導体装置の一つである混成集積回路装置に使
用する基板として、薄膜用としては表面が滑らか
なガラスを多く使用し、厚膜用としては導体の焼
成温度との関係からアルミナ等のセラミツクを多
く使用することが一般的であり、これらの基板は
放熱を効果的に行なうために放熱板に接着されて
使用される。しかしながら基板として上記のガラ
スやセラミツクを使用した場合、パツケージング
の際のリード線の取り出し方や収納ケースの取り
付け方等、実装上の煩わしさが常につきまとつて
いる。また特にパワートランジスタ等発熱量の大
きな半導体素子を組込んだ場合には、この素子で
発生する熱を放熱板に速やかに伝導させる必要が
あるために、基板と放熱板とを接着する際に両者
の熱抵抗を均一にする必要があり、また接着部分
における機械的強度もある程度大きくする必要が
あるが、これらの点で問題があつた。 For substrates used in hybrid integrated circuit devices, which are a type of semiconductor device, glass with a smooth surface is often used for thin films, and ceramics such as alumina are often used for thick films due to the firing temperature of the conductor. These substrates are generally used by being bonded to a heat sink in order to effectively dissipate heat. However, when the above-mentioned glass or ceramic is used as a substrate, there are always mounting difficulties such as how to take out lead wires during packaging and how to attach a storage case. In addition, especially when incorporating a semiconductor element that generates a large amount of heat, such as a power transistor, it is necessary to quickly conduct the heat generated by this element to the heat sink. It is necessary to make the thermal resistance uniform, and it is also necessary to increase the mechanical strength of the bonded portion to some extent, but there are problems in these respects.
そこで、最近では上記のような問題に対し、回
路を形成するための基板と放熱板とを一体化する
考え方が出現した。これは基板を複合材料によつ
て構成するものであり、たとえばホーロー基板や
IMST基板がそれに当る。第１図はこのうちのホ
ーロー基板の構成を示す断面図である。この基板
は鉄板１をガラス層２で覆つたものであり、その
一方面には銅からなる導電体層３がパターニング
形成されている。また第２図は上記IMST基板の
構成を断面して示すものであり、この基板はアル
ミニウム板１１の一方面に絶縁性樹脂層１２を形
成し、さらにこの上に銅からなる導電体層１３を
パターニング形成したものであり、上記ホーロー
基板およびIMST基板の導電体層３，１３それぞ
れの上には半導体素子を始めとする各種素子が取
着されて所定の機能回路が形成される。 Therefore, recently, in order to solve the above-mentioned problems, a concept of integrating a circuit board and a heat sink has emerged. This is a board made of a composite material, such as a hollow board or
This is the case with the IMST board. FIG. 1 is a sectional view showing the structure of the hollow substrate. This substrate consists of an iron plate 1 covered with a glass layer 2, on one side of which a conductor layer 3 made of copper is patterned. FIG. 2 shows a cross-sectional view of the configuration of the above-mentioned IMST board, which has an insulating resin layer 12 formed on one side of an aluminum plate 11, and a conductive layer 13 made of copper on top of this. Various elements including semiconductor elements are attached on each of the conductor layers 3 and 13 of the hollow substrate and the IMST substrate to form a predetermined functional circuit.
ところで上記ホーロー基板では、表面にガラス
層２が被覆されているために耐熱性は十分ある
が、ガラス層２の熱伝導性が良好でないために放
熱が効果的に行なわれないという欠点がある。一
方、IMST基板では絶縁性樹脂層１２を介して導
電体層１３が形成されているため、耐熱的、熱抵
抗的、耐電圧的それぞれの点で問題がある。この
うちIMST基板の熱抵抗について考えてみる。一
般に、ある物質中を伝導する熱量Ｑは次式で与え
られる。 By the way, the above-mentioned hollow substrate has sufficient heat resistance because its surface is coated with the glass layer 2, but has a drawback that heat radiation cannot be effectively performed because the thermal conductivity of the glass layer 2 is not good. On the other hand, in the IMST substrate, since the conductor layer 13 is formed through the insulating resin layer 12, there are problems in terms of heat resistance, thermal resistance, and voltage resistance. Among these, let's consider the thermal resistance of the IMST board. Generally, the amount of heat Q conducted in a certain substance is given by the following equation.
Ｑ＝Ｋ・Ａ・ΔＴ／ΔＸ ………(1) Ｋ：物質の熱伝導率 Ａ：熱が伝導する部分の面積 ΔＸ：物質の厚み ΔＴ：物質の両端での温度差 また上記(1)式を変形すると次式が得られる。 Q=K・A・ΔT/ΔX……(1) K: thermal conductivity of material A: Area of the part where heat is conducted ΔX: Thickness of material ΔT: temperature difference at both ends of the substance Furthermore, by transforming the above equation (1), the following equation is obtained.
ΔＴ＝ΔＸ／Ｋ・Ａ・Ｑ ………(2)
上記(2)式は電子回路におけるオームの法則Ｖ＝
Ｒ・Ｉ（Ｖ：電圧、Ｒ：抵抗、Ｉ：電流）に相当
し、ΔＸ／Ｋ・Ａは熱抵抗と称されRthで表わされる。
し
たがつて物質の熱伝導の良し悪しはこのRthの値
で大小で判断することができる。すなわち物質の
厚みΔＸが薄い程、また熱伝導率Ｋが大きい程、
熱抵抗Rthは小さくなり熱の伝導が良くなること
がわかる。そこでいま前記絶縁性樹脂層１２が25
μｍの厚みのエポキシ樹脂によつて構成されてい
るならば、この層１２の熱抵抗Rthの値は、
２．５×１０−３／３．５×１０−３・Ａ＝０．７１／
Ａとなり、大きなものとなつて
しまう。このためIMST基板でも放熱が効果的に
行なわれないという欠点がある。 ΔT=ΔX/K・A・Q……(2) The above equation (2) is Ohm’s law in electronic circuits V=
It corresponds to R·I (V: voltage, R: resistance, I: current), and ΔX/K·A is called thermal resistance and is expressed as Rth.
Therefore, the quality of heat conduction of a substance can be judged by the value of Rth. In other words, the thinner the thickness ΔX of the substance and the larger the thermal conductivity K,
It can be seen that the thermal resistance Rth becomes smaller and the heat conduction becomes better. Therefore, the insulating resin layer 12 is now
If it is made of epoxy resin with a thickness of μm, the value of thermal resistance Rth of this layer 12 is:
2.5×10 −3 /3.5×10 −3・A=0.71/
It becomes A and becomes a big thing. For this reason, even the IMST substrate has the disadvantage that heat dissipation is not performed effectively.
この発明は上記のような事情を考慮してなされ
たものであり、その目的とするところは、半導体
素子で発生する熱を効率よく外部に放出させるこ
とができる半導体装置およびその製造方法を提供
することにある。 The present invention has been made in consideration of the above circumstances, and its purpose is to provide a semiconductor device and a method for manufacturing the same that can efficiently release heat generated in a semiconductor element to the outside. There is a particular thing.
以下図面を参照してこの発明の一実施例を説明
する。第３図はこの発明に係る半導体装置を製造
する際の各工程を示す断面図であり、次のように
して製造される。まず第３図ａに示すように平面
寸法が40×60mm、厚さが２mmのアルミニウムから
なる基板２１の一表面にアルミナ（Al2O3）の粗
い粉末を吹き付けて20〜30μｍ程度の荒さに粗面
化し、この後、１〜２時間以内にプラズマ溶射に
より基板２１の表面にアルミナからなる絶縁性の
セラミツク層22を100〜120μｍの厚みに堆積形成
する。さらに上記セラミツク層２２形成後、プラ
ズマ溶射によりセラミツク層２２の表面全面に銅
からなる導電体層２３を40〜50μｍの厚に堆積形
成する。上記プラズマ溶射による方法は、プラズ
マ溶射ガンと称される電極間に不活性ガス、また
は不活性ガスと水素あるいはヘリウムとの混合ガ
スを流し、上記電極間に電気アークを発生させこ
れによりガスを励起させて熱プラズマを生じさせ
る。そしてこの熱プラズマの生じている焔の中に
アルミナまたは銅の粉末を導入し、このアルミナ
または銅を溶けた状態で基板２１またはセラミツ
ク層２２に付着させるものである。 An embodiment of the present invention will be described below with reference to the drawings. FIG. 3 is a cross-sectional view showing each step in manufacturing the semiconductor device according to the present invention, which is manufactured as follows. First, as shown in Figure 3a, coarse powder of alumina (Al 2 O 3 ) is sprayed onto one surface of a substrate 21 made of aluminum with a planar dimension of 40 x 60 mm and a thickness of 2 mm to give a roughness of about 20 to 30 μm. After the surface is roughened, an insulating ceramic layer 22 made of alumina is deposited to a thickness of 100 to 120 μm on the surface of the substrate 21 by plasma spraying within 1 to 2 hours. Further, after the ceramic layer 22 is formed, a conductor layer 23 made of copper is deposited to a thickness of 40 to 50 .mu.m over the entire surface of the ceramic layer 22 by plasma spraying. The above plasma spraying method involves flowing an inert gas or a mixture of inert gas and hydrogen or helium between electrodes called a plasma spray gun, generating an electric arc between the electrodes and exciting the gas. to generate a thermal plasma. Then, alumina or copper powder is introduced into the flame where the thermal plasma is generated, and the alumina or copper is adhered to the substrate 21 or the ceramic layer 22 in a molten state.
次に上記基板２１を125℃の温度で２〜３時間
加熱した後室温に戻し、さらに60℃に保つた熱板
上に放置して、上記導電体層２３表面に熱硬化性
の絶縁性組成物たとえばエポキシ樹脂２４を滴下
し、これを全面に拡げて塗布する（第３図ｂ）。
一般に溶射によつて形成される層は密度が焼結体
等よりも小さく、焼結体の90％程度といわれてい
る。すなわち上記形成されたセラミツク層２２お
よび導電体層２３には多数の連結空孔が存在して
いる。そこで上記のように導電体層２３の表面に
エポキシ樹脂を滴下して全面に塗布すると、上記
両層２２，２３に存在している連結空孔内にこの
エポキシ樹脂が入り込み連結空孔はエポキシ樹脂
で埋められる。上記エポキシ樹脂２４塗布後、３
分間放置してから、表面の余分なエポキシ樹脂２
４をスキージ等で除去し、150℃、30分および180
℃、30分加熱してエポキシ樹脂を硬化させる。 Next, the substrate 21 is heated at a temperature of 125° C. for 2 to 3 hours, returned to room temperature, and then left on a hot plate kept at 60° C., so that a thermosetting insulating composition is applied to the surface of the conductive layer 23. A material such as epoxy resin 24 is dropped and spread over the entire surface (FIG. 3b).
In general, the density of a layer formed by thermal spraying is lower than that of a sintered body, and is said to be about 90% of that of a sintered body. That is, a large number of connected pores are present in the ceramic layer 22 and conductor layer 23 formed above. Therefore, when epoxy resin is dropped onto the surface of the conductor layer 23 and applied to the entire surface as described above, this epoxy resin enters the connecting pores existing in both layers 22 and 23, and the connecting pores are filled with epoxy resin. It is filled with After applying the above epoxy resin 24, 3
Leave it for a minute, then remove any excess epoxy resin on the surface.
Remove 4 with a squeegee, etc., and heat at 150℃ for 30 minutes and 180℃.
Cure the epoxy resin by heating for 30 minutes.
次に導電体層２３の表面に残り、硬化したエポ
キシ樹脂をサンドペーパー等で除去し、さらに次
に導電体層２３表面に所望のパターンでエツチン
グ用レジスタを印刷しこれを125℃で10分間乾燥
させる。そして次に塩化第２鉄の50％水溶液を用
いて上記導電体層２３をエツチングして所望のパ
ターンを形成する（第３図ｃ）。この後は上記エ
ツチングによつてパターニングされた導電体層２
３表面に、第３図ｄに示すように半田クリーム２
５を選択的に印刷し、さらにこの上に銅からなる
ヒートブロツク２６に載置されたパワートランジ
スタ２７、小信号用のトランジスタ２８、抵抗チ
ツプ２９、端子３０を乗せ、150℃、15秒の予備
加熱を経て230℃、15秒で半田リフローして半田
付けを行なうことにより各素子を取着し、その
後、金属製等の蓋で封止することにより完成す
る。 Next, the hardened epoxy resin remaining on the surface of the conductor layer 23 is removed with sandpaper, etc. Next, an etching register is printed in the desired pattern on the surface of the conductor layer 23, and this is dried at 125°C for 10 minutes. let Then, the conductor layer 23 is etched using a 50% aqueous solution of ferric chloride to form a desired pattern (FIG. 3c). After this, the conductor layer 2 patterned by the above etching
3. Apply solder cream 2 to the surface as shown in Figure 3 d.
5 was selectively printed, and furthermore, a power transistor 27, a small signal transistor 28, a resistor chip 29, and a terminal 30 placed on a heat block 26 made of copper were placed on top of this, and a preliminary test was carried out at 150°C for 15 seconds. After heating, each element is attached by performing solder reflow at 230°C for 15 seconds, and then sealed with a metal lid to complete the process.
このような構成でなる半導体装置では、基板２
１上に堆積形成する絶縁物層としてセラミツク層
２２を採用したことにより、この絶縁物層の熱抵
抗を従来よりも大幅に低下させることができる。
たとえばこのセラミツク層２２の厚みを100μｍ
に設定すれば、前記Rthの式を用いて算出したこ
の層２２の熱抵抗は、１００×１０−４／０．２６・Ａ
＝３．８５×１０−２／Ａと
なり、エポキシ樹脂を用いた従来の場合の値の約
1/18となる。この結果、上記構成でなる半導体装
置では、半導体素子で発生する熱を効率よく外部
に放出させることができる。 In a semiconductor device having such a configuration, the substrate 2
By employing the ceramic layer 22 as the insulating layer deposited on the insulating layer 1, the thermal resistance of this insulating layer can be significantly lowered than in the past.
For example, the thickness of this ceramic layer 22 is 100 μm.
If set to
= 3.85 × 10 -2 /A, which is about the value of the conventional case using epoxy resin.
It will be 1/18. As a result, in the semiconductor device having the above configuration, heat generated in the semiconductor element can be efficiently released to the outside.
また溶射によつて形成されたセラミツク層２２
は初期には絶縁層としての役割を果たしている
が、時間が経つにつれて湿気等が前記連結空孔内
に入り込み、絶縁性が低下して短絡状態になつて
しまう。また導電体層２３を形成するとこの層内
の銅の粒子がセラミツク層２２の連結空孔内に入
り込み上記と同様に短絡現象を起すことになる。
しかしながら上記実施例の場合、セラミツク層２
２の連結空孔をエポキシ樹脂によつて埋めるよう
にしたので、セラミツク層２２の絶縁性は極めて
高いものとすることができる。たとえば基板２１
と導電体層２３との間の耐電圧を測定したところ
直流で4.5KV、60秒以上あり、この値は十分に実
用に耐え得るものである。なおこのように極めて
高い耐電圧性能をもたらす絶縁性組成物の選択基
準としては、粘度が低く作業性が良いこと、溶剤
を使用すると硬化後の体積が減少して絶縁性が低
下することがあるため粘度を下げるために溶剤を
使用しないこと、硬化温度が低くかつ硬化時間が
短かいこと、等の条件が必要である。またこのよ
うな条件を満足する樹脂としては前記エポキシ樹
脂の他に熱硬化性樹脂のうちのアクリル樹脂、ポ
リウレタン樹脂、ジアリルフタレート樹脂、ポリ
ブタジエン樹脂、ポリイミド樹脂、ビスマレイミ
ド樹脂等の単独あるいは二成分系または低分子量
の多官能性モノマーを配合したもののいずれもが
使用可能である。 Additionally, a ceramic layer 22 formed by thermal spraying
plays the role of an insulating layer initially, but as time passes, moisture and the like enter the connected pores, resulting in a decrease in insulation and a short-circuit condition. Further, when the conductor layer 23 is formed, the copper particles in this layer enter into the connected pores of the ceramic layer 22, causing a short circuit phenomenon as described above.
However, in the case of the above embodiment, the ceramic layer 2
Since the connecting holes 2 are filled with epoxy resin, the insulation of the ceramic layer 22 can be made extremely high. For example, the board 21
The withstand voltage between the conductive layer 23 and the conductive layer 23 was measured and was 4.5 KV in direct current for 60 seconds or more, which is sufficient for practical use. The selection criteria for an insulating composition that provides extremely high withstand voltage performance is that it has low viscosity and good workability, and that the use of solvents can reduce the volume after curing and reduce the insulation properties. Therefore, in order to lower the viscosity, conditions such as not using a solvent, low curing temperature and short curing time are required. In addition to the above-mentioned epoxy resins, examples of resins that satisfy these conditions include thermosetting resins such as acrylic resins, polyurethane resins, diallyl phthalate resins, polybutadiene resins, polyimide resins, and bismaleimide resins, either singly or in two-component systems. Alternatively, a compound containing a low molecular weight polyfunctional monomer can be used.
さらにまた上記セラミツク層２２を形成した後
にこの層２２の連結空孔をエポキシ樹脂によつて
埋め、この後に導電体層を形成すると、この導電
体層とセラミツク層２２との密着性は極めて悪い
ものとなつてしまう。これはセラミツク層２２の
表面が滑らかになるためと思われる。しかしなが
ら上記実施例ではセラミツク層２２の表面に導電
体層２３を堆積形成した後にエポキシ樹脂を塗布
するようにしたので、セラミツク層２２と導電体
層２３との密着性が良好なものとなる。たとえば
上記実施例装置において３mm□の導電体層２３に
0.6mmφの銅線を半田付けした際の引張強度を測
定したところ７Kg以上あつた。 Furthermore, if after forming the ceramic layer 22, the connecting pores of this layer 22 are filled with epoxy resin, and then a conductive layer is formed, the adhesion between this conductive layer and the ceramic layer 22 is extremely poor. I become confused. This seems to be because the surface of the ceramic layer 22 becomes smooth. However, in the above embodiment, since the epoxy resin is applied after depositing the conductor layer 23 on the surface of the ceramic layer 22, the adhesion between the ceramic layer 22 and the conductor layer 23 is good. For example, in the above embodiment device, the conductor layer 23 of 3 mm□
When we measured the tensile strength when soldering 0.6mmφ copper wire, it was over 7kg.
また基板２１上にセラミツク層２２と導電体層
２３とを順次堆積形成し、まずこの導電体層２３
を所望のパターンにエツチングしてからエポキシ
樹脂による連結空孔の埋め込みを行なう場合も考
えられるが、連結空孔を埋める前にエツチングを
行なうとエツチング液が連結空孔内に入り込んで
しまい、その後エポキシ樹脂による埋め込みを行
なつても耐電圧性が改善されないのである。 Further, a ceramic layer 22 and a conductor layer 23 are sequentially deposited on the substrate 21, and the conductor layer 23 is first deposited on the substrate 21.
It may be possible to etch the etching into a desired pattern and then fill in the connecting holes with epoxy resin, but if you perform etching before filling the connecting holes, the etching solution will get into the connecting holes, and then the epoxy resin will fill in the connecting holes. Even if it is filled with resin, the voltage resistance is not improved.
なおこの発明は上記実施例に限定されるもので
はなく、たとえば上記実施例ではセラミツク層２
２はアルミナによつて構成する場合について説明
したが、これはアルミナの他にマグネシア
（MgO）、ベリリア（BeO）、室化アルミ（AlN）、
室化ボロン（BN）のうちの一つあるいはこれら
のうちの少なくとも一つを含む材料によつて構成
するようにしてもよく、溶射による方法もプラズ
マ溶射以外の溶射技術が使用可能である。さらに
導電体層２３は銅によつて構成する場合について
説明したが、これも銅の他にアルミニウム、ニツ
ケルのうち一つあるいはそれらの合金が使用可能
である。 Note that the present invention is not limited to the above embodiments; for example, in the above embodiments, the ceramic layer 2
2 explained the case where it is composed of alumina, but in addition to alumina, magnesia (MgO), beryllia (BeO), indoor aluminum (AlN),
It may be made of one of boron chloride (BN) or a material containing at least one of these, and thermal spraying techniques other than plasma spraying can be used. Further, although the conductive layer 23 is made of copper, it is also possible to use one of aluminum, nickel, or an alloy thereof in addition to copper.
以上説明したようにこの発明に係る半導体装置
およびその製造方法では、半導体素子で発生する
熱を効率よく外部に放出させることができる。 As described above, in the semiconductor device and the manufacturing method thereof according to the present invention, heat generated in the semiconductor element can be efficiently released to the outside.
第１図および第２図はそれぞれ従来の半導体装
置の断面図、第３図ａ〜ｄはこの発明に係る半導
体装置を製造する際の各工程を示す断面図であ
る。
２１……基板、２２……セラミツク層、２３…
…導電体層、２４……エポキシ樹脂、２５……半
田クリーム、２６……ヒートブロツク、２７……
パワートランジスタ、２８……小信号用のトラン
ジスタ、２９……抵抗チツプ、３０……端子。
1 and 2 are sectional views of a conventional semiconductor device, and FIGS. 3a to 3d are sectional views showing each step in manufacturing the semiconductor device according to the present invention. 21...Substrate, 22...Ceramic layer, 23...
...Conductor layer, 24...Epoxy resin, 25...Solder cream, 26...Heat block, 27...
Power transistor, 28...transistor for small signals, 29...resistance chip, 30...terminal.
Claims (1)
され連結空孔を備えた絶縁性のセラミツク層と、
このセラミツク層の表面に堆積形成され連結空孔
を備えかつパターニングされた導電体層と、上記
セラミツク層および導電体層に備えられた連結空
孔を埋めるように設けられた絶縁性組成物と、上
記導電体層上に取着される少なくとも一つの半導
体素子とを具備したことを特徴とする半導体装
置。 ２ 放熱基板の表面に溶射技術によつて絶縁性の
セラミツク層を堆積形成し、上記セラミツク層の
表面に溶射技術によつて導電体層を堆積形成し、
上記導電体層表面に熱硬化性の絶縁性組成物を塗
布、硬化させ、しかる後上記導電体層をパターニ
ングし、このパターニングされた導電体層上に少
なくとも一つの半導体素子を取着するようにした
ことを特徴とする半導体装置の製造方法。[Scope of Claims] 1. A heat dissipation substrate; an insulating ceramic layer deposited on the surface of the heat dissipation substrate and provided with connecting holes;
a patterned conductor layer deposited on the surface of the ceramic layer and provided with connected pores; an insulating composition provided to fill the connected pores provided in the ceramic layer and the conductor layer; A semiconductor device comprising at least one semiconductor element attached on the conductor layer. 2. Depositing an insulating ceramic layer on the surface of the heat dissipation substrate by thermal spraying technique, depositing a conductive layer on the surface of the ceramic layer by thermal spraying technique,
A thermosetting insulating composition is applied and cured on the surface of the conductor layer, and then the conductor layer is patterned, and at least one semiconductor element is attached on the patterned conductor layer. A method for manufacturing a semiconductor device, characterized in that:
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13657080A JPS5760894A (en) | 1980-09-30 | 1980-09-30 | Semiconductor device and method of producing same |
| EP19810107748 EP0048992B1 (en) | 1980-09-30 | 1981-09-29 | Printed circuit board and method for fabricating the same |
| DE8181107748T DE3176951D1 (en) | 1980-09-30 | 1981-09-29 | Printed circuit board and method for fabricating the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13657080A JPS5760894A (en) | 1980-09-30 | 1980-09-30 | Semiconductor device and method of producing same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5760894A JPS5760894A (en) | 1982-04-13 |
| JPS6138863B2 true JPS6138863B2 (en) | 1986-09-01 |
Family
ID=15178338
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13657080A Granted JPS5760894A (en) | 1980-09-30 | 1980-09-30 | Semiconductor device and method of producing same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5760894A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10590535B2 (en) | 2017-07-26 | 2020-03-17 | Asm Ip Holdings B.V. | Chemical treatment, deposition and/or infiltration apparatus and method for using the same |
| US10600673B2 (en) | 2015-07-07 | 2020-03-24 | Asm Ip Holding B.V. | Magnetic susceptor to baseplate seal |
| US10605530B2 (en) | 2017-07-26 | 2020-03-31 | Asm Ip Holding B.V. | Assembly of a liner and a flange for a vertical furnace as well as the liner and the vertical furnace |
| US10607895B2 (en) | 2017-09-18 | 2020-03-31 | Asm Ip Holdings B.V. | Method for forming a semiconductor device structure comprising a gate fill metal |
| US10604847B2 (en) | 2014-03-18 | 2020-03-31 | Asm Ip Holding B.V. | Gas distribution system, reactor including the system, and methods of using the same |
| USD880437S1 (en) | 2018-02-01 | 2020-04-07 | Asm Ip Holding B.V. | Gas supply plate for semiconductor manufacturing apparatus |
| US10612137B2 (en) | 2016-07-08 | 2020-04-07 | Asm Ip Holdings B.V. | Organic reactants for atomic layer deposition |
| US10612136B2 (en) | 2018-06-29 | 2020-04-07 | ASM IP Holding, B.V. | Temperature-controlled flange and reactor system including same |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7196459B2 (en) * | 2003-12-05 | 2007-03-27 | International Resistive Co. Of Texas, L.P. | Light emitting assembly with heat dissipating support |
-
1980
- 1980-09-30 JP JP13657080A patent/JPS5760894A/en active Granted
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10604847B2 (en) | 2014-03-18 | 2020-03-31 | Asm Ip Holding B.V. | Gas distribution system, reactor including the system, and methods of using the same |
| US10600673B2 (en) | 2015-07-07 | 2020-03-24 | Asm Ip Holding B.V. | Magnetic susceptor to baseplate seal |
| US10612137B2 (en) | 2016-07-08 | 2020-04-07 | Asm Ip Holdings B.V. | Organic reactants for atomic layer deposition |
| US10590535B2 (en) | 2017-07-26 | 2020-03-17 | Asm Ip Holdings B.V. | Chemical treatment, deposition and/or infiltration apparatus and method for using the same |
| US10605530B2 (en) | 2017-07-26 | 2020-03-31 | Asm Ip Holding B.V. | Assembly of a liner and a flange for a vertical furnace as well as the liner and the vertical furnace |
| US10607895B2 (en) | 2017-09-18 | 2020-03-31 | Asm Ip Holdings B.V. | Method for forming a semiconductor device structure comprising a gate fill metal |
| USD880437S1 (en) | 2018-02-01 | 2020-04-07 | Asm Ip Holding B.V. | Gas supply plate for semiconductor manufacturing apparatus |
| US10612136B2 (en) | 2018-06-29 | 2020-04-07 | ASM IP Holding, B.V. | Temperature-controlled flange and reactor system including same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5760894A (en) | 1982-04-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS632159B2 (en) | ||
| US3423517A (en) | Monolithic ceramic electrical interconnecting structure | |
| JPS6138863B2 (en) | ||
| EP0048992B1 (en) | Printed circuit board and method for fabricating the same | |
| JPH07283499A (en) | Compound board for electronic parts | |
| JPH1145616A (en) | Forming method of conductive filler, conductive paste and circuit body | |
| JP4383866B2 (en) | Power electronic unit | |
| JPH0568877B2 (en) | ||
| JP2726515B2 (en) | Semiconductor tower mounting circuit board and method of manufacturing the same | |
| RU2454841C2 (en) | Circuit substrate | |
| JPH06188530A (en) | Dielectric material and circuit board employing it | |
| JPS59119749A (en) | Semiconductor device | |
| JP2753743B2 (en) | Manufacturing method of electronic circuit board | |
| JPS6262470B2 (en) | ||
| JP2632151B2 (en) | Manufacturing method of circuit block | |
| JPS5818997A (en) | Method of producing hybrid integrated circuit substrate | |
| JPS62226645A (en) | Wiring substrate | |
| JPS59184586A (en) | Circuit board for placing semiconductor element | |
| JPH01157589A (en) | Manufacture of metal base substrate | |
| JPH02125728A (en) | Composite base and its manufacture | |
| JPH01232796A (en) | Manufacture of metal core insulated board | |
| JPH01240676A (en) | Manufacture of metallic base substrate | |
| JPH0760874B2 (en) | Semiconductor device | |
| JPH0770798B2 (en) | High thermal conductivity circuit board | |
| JPS6346592B2 (en) |