JPS6136412B2 - - Google Patents
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- Publication number
- JPS6136412B2 JPS6136412B2 JP53162426A JP16242678A JPS6136412B2 JP S6136412 B2 JPS6136412 B2 JP S6136412B2 JP 53162426 A JP53162426 A JP 53162426A JP 16242678 A JP16242678 A JP 16242678A JP S6136412 B2 JPS6136412 B2 JP S6136412B2
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- Prior art keywords
- circuit
- logic
- signal
- output
- selection
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Links
- 238000000034 method Methods 0.000 claims description 2
- 238000001514 detection method Methods 0.000 description 7
- 230000002159 abnormal effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
Landscapes
- Logic Circuits (AREA)
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Hardware Redundancy (AREA)
Description
本発明は故障検出回路および多数決回路の部分
回路を内蔵する三重化回路に関する。
従来論理回路モジユールで構成された三重化回
路の故障検出および多数決出力のためには、三重
化回路を構成する該論理回路モジユールの他に故
障検出回路および多数決回路を含む別の論理回路
モジユールを付加しなければならない欠点があ
る。
本発明の目的は他の論理回路モジユールを付加
することなく故障の検出および1論理回路モジユ
ールの機能回路の故障が発生した場合も多数決論
理で正しい値を出力することが可能な三重化回路
を提供することにある。
本発明の回路は、同一の信号を入力し処理する
3個の同一論理ユニツトを接続した三重化回路に
おいて、自論理回路と、外部の論理回路からの信
号と前記自論理回路からの信号とを比較する比較
回路と、前記外部の論理回路からの信号と前記自
論理回路からの信号とを外部からの指示信号によ
り選択出力する選択回路とを含む論理回路ユニツ
トを3個具備し、前記3個の論理ユニツトのうち
前段の論理ユニツトの選択回路からの信号を後段
の論理ユニツトの選択回路に前記外部の論理回路
からの信号として与えるように順次巡回的に接続
する接続手段と、3個の前記比較回路からのそれ
ぞれの不一致信号を故障信号として論理和をとり
出力する手段と、前記3個のうち特定の論理ユニ
ツトの前段の論理ユニツト内の比較回路の比較結
果信号を前記特定の論理ユニツトの選択回路の選
択指示信号として与えるとともに他の2個の論理
ユニツトの選択回路の選択指示信号としてそれぞ
れの論理回路からの信号を出力するように選択指
示信号を与える手段と、前記特定の論理ユニツト
の選択回路からの出力信号を三重化回路の出力と
する出力手段とを含むことを特徴とする。
本発明は、三重化されたLSI(Large Scale
Integration:大規模集積回路の略)の機能回路
出力は、該LSIのうちいずれかひとつのLSIの機
能回路故障により、たかだか6とおりの出力信号
の組合せを持ち(表1参照)、該出力の多数決論
理による正しい出力は、いずれかひとつの機能回
路出力に着目した場合、他の2つの機能回路出力
の排他的論理和が“1”の時は自出力を、排他的
論理和が“0”の時は他出力をそれぞれ選択する
ことにより可能である、という原理に基いてい
る。
次に本発明の一実施例について図面を参照して
詳細に説明する。
図に示される本発明の三重化回路は、LSI10
0,200および300、該LSIの論理出力端子
101,102,201,202,301および
302、論理入力
The present invention relates to a triplexing circuit incorporating a failure detection circuit and a partial circuit of a majority decision circuit. In order to detect failures and output a majority vote in a conventional triplexed circuit configured with logic circuit modules, another logic circuit module including a failure detection circuit and a majority vote circuit is added in addition to the logic circuit modules that make up the triplexed circuit. There are drawbacks that must be met. An object of the present invention is to provide a triplex circuit that can detect failures and output correct values using majority logic even if a failure occurs in the functional circuit of one logic circuit module without adding another logic circuit module. It's about doing. The circuit of the present invention is a triplex circuit in which three identical logic units that input and process the same signal are connected, and a signal from an own logic circuit, an external logic circuit, and a signal from the own logic circuit are connected. Three logic circuit units each including a comparison circuit for comparison and a selection circuit for selectively outputting a signal from the external logic circuit and a signal from the own logic circuit according to an external instruction signal, connecting means for sequentially and cyclically connecting a signal from a selection circuit of a preceding logic unit among the logic units of the logic unit to a selection circuit of a succeeding logic unit as a signal from the external logic circuit; Means for ORing and outputting each mismatch signal from the comparison circuit as a failure signal, and means for outputting a comparison result signal of the comparison circuit in the logic unit in the previous stage of the specific logic unit among the three logic units. means for providing a selection instruction signal so as to output a signal from each logic circuit as a selection instruction signal to the selection circuit and to output a signal from each logic circuit as a selection instruction signal to the selection circuit of the other two logic units; The present invention is characterized in that it includes output means for outputting an output signal from the selection circuit as an output from the triplexing circuit. The present invention is a triplexed LSI (Large Scale
The functional circuit output of a large-scale integrated circuit (Integration: Abbreviation for large-scale integrated circuit) has at most six combinations of output signals due to a functional circuit failure in any one of the LSIs (see Table 1), and the majority of the outputs The correct output by logic is that when focusing on the output of any one functional circuit, when the exclusive OR of the other two functional circuit outputs is "1", it is the own output, and when the exclusive OR is "0", it is the own output. It is based on the principle that time can be changed by selecting different outputs. Next, one embodiment of the present invention will be described in detail with reference to the drawings. The triplex circuit of the present invention shown in the figure is an LSI10
0, 200 and 300, logic output terminals 101, 102, 201, 202, 301 and 302 of the LSI, logic input
【表】
いて示す。○+は排他的
はA3)
論理和演算を示す。な
1 0 0 0 0(A2又
おA2、A3に着目した場
はA3)
合も本原理は正しいこ
とが同様に確認できる
1 0 1 1 1(A1)
1 1 0 1 1(A1)
端子103,104,203,204,303
および304、故障出力端子105,205およ
び305、選択回路切換端子106,206およ
び306、機能回路入力端子107,108,1
09,207,208,209,307,308
および309、選択回路切換入力端子110,2
10および310、該LSIに内蔵されている機能
回路F10,F20およびF30、選択回路S1
1,S12,S21,S22,S31およびS3
2、排他的論理和回路X13,X14,X23,
X24,X33およびX34、否定論理和回路N
15,N25およびN35、論理積回路P16,
P26およびP36と、該LSIとは別の前段機能
回路50、後段機能回路150および故障処理回
路250から構成されている。
該LSIの各端子間の結線は、論理出力端子10
1,102,201,202,301および30
2がそれぞれ論理入力端子303,304,10
3,104,203および204に、故障出力端
子105,205および305がワイヤードオア
論理で故障処理回路250に、選択回路切換出力
端子206が選択回路切換入力端子110にそれ
ぞれ接続されている。また該LSIの機能回路入力
端子107,108,109,207,208,
209,307,308および309はすべて前
段機能回路50に、論理出力端子101や102
は論理入力端子303や304の他後段機能回路
150にそれぞれ接続され、選択回路切換出力端
子106や306は開放され、選択回路切換入力
端子210や310は接地されている。
図から明らかなようにLSI100,200およ
び300の構成は同様であり、該LSIの論理入力
端子と論理出力端子との数は機能回路出力数に対
応するが、故障出力端子と選択回路切換出力端子
と選択回路切換入力端子との数は機能回路出力数
にかかわらずそれぞれ1端子である。
次に本発明の一実施例での故障検出および多数
決出力に関する動作について図を用いて説明す
る。図の実施例では機能回路出力は2出力である
が説明を簡略に行うため1出力に着目して説明す
る。説明をさらに簡潔に行うために該LSIの機能
回路F10,F20およびF30の出力信号を信
号A1,A2およびA3とし、選択回路S11,
S21およびS31に入力する選択回路切換入力
信号を信号C1,C2およびC3とし、論理入力
端子103,203および303に入力される論
理入力信号を信号B1,B2およびB3とし、選
択回路S11,S21およびS31の出力信号を
信号D1,D2およびD3とし、排他的論理和回
路X13,X23およびX33の出力信号を信号
E1,E2およびE3とする。
図から明らかなように、選択回路S11,S2
1およびS31の出力信号D1,D2およびD3
は、該LSI100,200,300の論理出力信
号であり、論理出力端子の結線によりそれぞれ該
LSI300,100および200の論理入力信号
B3,B1およびB2に等しい(D1=B3、D
2=B1およびD3=B2)。また論理入力端子
103,203および303の論理入力信号B
1,B2およびB3を一方の入力とし、機能回路
F10,F20およびF30の出力信号A1,A
2およびA3をもう一方の入力とする排他的論理
和回路X13,X23およびX33の出力信号E
1,E2およびE3は、否定的論理和回路N1
5,N25およびN35を介して選択回路切換出
力端子106,206および306に出力され
る。
但し、機能回路F10の出力A1とLSI200か
ら選択回路S21を介して与えられる信号B1と
のどちらか一方を選択回路S11やS12で選択
出力させるため選択回路切換出力端子206が選
択回路切換入力端子110に接続されている(選
択回路切換出力端子106や306は開放、選択
回路切換入力端子210や310は接地されてい
る)。従つて、選択回路切換入力端子110に入
力される選択回路切換入力信号C1は排他的論理
和回路X23の出力信号E2の否定値に等しい
(C1=2=22)。
選択回路S11,S21およびS31は、該
LSIの論理入力端子103,203および303
からの論理入力信号B1,B2およびB3と、機
能回路F10,F20およびF30の出力信号A
1,A2およびA3と、選択回路切換入力端子か
らの選択回路切換入力信号C1,C2およびC3
を入力とし、選択回路出力信号D1,D2および
D3を出力する。選択回路機能を、選択回路S1
1を例にとつて表2に説明する。[Table] ○+ is exclusive
is A3)
Indicates a logical sum operation. Na
1 0 0 0 0(A2 or
If you focus on A2 and A3
is A3)
In this case, this principle is correct.
can be confirmed similarly.
1 0 1 1 1(A1)
1 1 0 1 1(A1)
Terminals 103, 104, 203, 204, 303
and 304, failure output terminals 105, 205 and 305, selection circuit switching terminals 106, 206 and 306, functional circuit input terminals 107, 108, 1
09,207,208,209,307,308
and 309, selection circuit switching input terminal 110, 2
10 and 310, functional circuits F10, F20 and F30 built into the LSI, selection circuit S1
1, S12, S21, S22, S31 and S3
2. Exclusive OR circuits X13, X14, X23,
X24, X33 and X34, NOR circuit N
15, N25 and N35, AND circuit P16,
It is composed of P26 and P36, a front-stage functional circuit 50, a rear-stage functional circuit 150, and a failure processing circuit 250, which are separate from the LSI. The connection between each terminal of the LSI is the logic output terminal 10.
1,102,201,202,301 and 30
2 are logic input terminals 303, 304, and 10, respectively.
3, 104, 203 and 204, fault output terminals 105, 205 and 305 are connected to the fault processing circuit 250 by wired-OR logic, and a selection circuit switching output terminal 206 is connected to the selection circuit switching input terminal 110, respectively. In addition, the functional circuit input terminals 107, 108, 109, 207, 208 of the LSI,
209, 307, 308, and 309 are all connected to the front-stage functional circuit 50, and the logic output terminals 101 and 102
are respectively connected to the logic input terminals 303 and 304 as well as the subsequent functional circuit 150, the selection circuit switching output terminals 106 and 306 are open, and the selection circuit switching input terminals 210 and 310 are grounded. As is clear from the figure, the configurations of LSIs 100, 200, and 300 are similar, and the number of logic input terminals and logic output terminals of the LSIs corresponds to the number of functional circuit outputs, but the failure output terminal and selection circuit switching output terminal and selection circuit switching input terminals are each one regardless of the number of functional circuit outputs. Next, operations related to failure detection and majority output in one embodiment of the present invention will be explained using the drawings. In the illustrated embodiment, there are two functional circuit outputs, but in order to simplify the explanation, the explanation will focus on one output. To make the explanation more concise, the output signals of the functional circuits F10, F20, and F30 of the LSI are referred to as signals A1, A2, and A3, and the selection circuits S11,
Selection circuit switching input signals input to S21 and S31 are signals C1, C2, and C3, logic input signals input to logic input terminals 103, 203, and 303 are signals B1, B2, and B3, and selection circuits S11, S21, and The output signals of S31 are assumed to be signals D1, D2 and D3, and the output signals of exclusive OR circuits X13, X23 and X33 are assumed to be signals E1, E2 and E3. As is clear from the figure, selection circuits S11 and S2
1 and S31 output signals D1, D2 and D3
are the logic output signals of the LSIs 100, 200, and 300, and the respective logic output signals are determined by connecting the logic output terminals.
Equal to logic input signals B3, B1 and B2 of LSI300, 100 and 200 (D1=B3, D
2=B1 and D3=B2). In addition, logic input signal B of logic input terminals 103, 203 and 303
1, B2 and B3 as one input, and output signals A1, A of functional circuits F10, F20 and F30.
Output signal E of exclusive OR circuits X13, X23, and X33 with 2 and A3 as other inputs
1, E2 and E3 are negative OR circuit N1
5, N25 and N35 to selection circuit switching output terminals 106, 206 and 306. However, in order to selectively output either the output A 1 of the functional circuit F10 or the signal B1 given from the LSI 200 via the selection circuit S21 by the selection circuits S11 or S12, the selection circuit switching output terminal 206 is used as the selection circuit switching input terminal. 110 (the selection circuit switching output terminals 106 and 306 are open, and the selection circuit switching input terminals 210 and 310 are grounded). Therefore, the selection circuit switching input signal C1 input to the selection circuit switching input terminal 110 is equal to the negative value of the output signal E2 of the exclusive OR circuit X23 (C1=2=22). The selection circuits S11, S21 and S31 select the corresponding
LSI logic input terminals 103, 203 and 303
logic input signals B1, B2 and B3 from and output signals A of functional circuits F10, F20 and F30.
1, A2 and A3, and selection circuit switching input signals C1, C2 and C3 from the selection circuit switching input terminals.
is input, and outputs selection circuit output signals D1, D2, and D3. The selection circuit function is changed to selection circuit S1.
This will be explained in Table 2 using No. 1 as an example.
【表】【table】
【表】
表 3
A1 A2 A3
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
三重化回路を構成する機能回路F10,F20
およびF30が正常に動作しているか、あるいは
たかだか1LSIの機能回路が異常の場合の機能回
路F10,F20およびF30の出力信号A1,
A2およびA3がとりえる値の組合せはたかだか
8とおりである(具体的には表3に示す)。表3
に示す信号A1,A2およびA3の組合せすべて
に対して三重化回路出力(図ではLSI100の論
理出力信号D1)が多数決論理に従つた正しい値
であることを次に説明する。
LSI300の論理出力信号D3は、該LSIの選
択回路S31の選択回路切換入力端子が接地され
ているため論理入力信号B3にかかわらず信号A
3に等しくなる(表2の選択回路の機能から明ら
かである)。次段LSI200の論理出力信号D2
も同様の理由で信号A2と等しい。つまり三重化
回路の出力であるLSI100の論理出力信号D1
は、信号A1とB1(=D2=A2)とのどちら
か一方を選択回路切換入力信号C1(信号C1は
信号A2とA3の排他的論理和回路出力信号E2
の否定値に等しい。なぜならC1=2=2
B2。ここでB2=D3=A3。)の指示により
決定された信号である。しかも信号C1が論理
“0”である場合は信号B1(A2)にかかわら
ず、信号D1は信号A1に等しいため(表2より
明らか)、信号C1が論理“1”となる場合、つ
まり信号A2と信号A3の排他的論理和が論理
“0”となる(信号A2と信号A3とが同値であ
る)場合のみ信号B1(A2)を出力する他は信
号A1が出力されることになる(各段LSIの入出
力信号の遷移を表4に示す)。[Table] Table 3 A1 A2 A3 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Functional circuits F10 and F20 constituting the triplex circuit
and output signal A1 of functional circuits F10, F20 and F30 when F30 is operating normally or at most 1 LSI functional circuit is abnormal;
There are at most eight combinations of values that A2 and A3 can take (specifically shown in Table 3). Table 3
It will be explained next that the triplex circuit output (logic output signal D1 of LSI 100 in the figure) is a correct value according to majority logic for all combinations of signals A1, A2, and A3 shown in FIG. Since the selection circuit switching input terminal of the selection circuit S31 of the LSI is grounded, the logic output signal D3 of the LSI 300 is the signal A regardless of the logic input signal B3.
3 (as is clear from the function of the selection circuit in Table 2). Logic output signal D2 of next stage LSI 200
is also equal to signal A2 for the same reason. In other words, the logic output signal D1 of LSI 100 which is the output of the triplexing circuit
selects either one of the signals A1 and B1 (=D2=A2) The circuit switching input signal C1 (signal C1 is the exclusive OR circuit output signal E2 of the signals A2 and A3)
is equal to the negation of . Because C1=2=2
B2. Here B2=D3=A3. ) is the signal determined by the instruction. Moreover, when the signal C1 is a logic "0", the signal D1 is equal to the signal A1 regardless of the signal B1 (A2) (as is clear from Table 2), so when the signal C1 is a logic "1", that is, the signal A2 The signal A1 is output except that the signal B1 (A2) is output only when the exclusive OR of the Table 4 shows the transition of the input/output signals of the stage LSI).
【表】
表4で示される三重化回路出力(LSI100の
論理出力信号D1)がA1,A2およびA3の3
つの組合せのすべてのケースでA1,A2および
A3の多数決論理による出力値と等しいことは表
4から明らかである。
本実施例によると、三重化された機能回路出力
信号A1,A2およびA3の多数決出力は、三重
化回路の出力となる論理出力信号D1を出力する
LSI100を除く他のLSI(200と300)の
機能回路出力信号A2とA3が一致する場合は
LSI200の機能回路出力A2となり、A2とA
3が不一致の場合はLSI100の機能回路出力A
1となる。本実施例が多数決論理による正しい出
力を満足していることは表4から明らかで、これ
は5頁で記述した原理が本実施例回路で実現され
ていることを示す。
また故障検出について説明すると、三重化され
た機能回路出力信号A1,A2およびA3のいず
れかが他の2出力と異なる出力を示す場合は、い
ずれの組合せにおいても故障出力端子の出力信号
のいずれかが論理“0”となり、これらの端子の
ワイヤードオア論理で接続される故障処理回路2
50の入力信号が論理“0”となり故障が検出さ
れることは先の説明から明らかである。
なお本実施例ではLSI100の論理出力を三重
化回路の出力とする例で示したが、三重化回路出
力をLSI200またはLSI300の論理出力で実
現する場合も、選択回路切換入力端子と選択回路
切換出力端子との接続を変えるだけで容易に実現
できることは明らかである。
また以上の説明は第1図の実施例の機能回路2
出力のうち1出力についてのみ着目して行われた
が、第1図から明らかなように機能回路出力に対
応して接続される故障検出および多数決出力のた
めの付加回路と結線はすべて同一構成であるため
残りの1出力についても動作の正しいことがいえ
る。さらに本実施例の機能回路出力は2出力で示
したが、3以上であつても同様である。
本実施例では特に言及しなかつたが、2重故障
を除外するならば、選択回路S11および論理出
力端子101の故障をのぞく他のすべての端子と
回路との故障についても多数決論理による正しい
出力が可能であることが以上の説明から確認でき
る。
本発明には三重化回路の故障検出および多数決
出力のための部分回路をLSIに内蔵して接続する
だけで故障検出および多数決出力が可能となるこ
とにより、多数決回路用LSIを不要にしパツケー
ジ内に占める面積が小さくなる効果がある。さら
に三重化回路を構成する本発明によるLSIは同一
構成であり、端子数はたかだか機能回路数の2倍
(+3)である。[Table] The triplex circuit output (Logic output signal D1 of LSI100) shown in Table 4 is 3 of A1, A2, and A3.
It is clear from Table 4 that in all cases of the two combinations, the output values of A1, A2 and A3 are equal to the output values of the majority logic. According to this embodiment, the majority output of the triplexed functional circuit output signals A1, A2, and A3 outputs the logical output signal D1, which is the output of the triplexed circuit.
If the functional circuit output signals A2 and A3 of other LSIs (200 and 300) other than LSI100 match,
It becomes the functional circuit output A2 of LSI200, and A2 and A
If 3 does not match, LSI100 functional circuit output A
It becomes 1. It is clear from Table 4 that this embodiment satisfies the correct output based on majority logic, which shows that the principle described on page 5 is realized in the circuit of this embodiment. Regarding failure detection, if any one of the triplexed functional circuit output signals A1, A2, and A3 shows an output different from the other two outputs, in any combination, either one of the output signals of the failure output terminal becomes the logic “0”, and the fault processing circuit 2 is connected by wired OR logic of these terminals.
It is clear from the above description that the input signal 50 becomes logic "0" and a fault is detected. In this example, the logic output of LSI100 is shown as the output of the triplexing circuit, but when realizing the triplexing circuit output with the logic output of LSI200 or LSI300, the selection circuit switching input terminal and the selection circuit switching output It is clear that this can be easily achieved by simply changing the connection to the terminal. Further, the above explanation is based on the functional circuit 2 of the embodiment shown in FIG.
This was done by focusing on only one of the outputs, but as is clear from Figure 1, the additional circuits and connections for fault detection and majority output connected to the functional circuit outputs all have the same configuration. Therefore, it can be said that the operation is correct for the remaining one output as well. Furthermore, although the functional circuit outputs in this embodiment are shown as two outputs, the same applies even if there are three or more outputs. Although not specifically mentioned in this embodiment, if double failures are excluded, correct outputs based on majority logic will also occur for failures of all other terminals and circuits, except for failures of the selection circuit S11 and the logic output terminal 101. It can be confirmed from the above explanation that this is possible. In the present invention, a partial circuit for fault detection and majority decision output of a triplexed circuit is built into an LSI, and fault detection and majority decision output are possible just by connecting it, thereby eliminating the need for an LSI for the majority decision circuit and integrating it into the package. This has the effect of reducing the area occupied. Furthermore, the LSIs according to the present invention constituting the triplexed circuit have the same configuration, and the number of terminals is at most twice (+3) the number of functional circuits.
図は本発明の一実施例を示すLSIによる三重化
回路のブロツク図である。
図において、100,200,300……
LSI、F10,F20,F30……機能回路、S
11,S12,S21,S22,S31,S32
……選択回路、X13,X14,X23,X2
4,X33,X34……排他的論理和回路、N1
5,N25,N35……否定的論理和回路、P1
6,P26,P36……論理積回路、103,1
04,203,204,303,304……論理
入力端子、101,102,201,202,3
01,302……論理出力端子、105,20
5,305……故障出力端子、106,206,
306……選択回路切換出力端子、110,21
0,310……選択回路切換入力端子、107,
108,109,207,208,209,30
7,308,309……機能回路入力端子、50
……前段機能回路、150……後段機能回路、2
50……故障処理回路、A1,A2,A3……機
能回路出力信号、B1,B2,B3……論理入力
信号、C1,C2,C3……選択回路切換入力信
号、D1,D2,D3……選択回路出力信号、E
1,E2,E3……排他的論理和回路出力信号。
The figure is a block diagram of a triplex circuit using an LSI, showing one embodiment of the present invention. In the figure, 100, 200, 300...
LSI, F10, F20, F30...Functional circuit, S
11, S12, S21, S22, S31, S32
...Selection circuit, X13, X14, X23, X2
4, X33, X34...exclusive OR circuit, N1
5, N25, N35...Negative OR circuit, P1
6, P26, P36...AND circuit, 103,1
04, 203, 204, 303, 304...Logic input terminal, 101, 102, 201, 202, 3
01,302...Logic output terminal, 105,20
5,305...Failure output terminal, 106,206,
306...Selection circuit switching output terminal, 110, 21
0,310...Selection circuit switching input terminal, 107,
108, 109, 207, 208, 209, 30
7,308,309...Functional circuit input terminal, 50
...Front stage functional circuit, 150...Late stage functional circuit, 2
50... Failure processing circuit, A1, A2, A3... Functional circuit output signal, B1, B2, B3... Logic input signal, C1, C2, C3... Selection circuit switching input signal, D1, D2, D3... Selection circuit output signal, E
1, E2, E3...Exclusive OR circuit output signals.
Claims (1)
ユニツトを接続した三重化回路において、自論理
回路と、外部の論理回路からの信号と前記自論理
回路からの信号とを比較する比較回路と、前記外
部の論理回路からの信号と前記自論理回路からの
信号とを外部からの指示信号により選択し出力す
る選択回路とを含む論理回路ユニツトを3個具備
し、前記3個の論理ユニツトのうち前段の論理ユ
ニツトの選択回路からの信号を後段の論理ユニツ
トの選択回路に前記外部の論理回路からの信号と
して与えるように順次巡回的に接続する接続手段
と、3個の前記比較回路からのそれぞれの不一致
信号を故障信号として論理和をとり出力する手段
と、前記3個のうち特定の論理ユニツトの前段の
論理ユニツト内の比較回路の比較結果信号を前記
特定の論理ユニツトの選択回路の選択指示信号と
して与えるとともに他の2個の論理ユニツトの選
択回路の選択指示信号としてそれぞれの論理回路
からの信号を出力するように選択指示信号を与え
る手段と、前記特定の論理ユニツトの選択回路か
らの出力信号を三重化回路の出力とする出力手段
とを含むことを特徴とする三重化回路。1 In a triplex circuit connecting three identical logic units that input and process the same signal, a comparator circuit that compares a signal from an external logic circuit with a signal from the own logic circuit; , comprises three logic circuit units each including a selection circuit that selects and outputs a signal from the external logic circuit and a signal from the own logic circuit according to an instruction signal from the outside; connecting means for sequentially and cyclically connecting signals from the selection circuit of the logic unit in the preceding stage to the selection circuit of the logic unit in the succeeding stage as signals from the external logic circuit; Means for logical suming and outputting each mismatch signal as a failure signal; and means for selecting a comparison result signal of a comparison circuit in a logic unit preceding a specific logic unit among the three logic units to a selection circuit of the specific logic unit. means for providing a selection instruction signal so as to output the signal from each logic circuit as an instruction signal and as a selection instruction signal for the selection circuit of the other two logic units; A triplexing circuit comprising output means for outputting an output signal from the triplexing circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16242678A JPS5588429A (en) | 1978-12-26 | 1978-12-26 | Tripled circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16242678A JPS5588429A (en) | 1978-12-26 | 1978-12-26 | Tripled circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5588429A JPS5588429A (en) | 1980-07-04 |
JPS6136412B2 true JPS6136412B2 (en) | 1986-08-18 |
Family
ID=15754371
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16242678A Granted JPS5588429A (en) | 1978-12-26 | 1978-12-26 | Tripled circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5588429A (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2682251B2 (en) * | 1991-04-05 | 1997-11-26 | 株式会社日立製作所 | Multiplex controller |
-
1978
- 1978-12-26 JP JP16242678A patent/JPS5588429A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS5588429A (en) | 1980-07-04 |
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