JPS613288A - Manufacture of ic card - Google Patents

Manufacture of ic card

Info

Publication number
JPS613288A
JPS613288A JP59123115A JP12311584A JPS613288A JP S613288 A JPS613288 A JP S613288A JP 59123115 A JP59123115 A JP 59123115A JP 12311584 A JP12311584 A JP 12311584A JP S613288 A JPS613288 A JP S613288A
Authority
JP
Japan
Prior art keywords
common electrode
wiring board
lead
input
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59123115A
Other languages
Japanese (ja)
Inventor
Tamio Saito
斎藤　民雄
Yoshikatsu Fukumoto
福本　好克
Shuji Hiranuma
平沼　修二
Hiroshi Ohira
洋 大平
Masayuki Ouchi
正之 大内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP59123115A priority Critical patent/JPS613288A/en
Publication of JPS613288A publication Critical patent/JPS613288A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07745—Mounting details of integrated circuit chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Credit Cards Or The Like (AREA)

Abstract

PURPOSE:To prevent an IC chip from being broken by static electricity by providing a common electrode to which plural lead-out lines are connected in common at an outer part of an organic sheet, and disconnecting the lead-out lines and common electrode after a press process. CONSTITUTION:A wiring board 14 which mounts an IC chip 11 and has a wiring pattern 12 and an input/output terminal 13 formed is formed projecting partially from organic sheets 15 and 16 as shown by 14a. Then, the lead-out lines 17 each connected to the input/output terminal 13 at one terminal and the common electrode 18 connected to the other-terminal sides of the lead-out lines 17 in common are formed on the projection part 14a of the wiring board 14. An opening 15a is formed in one prganic material sheet 15 opposite the input/output terminal 13. The projection part 14a of the wiring board 14 is cut together with the lead-out lines 17 after the press process to disconnect the lead-out line 17 and common electrode 18.

Description

【発明の詳細な説明】 ［発明の技術分野］ この発明はＩＣカードの製造方法に係り、特にプレス工
程における静電気による素子破壊を防止する方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing an IC card, and more particularly to a method for preventing element destruction due to static electricity during a pressing process.

［発明の技術的背景とその問題点コ ＩＣカードはカード状基体にＣＰＬＪ、メモリ等のＩＣ
チップを組込んで従来からの磁気カードを発展させたよ
うな機能を持たせたものであり、キャッシュカードその
他への応用が考えられている。[Technical background of the invention and its problems] An IC card has a card-like base with ICs such as CPLJ and memory.
It incorporates a chip to give it functionality similar to that of a conventional magnetic card, and is being considered for application in cash cards and other applications.

このようなＩＣカードはＩＣチップを内蔵しない通常の
磁気カード等との互換性維持、例えばエンボスの形成や
、磁気テープの貼着を可能とする等の要求から、カード
状基体の少なくとも表面部材は塩、化ビニールのような
有機物のシートであることが望まれる。Such IC cards are required to maintain compatibility with ordinary magnetic cards that do not have built-in IC chips, for example, to be able to form embossing and attach magnetic tape, so at least the surface material of the card-like substrate is A sheet of organic material such as salt or vinyl chloride is preferable.

第１図は従来のＩＣカードの一例を示すもので、ＩＣチ
ップ１を搭載し、かつ配線パターン２およびＩＣチップ
１に配線パターン２を介して接続された入出力端子３が
形成された配線基板４を、２枚の有機物シート５，６で
挟み、プレスにより一体化した構造となっている。FIG. 1 shows an example of a conventional IC card, in which a wiring board is mounted with an IC chip 1, and has a wiring pattern 2 and an input/output terminal 3 connected to the IC chip 1 via the wiring pattern 2. 4 is sandwiched between two organic sheets 5 and 6 and integrated by pressing.

しかしながら、このようなＩＣカードの製造に際しては
、プレス工程時に有機物シート５，６のピエゾ効果で静
電気が発生し、これによってＩＣチップ１の破壊を招き
易いという問題がある。However, when manufacturing such an IC card, there is a problem in that static electricity is generated due to the piezoelectric effect of the organic sheets 5 and 6 during the pressing process, which tends to lead to destruction of the IC chip 1.

ＩＣチップ１の構造は例えばその一部の断面を第２図に
示すように、半導体ウェハ７上に拡散によりチャネル８
が形成され、その上に酸化ｌｌ１９、さらにその上にゲ
ート電極１０が形成されている。The structure of the IC chip 1 is such that a channel 8 is formed on a semiconductor wafer 7 by diffusion, as shown in FIG.
is formed, oxide 119 is formed thereon, and gate electrode 10 is further formed thereon.

これはＭＯＳキャパシタである。ゲート電極１０とチャ
ネル８またはウェハ７との簡にはブレークダウン電圧が
存在し、この間の電圧が一定値以上になると酸化ｌ１１
９が破壊される。従って、上述のように静電気が発生す
ると、第２図の端子Ａ、Ｂ開に静電気に基く高電圧が印
加されることにより酸化膜９が破壊され、Ｉ’　Ｃチッ
プ１が不良となることがある。This is a MOS capacitor. There is a breakdown voltage between the gate electrode 10 and the channel 8 or wafer 7, and when the voltage between this voltage exceeds a certain value, oxidation occurs.
9 is destroyed. Therefore, when static electricity is generated as described above, a high voltage based on static electricity is applied to the terminals A and B in FIG. be.

［発明の目的〕 この発明の目的は、プレス工程において発生する静電気
によりＩＣチップが破壊されるおそれのないＩＣチップ
の製造方法を提供することである。[Object of the Invention] An object of the present invention is to provide a method for manufacturing an IC chip in which there is no fear that the IC chip will be destroyed by static electricity generated during the pressing process.

［発明の概要コ この発明は、ＩＣチップを搭載し、かつ該ＩＣチップに
接続される入出力端子を有する配線基板を２枚の有機物
シートで挟み、これら配線基板および有機物シートをプ
レスにより一体化してＩＣカードを製造するに際し、入
出力端子の全部または所定の一部に接続された複数の引
出し線と、これらの引出し線を有機物シートの外方で共
通接続　。[Summary of the Invention] This invention involves sandwiching a wiring board on which an IC chip is mounted and having input/output terminals connected to the IC chip between two organic sheets, and integrating the wiring board and the organic sheet by pressing. When manufacturing IC cards, multiple lead lines are connected to all or a predetermined part of the input/output terminals, and these lead lines are commonly connected outside the organic material sheet.

する共通電極を設け、配線基板と有機物シートとのプレ
ス工程の後に引出し線と共通電極とを切離すことを特徴
としている。The present invention is characterized in that a common electrode is provided, and the lead wire and the common electrode are separated after the wiring board and the organic sheet are pressed together.

すなわち、共通電極によって入出力端子のうち少なくと
もその間に高電圧が印加されるとＩＣチップを破壊させ
るような端子を短絡しておき、その状態でプレスを行な
うのである。この場合、共通電極を特別に設けてもよい
が、入出力端子にメッキを施す場合、メッキ用電極がち
ょうど入出力端子に共通接続された形で設けられるので
、このメッキ用電極をプレス工程が終了するまで残して
おくことにより、これを静電気の影響を防止するための
共通電極としても流用することができる。That is, at least among the input and output terminals, terminals that would destroy the IC chip if a high voltage is applied therebetween are short-circuited by the common electrode, and pressing is performed in this state. In this case, a common electrode may be specially provided, but when plating the input/output terminals, the plating electrodes are provided in a form that is just commonly connected to the input/output terminals, so the plating electrodes are used in the pressing process. By leaving it until the end of the process, it can also be used as a common electrode to prevent the effects of static electricity.

［発明の効果］ この発明によれば、プレス時に有機物シートのピエゾ効
果による静電気が発生しても、この静電気に基く高電圧
は共通電極によって短絡され、ＩＣチップには印加され
ないので、ＩＣチップの破壊を防止することができる。[Effects of the Invention] According to this invention, even if static electricity is generated due to the piezo effect of the organic sheet during pressing, the high voltage based on this static electricity is short-circuited by the common electrode and is not applied to the IC chip. Destruction can be prevented.

また、メッキ用電極を共通電極として流用すれば、特に
特別な工程を追加する必要がなく、共通電極と引出し線
とを切離す工程をずらすだけでその目的を達成できると
いう利点がある。Further, if the plating electrode is used as the common electrode, there is an advantage that there is no need to add any special process, and the purpose can be achieved simply by shifting the process of separating the common electrode and the lead wire.

［発明の実施例］ 第３図〜第５図はこの発明の一実施例のＩＣカードの製
造方法を説明するためのものである。[Embodiment of the Invention] FIGS. 3 to 5 are for explaining a method of manufacturing an IC card according to an embodiment of the invention.

第３図において、ＩＣチップ１１を搭載し、かつ配線パ
ターン１２および入出力端子１３が形成された配線基板
１４は、有機物シート１５．１６から１４ａで示す如く
一部が突出して形成されている。そして、この配線基板
１４の突出部１４ａ上に、各一端が入出力端子１３に接
続された引出し線１７と、これらの引出し線１７の各他
端に共通接続された共通電極１８が形成されている。一
方の有機物シート１５には、入出力端子１３に対向した
位置に開口１５ａが設けられている。In FIG. 3, a wiring board 14 on which an IC chip 11 is mounted and on which a wiring pattern 12 and an input/output terminal 13 are formed is formed so that a portion thereof protrudes from organic sheets 15, 16 to 14a. Then, on the protrusion 14a of the wiring board 14, lead wires 17 each having one end connected to the input/output terminal 13, and a common electrode 18 commonly connected to each other end of these lead wires 17 are formed. There is. One organic sheet 15 is provided with an opening 15 a at a position facing the input/output terminal 13 .

引出し１１７および共通電極１°８は、入出力端子１３
上に金メッキ等を施す場合に用いられるメッキ用電極で
あり、通常はメッキ工程の後、配線基板１４のテストや
アッセンブリ後のテストに邪魔とならないように直ちに
除去されるものあるが、この発明では第４図に示すよう
に配ａｔ基板１１゜有機物シート１５．１６を重ねてプ
レスする際にも、これらの引出し線１７および共通電極
１８を残しておく。このようにすると、プレスによる圧
力で有機物シート１５．１６からピエゾ効果（圧電効果
）によって高電圧の静電気が発生しても、共通電極１８
で短絡されるため、入出力端子１３の相互間に印加され
ることはない。これは第２図でいえば端子Ａ、Ｂ間を短
絡したことに相当する。The drawer 117 and the common electrode 1°8 are connected to the input/output terminal 13
This is a plating electrode used when applying gold plating, etc. on the top, and is usually removed immediately after the plating process so as not to interfere with the test of the wiring board 14 or the test after assembly. As shown in FIG. 4, even when pressing the organic material sheets 15 and 16 on the distribution substrate 11°, these lead lines 17 and the common electrode 18 are left. In this way, even if high voltage static electricity is generated from the organic sheet 15, 16 due to the piezo effect (piezoelectric effect) due to pressure from the press, the common electrode 18
Since the voltage is short-circuited between the input and output terminals 13, no voltage is applied between the input and output terminals 13. This corresponds to short-circuiting between terminals A and B in FIG. 2.

従って、例えば酸化膜９に高電圧が印加されることはな
く、その破壊が防止される。Therefore, for example, high voltage is not applied to the oxide film 9, and its destruction is prevented.

このようにプレス工程が終了した後は、引出し線１７お
よび共通電極１８は不要であり、ＩＣチップ１１の正常
動作を妨げるので、第５図に示すように配線基板１４の
突出部１４ａを引出し線１７とともに切断して、引出し
線１７と共通電極１８とを切離す。この場合、配線基板
１４の突出部１４ａを切断面が有機物シート１５．１６
の端面と一致するように切断すれば、美観が損われるこ
とはない。こうして配線基板１４と有機物シート１５．
１６とが一体化されることにより、ＩＣカードが完成す
る。この状態では入出力端子１３は有機物シート１５に
形成された開口１５ａより露出し、外部装置（カード読
取り装置等）との接続が可能な状態となる。After the pressing process is completed in this way, the lead wire 17 and the common electrode 18 are unnecessary and will interfere with the normal operation of the IC chip 11. Therefore, as shown in FIG. 17 to separate the lead wire 17 and the common electrode 18. In this case, the cut surface of the protrusion 14a of the wiring board 14 is the organic sheet 15.16.
If the cut is made to match the end face of the cutter, the aesthetic appearance will not be affected. In this way, the wiring board 14 and the organic sheet 15.
16, an IC card is completed. In this state, the input/output terminal 13 is exposed through the opening 15a formed in the organic sheet 15, and is ready for connection with an external device (such as a card reader).

以上のように、この発明によればプレス工程において発
生する静電気によるＩＣチップの破壊が防止され、信頼
性の高いＩＣカードの製造が可能となる。As described above, according to the present invention, IC chips are prevented from being destroyed by static electricity generated during the pressing process, and highly reliable IC cards can be manufactured.

この発明は上記実施例に限定されるものではなく、その
要旨を逸脱しない範囲で種々変形実施力（可能であり、
例えば実施例ではメッキ用共通電極を静電気の影響によ
るＩＣチップの破壊防止に利用したが、専用の共通電極
を用意してもよいことは勿論である。その場合、共通電
極は入出力端子の全てに接続されている必要はな（、静
電気による高電圧が印加されるおそれのない端子や、高
電圧が印加されてもＩＣチップの破壊を招くおそれのな
い端子を除く所定の一部の端子にのみ接続されていれば
よい。This invention is not limited to the above-described embodiments, and may be modified in various ways without departing from the gist of the invention.
For example, in the embodiment, the common electrode for plating was used to prevent destruction of the IC chip due to the influence of static electricity, but it is of course possible to prepare a dedicated common electrode. In that case, the common electrode does not need to be connected to all input/output terminals (terminals where there is no risk of high voltage being applied due to static electricity, or terminals where there is a risk of damaging the IC chip even if high voltage is applied). It is only necessary to connect only to some predetermined terminals excluding terminals that are not present.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来のＩＣカードの製造工程における問題点を
説明するためのＩＣカードの展開斜視図、第２図はＩＣ
チップの一部の構造を示す断面図、第３図〜第５図はこ
の発明の一実施例のＩＣカードの製造工程を説明するた
めの図である。 １１・・・ＩＣチップ、１２・・・配線パターン、１３
・・・入出力端子、１４・・・配線基板、１５．１６・
・・有機物シート、１７・・・引出し線、１８・・・共
通電極。 出願人代理人　弁理士　鈴江武彦 第１図 第３図 第４図Figure 1 is an exploded perspective view of an IC card to explain problems in the conventional IC card manufacturing process, and Figure 2 is an exploded perspective view of an IC card.
3 to 5, which are cross-sectional views showing the structure of a part of the chip, are diagrams for explaining the manufacturing process of an IC card according to an embodiment of the present invention. 11...IC chip, 12...wiring pattern, 13
...Input/output terminal, 14...Wiring board, 15.16.
...Organic material sheet, 17...Leader line, 18...Common electrode. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 3 Figure 4

Claims (3)

【特許請求の範囲】[Claims] （１）ＩＣチップを搭載し、かつ該ＩＣチップに接続さ
れる入出力端子を有する配線基板を２枚の有機物シート
で挟み、これら配線基板および有機物シートをプレスに
より一体化してＩＣカードを製造するに際し、前記入出
力端子の全部または所定の一部に接続された複数の引出
し線と、これらの引出し線を有機物シートの外方で共通
接続する共通電極を設け、前記配線基板と有機物シート
とのプレス工程の後に前記引出し線と共通電極とを切離
すことを特徴とするＩＣカードの製造方法。(1) A wiring board on which an IC chip is mounted and which has input/output terminals connected to the IC chip is sandwiched between two organic sheets, and these wiring boards and organic sheets are integrated by pressing to manufacture an IC card. In this case, a plurality of lead wires connected to all or a predetermined part of the input/output terminals and a common electrode that connects these lead wires in common on the outside of the organic sheet are provided, and the connection between the wiring board and the organic sheet is provided. A method for manufacturing an IC card, characterized in that the lead wire and the common electrode are separated after the pressing step. （２）共通電極はＩＣチップに接続される入出力端子の
メッキ用電極であることを特徴とする特許請求の範囲第
１項記載のＩＣカードの製造方法。(2) The method for manufacturing an IC card according to claim 1, wherein the common electrode is an electrode for plating input/output terminals connected to the IC chip. （３）配線基板を有機物シートとのプレス時に有機物シ
ートから外方に一部が突出するように形成して、共通電
極および引出し線の共通電極近傍部分をこの配線基板の
突出部上に形成し、プレス工程の後に配線基板の突出部
を引出し線とともに切断することにより引出し線と共通
電極とを切離すことを特徴とする特許請求の範囲第１項
記載のＩＣカードの製造方法。(3) The wiring board is formed so that a part thereof protrudes outward from the organic sheet when pressed with the organic sheet, and the common electrode and the portion of the lead wire near the common electrode are formed on the protruding part of the wiring board. 2. The method of manufacturing an IC card according to claim 1, wherein the lead wire and the common electrode are separated by cutting the protruding portion of the wiring board together with the lead wire after the pressing step.
JP59123115A 1984-06-15 1984-06-15 Manufacture of ic card Pending JPS613288A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59123115A JPS613288A (en) 1984-06-15 1984-06-15 Manufacture of ic card

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59123115A JPS613288A (en) 1984-06-15 1984-06-15 Manufacture of ic card

Publications (1)

Publication Number Publication Date
JPS613288A true JPS613288A (en) 1986-01-09

Family

ID=14852547

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59123115A Pending JPS613288A (en) 1984-06-15 1984-06-15 Manufacture of ic card

Country Status (1)

Country Link
JP (1) JPS613288A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4924076A (en) * 1987-07-14 1990-05-08 Mitsubishi Denki Kabushiki Kaisha Memory card housing a semiconductor device
US5250470A (en) * 1989-12-22 1993-10-05 Oki Electric Industry Co., Ltd. Method for manufacturing a semiconductor device with corrosion resistant leads

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4924076A (en) * 1987-07-14 1990-05-08 Mitsubishi Denki Kabushiki Kaisha Memory card housing a semiconductor device
US5250470A (en) * 1989-12-22 1993-10-05 Oki Electric Industry Co., Ltd. Method for manufacturing a semiconductor device with corrosion resistant leads

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