JPS6130078A - Microwave high-output transistor - Google Patents
Microwave high-output transistorInfo
- Publication number
- JPS6130078A JPS6130078A JP15061084A JP15061084A JPS6130078A JP S6130078 A JPS6130078 A JP S6130078A JP 15061084 A JP15061084 A JP 15061084A JP 15061084 A JP15061084 A JP 15061084A JP S6130078 A JPS6130078 A JP S6130078A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- resistance
- layer
- gate electrode
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 239000004065 semiconductor Substances 0.000 claims abstract description 9
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 10
- 230000010355 oscillation Effects 0.000 abstract description 10
- 239000012535 impurity Substances 0.000 abstract description 5
- 238000009792 diffusion process Methods 0.000 description 10
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 9
- 238000004364 calculation method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 241001494479 Pecora Species 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明はマイクロ波高出力トランジスタに関し。[Detailed description of the invention] (Industrial application field) The present invention relates to a microwave high power transistor.
特にマイクロ波帯高出力用ヒ化ガリウム電界効果トラン
ジスタ（以下ＧａＡｓ Ｆ Ｅ Ｔと記す）に関する。In particular, the present invention relates to a gallium arsenide field effect transistor (hereinafter referred to as GaAs FET) for high output power in the microwave band.
（従来技術）
ＧａＡｓ Ｆ Ｅ Ｔは年々高周波数化、高ゲイン化が
進み、それに伴い素子内の浮遊容量の低減、高周波直列
抵抗Ｒ８の低減、熱抵抗ａｔｈの低減など、種々の技術
開発がなされ、現在ではＸ帯の領域まで安定的に製品と
供給できるようになってきた。(Prior art) As the frequency and gain of GaAs FETs progresses year by year, various technological developments have been made to reduce stray capacitance within the device, reduce high frequency series resistance R8, and reduce thermal resistance ath. Currently, we are able to stably supply products up to the X-band range.
また従来から生産されているＣ帯の製品も高効率。In addition, conventionally produced C-band products are also highly efficient.
高ゲインが要求されるようになシ、それに対応する製品
の開発が急がれている。As high gain is increasingly required, there is an urgent need to develop products that meet this demand.
そこで、Ｘ帯以上の＾い周波数用に開発された技術を用
いてＣ″ｍｍ薬品涯することが考えられるが、一般にＸ
帯用の技術を用いたＧａＡｓ Ｆ ＥＴはＣ帯ではゲイ
ンが高くなシすぎ１回路状態や周波数によってはＦＥＴ
内部での帰還によシ発躯を起す可能性が大である０
第３図（ａ）、 （ｂ）は、従来の高出力ＧａＡｓＦＥ
Ｔの一例の平面図及びＡ−Ａ’断面図でおる。第３図（
ａ）、 （ｂ）において、高抵抗のＧ ａ Ａ ｓ基板
１上にソースミ極２．ゲート電極３．ドレイン電極４が
配置され、また各電極がクシ形に交錯した部分直下が、
活性動作領域であって破線５はその領域線である。Therefore, it is possible to treat C″mm chemicals using technology developed for frequencies higher than the X band, but in general,
GaAs FETs using C-band technology do not have high gain in the C-band, so depending on the circuit condition and frequency, the FET
There is a high possibility that the internal feedback will cause an eruption.
These are a plan view and an AA' cross-sectional view of an example of T. Figure 3 (
In a) and (b), a source mirror 2. is placed on a high resistance GaAs substrate 1. Gate electrode 3. Directly below the part where the drain electrode 4 is arranged and each electrode intersects in a comb shape,
This is the active operation region, and the broken line 5 is the region line.
上記構造のＦＥＴがＸ帯で必要な特性を得た場合の最大
有能電力利得（ＭＡＧ）のシュミレーシ冒ンを実際の製
品のＳパラメータをもとに行いその結果を第４図に示し
た。第４図に於て、実線部は発振に対して安定な領域で
あシ、また破線部は動作が不安定になり易く、回路状態
１周波数によっては発振を起す領域でおる。第４図によ
シ前記ＦＥ’Ｉ’の安定な動作領域は１１ ＧＨｚ以上
であシ２３ＧＨｚでゲインがＯｄＢとなることがわかる
。A simulation of the maximum available power gain (MAG) when the FET with the above structure obtains the necessary characteristics in the X band was performed based on the S parameters of the actual product, and the results are shown in FIG. In FIG. 4, the solid line portion is a stable region against oscillation, and the broken line portion is a region where operation tends to become unstable and oscillation may occur depending on the circuit state and frequency. It can be seen from FIG. 4 that the stable operating range of the FE'I' is above 11 GHz, and the gain becomes OdB at 23 GHz.
すなわち従来のままでは１１ＧＨｚ以下では安定な動作
は期待できず問題である。That is, with the conventional technology, stable operation cannot be expected at frequencies below 11 GHz, which is a problem.
（発明の目的）
本発明の目的は、Ｘ帯用に開発されたＧ ａ Ａ ５Ｆ
ＥＴｆ、Ｘ帯での性能を損わずにＣ帯においても発振に
対して安定な状態で、かつ高ゲインを実現し高帯域に使
用できるＧａＡｓＦＥＴを提供することにある。(Object of the invention) The object of the present invention is to obtain the G a A 5F developed for
The object of the present invention is to provide a GaAsFET that is stable against oscillation even in the C band without impairing its performance in the ETF and X bands, achieves high gain, and can be used in a high band.
（作用）
従来のＸ帯用の技術によ多形成したＧ ａ Ａ ｓ Ｆ
ＥＴはＣ帯ではゲインが高くなりすぎ１回路状態や周波
数によりＦＥＴ内部での帰還により発振を起す可能性が
大で実用に適さなかった。(Function) G a A s F formed using conventional X-band technology
The gain of the ET becomes too high in the C band, and depending on the circuit condition and frequency, there is a large possibility that oscillation will occur due to feedback inside the FET, making it unsuitable for practical use.
しかし本発明によれば、ゲートパッド直下に有限な抵抗
値を持つ拡散層が形成され、該拡散層は高抵抗ＧａＡｓ
基板を貫通して形成されているので、本発明によるＧａ
Ａｓ ＦＥＴを半導体素子用容器に搭載すれば、ゲート
電極が半導体素子用容器の接地電位と接続され、結果と
してゲート電極と接地電極間に電気抵抗を形成したこと
になる。この電気抵抗は拡散層の不純物濃度を制御する
ことによシ適当な抵抗値とすることが出来るので、この
抵抗値を変えることＫより広い帯域にわたって発振の起
らない安定領域を有するＧａＡｓＦＥＴが得られる。However, according to the present invention, a diffusion layer having a finite resistance value is formed directly under the gate pad, and the diffusion layer is made of high resistance GaAs.
Since the Ga layer according to the present invention is formed through the substrate,
When the As FET is mounted in a semiconductor device container, the gate electrode is connected to the ground potential of the semiconductor device container, and as a result, an electric resistance is formed between the gate electrode and the ground electrode. This electrical resistance can be set to an appropriate resistance value by controlling the impurity concentration of the diffusion layer, so by changing this resistance value, a GaAsFET with a stable region in which oscillation does not occur over a wider band than K can be obtained. It will be done.
（実施例）
以下、本発明の実施例について、図面を参照して説明す
る。(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.
第１図＋り、 （ｂ）は本発明の一実施例の平面図及び
Ｂ−Ｂ’断面図である０第１図（ａ）において、１は高
抵抗Ｇ ａ Ａ ｓ 基板、 ２Ｆｉソース電極、３
はゲート電極、４はドレイン電極である。各電極がクシ
形に交錯した部分直下が活性動作領域であシ破線５はそ
の領域線である０また第１図（ｂ）において、破線６け
動作活性領域である０また７はゲートパ、ド直下に形成
され有限な抵抗値を持つ不純物拡散層であり、この拡散
層は高抵抗Ｇ ａ Ａ ｓ基板１を貫通し裏面に達Ｌ７
ている。なお第１図（ａ）の破線８けゲート直下の拡散
層の領域を示し第１図（ｂ）の７に和尚する。Figure 1 (b) is a plan view and a BB' cross-sectional view of an embodiment of the present invention. In Figure 1 (a), 1 is a high resistance Ga As substrate, 2 is a Fi source electrode. ,3
4 is a gate electrode, and 4 is a drain electrode. The area directly below the part where the electrodes intersect in a comb shape is the active operating region, and the broken line 5 is the area line 0. In FIG. This is an impurity diffusion layer formed directly below and having a finite resistance value, and this diffusion layer penetrates the high resistance GaAs substrate 1 and reaches the back surface L7.
ing. Note that the region of the diffusion layer immediately below the 8-gate gate is indicated by the broken line in FIG. 1(a), and is referred to as 7 in FIG. 1(b).
第１図（ａ）、 （ｂ）に示す構造のＧａＡｓＦＢＴは
半導体素子用容器に搭載すると、ゲート電極が、前記拡
散層７を介して接地されることになり、この拡散層の不
純＊濃度を制御すればこの拡散層の抵抗値を適当な値に
することが出来る０
すなわち、ゲート電極と接地電極間の電気抵抗により広
い帯域にわたって発振を起すことなく動作させることが
できる０
第２図は第１図（ａ）、 （ｂ）に示したゲート電極を
抵抗を介して接地電位に接続した本実施例のＧ ａ Ａ
５ＦＥＴで抵抗値を２０００としたときの最大有能電
力利得（ＭＡＧ）の計算結果を示す図である０第２図に
おいて実線が安定な帯域、破線が不安定な帯域を意味す
る。第２図では今回のシーミレーシ、ンで計算可能な２
ＧＨｚから６ＧＨｚまでが動作の安定な領域となってお
シ、このときはゲイン１２〜１４ｄＢが得られておシ、
また２２．５ＧＨｚでＯｄＢとなっている０
この結果をゲートを抵抗を介して接地電位に接続しない
従来のＧａＡｓ Ｆ Ｅ Ｔの結果を示す第４図と比較
すると第２図に示す本実施例ではゲインＯｄＢの周波数
では従来の第４図のものに対し５００ＭＨｚ低下してい
るが、１１〜１６ＧＨｚでは殆んど両者は変っていない
結果を示している。発振に対して安定でゲインＯｄ８以
上の得られる領域も第４図の従来例の１１〜２３ＧＨｚ
に対し第２図の本実施例では２〜６ ＧＨｚ、 １０．
５〜２２．５ ＧＨｚとなっており、また、２〜６ＧＨ
ｚでゲイン１２〜１４ｄＢを得ている。ゲート電極を２
０００の抵抗で接地した場合が、はるかに広帯域となっ
ていることがわかる。When the GaAsFBT having the structure shown in FIGS. 1(a) and 1(b) is mounted in a semiconductor device container, the gate electrode will be grounded via the diffusion layer 7, and the impurity* concentration of this diffusion layer will be reduced. If controlled, the resistance value of this diffusion layer can be set to an appropriate value. In other words, the electric resistance between the gate electrode and the ground electrode allows operation over a wide range without causing oscillation. G a A of this example in which the gate electrodes shown in Figure 1 (a) and (b) are connected to the ground potential via a resistor.
In FIG. 2, which is a diagram showing the calculation results of the maximum available power gain (MAG) when the resistance value is 2000 for a 5FET, the solid line indicates a stable band, and the broken line indicates an unstable band. In Figure 2, the current sea mileage is 2, which can be calculated using n.
The range from GHz to 6 GHz is stable operation, and at this time a gain of 12 to 14 dB can be obtained.
Moreover, when comparing this result with FIG. 4, which shows the results of a conventional GaAs FET in which the gate is not connected to the ground potential through a resistor, it is OdB at 22.5 GHz. At the frequency of the gain OdB, the frequency is lowered by 500 MHz compared to the conventional one shown in FIG. 4, but at 11 to 16 GHz, the results show that the two are almost unchanged. The range in which it is stable against oscillation and obtains a gain of Od8 or more is 11 to 23 GHz in the conventional example shown in Figure 4.
On the other hand, in this embodiment shown in FIG. 2, the frequency is 2 to 6 GHz, 10.
5 to 22.5 GHz, and 2 to 6 GHz
A gain of 12 to 14 dB is obtained at z. 2 gate electrodes
It can be seen that when grounded with a resistance of 000, the band is much wider.
（発明の効果）
以上説明したように１本発明によれば、１０ＧＨｚ以上
での高周波特性をほとんど損なう ことな（１０ＧＨｚ
以下で本発振に対して安定な領域を持つ高ゲインなマイ
クロ波帯ＧａＡｓＦＥＴを得ることができる。(Effects of the Invention) As explained above, according to the present invention, the high frequency characteristics at 10 GHz or higher are hardly impaired (10 GHz
A high-gain microwave band GaAsFET having a stable region for main oscillation can be obtained in the following manner.
第１図（ａ）、Φ）は本発明の一実施例の平面図及びＢ
−Ｂ’断面図、第２図は本発明の一実施例の構造のＧａ
Ａｓ ＦＥＴのＭＡＧの計算結果を示す図、第３図（ａ
）、（ｂ）は従来のマイクロ波帯高出力Ｇ ａ Ａ ５
ＦＥＴの平面図及びＡ−Ａ’断面図、第４図は従来のマ
イクロ波帯高出力ＧａＡｓ ＦＥＴのＭＡＧの計算結果
を示す図である。
１・・・・・・Ｇ ａ Ａ ｓ基板、２・・・・・・ソ
ース電極、３・・・・・・ゲート電極、４・・・・・・
ドレイン電極、５，６・・・・・・動ト電極直下の不純
物拡散による抵抗層の領域線（破線部）。
γ
第 ｌ 図
Σ＜、５＼ｍｌ／）毎 〔偽り
羊 ３ 図FIG. 1(a), Φ) is a plan view of an embodiment of the present invention, and FIG.
-B' sectional view, FIG. 2 is a Ga structure according to an embodiment of the present invention.
Figure 3 (a) is a diagram showing the calculation results of MAG of As FET.
), (b) are conventional microwave band high output G a A 5
A plan view and an AA' cross-sectional view of the FET, and FIG. 4 are diagrams showing calculation results of MAG of a conventional microwave band high-power GaAs FET. 1...G a As substrate, 2... Source electrode, 3... Gate electrode, 4...
Drain electrode, 5, 6... Area line (broken line part) of the resistance layer due to impurity diffusion directly under the active electrode. γ lth figure Σ<, 5\ml/) every [false sheep 3 figures
Claims (1)
びゲート電極を有するＧａＡｓＦＥＴにおいて、ゲート
電極直下に抵抗層領域を有し、該抵抗層領域は前記半導
体基板を貫通し、該抵抗層を形成した半導体チップを半
導体素子用容器に搭載することによって前記抵抗層を介
してゲート電極が半導体素子用容器の接地電位と接続さ
れ、前記ゲート電極と前記接地電極間に電気抵抗を形成
したことを特徴とするマイクロ波高出力トランジスタ。A GaAsFET having an active layer, a source/drain, and a gate electrode on a semi-insulating semiconductor substrate has a resistance layer region directly below the gate electrode, and the resistance layer region penetrates the semiconductor substrate to form the resistance layer. The gate electrode is connected to the ground potential of the semiconductor device container via the resistance layer by mounting the semiconductor chip in the semiconductor device container, and an electric resistance is formed between the gate electrode and the ground electrode. Microwave high output transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15061084A JPS6130078A (en) | 1984-07-20 | 1984-07-20 | Microwave high-output transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15061084A JPS6130078A (en) | 1984-07-20 | 1984-07-20 | Microwave high-output transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6130078A true JPS6130078A (en) | 1986-02-12 |
Family
ID=15500641
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15061084A Pending JPS6130078A (en) | 1984-07-20 | 1984-07-20 | Microwave high-output transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6130078A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0472357A2 (en) * | 1990-08-22 | 1992-02-26 | Mitsubishi Denki Kabushiki Kaisha | A semiconductor integrated circuit |
-
1984
- 1984-07-20 JP JP15061084A patent/JPS6130078A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0472357A2 (en) * | 1990-08-22 | 1992-02-26 | Mitsubishi Denki Kabushiki Kaisha | A semiconductor integrated circuit |
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