JPS61288218A - Semiconductor synchronous controller - Google Patents
Semiconductor synchronous controllerInfo
- Publication number
- JPS61288218A JPS61288218A JP60130176A JP13017685A JPS61288218A JP S61288218 A JPS61288218 A JP S61288218A JP 60130176 A JP60130176 A JP 60130176A JP 13017685 A JP13017685 A JP 13017685A JP S61288218 A JPS61288218 A JP S61288218A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- synchronizing signal
- synchronization signal
- semiconductor
- control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は２つ以上の半導体装置を同期制御する半導体同
期制御装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor synchronous control device that synchronously controls two or more semiconductor devices.
従来、この種の装置としては、第３図に示すものがあっ
た。第３図は従来の半導体同期制御装置１、他の半導体
装置７およびこれらの装置間の結線を示す。第３図にお
いて、２は第４図（８）に示す同期信号Ｔ１を発生する
同期信号発生回路、３は同期信号Ｔ１に同期して動作す
る制御回路、４は同期信号Ｔ１をバッファ５を介して出
力するための出力手段としての出力端子、６は制御回路
３から出力される第４図（Ｃ）に示す制御信号ａの出力
端子、８は出力端子４から出力される同期信号Ｔ１が入
力される入力端子、９は入力された同期信号ＴＩを第４
図（ｂ）に示す同期信号Ｔ２として出力するバッファ、
１０は同期信号Ｔ２に同期して動作する制御回路、１１
は出力端子６から出力された第４図（Ｃ）に示す制御信
号ａが入力される入力端子であり、半導体同期制御装置
１は同期信号発生回路２．制御回路３．出力端子４．バ
ッファ５および出力端子６から構成され、半導体装置７
は入力端子８．バッファ９．制御回路１０および入力端
子１１から構成される。Conventionally, there has been a device of this type as shown in FIG. FIG. 3 shows a conventional semiconductor synchronous control device 1, another semiconductor device 7, and connections between these devices. In FIG. 3, 2 is a synchronization signal generation circuit that generates the synchronization signal T1 shown in FIG. 6 is an output terminal for the control signal a shown in FIG. The input terminal 9 receives the input synchronization signal TI from the fourth
A buffer that outputs the synchronization signal T2 shown in FIG.
10 is a control circuit that operates in synchronization with the synchronization signal T2; 11
is an input terminal to which the control signal a shown in FIG. 4(C) output from the output terminal 6 is input, and the semiconductor synchronous control device 1 includes a synchronous signal generating circuit 2. Control circuit 3. Output terminal 4. Consisting of a buffer 5 and an output terminal 6, a semiconductor device 7
is input terminal 8. Buffer 9. It is composed of a control circuit 10 and an input terminal 11.
上述した同期信号Ｔ１．同期信号Ｔ２．制御信号ａの位
相関係を第４図に示す。第４図（Ｃ）に示す時間ｄはバ
ッファ９から出力される同期信号Ｔ２の同期信号Ｔ１に
対する遅れ時間であり、時間ｈは同期信号Ｔ１の立上が
りから制御信号ａが立下がるまでの制御信号ａの保持時
間を示す。The above-mentioned synchronization signal T1. Synchronization signal T2. FIG. 4 shows the phase relationship of the control signal a. The time d shown in FIG. 4(C) is the delay time of the synchronization signal T2 output from the buffer 9 with respect to the synchronization signal T1, and the time h is the delay time of the control signal a from the rise of the synchronization signal T1 to the fall of the control signal a. shows the retention time.
次に動作について第３図、第４図を用いて説明する。半
導体同期制御装置１の内部では、同期信号発生回路２に
より第４図（ａ）に示す同期信号Ｔ１が発生し、制御回
路３がこの同期信号Ｔ１に同期して動作すると共に、同
期信号Ｔ１は出力端子４から出力される。同期信号ＴＩ
は半導体装置７の入力端子８．バッファ９を経由して第
４図（ｂ）に示す同期信号Ｔ２となり、制御回路１０を
動作させる。半導体同期制御装置１の制御回路３は同期
信号ＴＩの立上がりで制御信号ａを出力端子６へ出力し
、半導体装置７の制御回路１０はこの制御信号ａを同期
信号Ｔ２の立上がりで取込むが、第４図（Ｃ１に示すよ
うに同期信号Ｔ２は同期信号ＴＩより時間ｄだけ位相が
遅れているので、制御信号ａの同期信号Ｔ２に対する保
持時間は同期信号Ｔ１に対する保持時間りより時間ｄだ
け短くなる。Next, the operation will be explained using FIGS. 3 and 4. Inside the semiconductor synchronous control device 1, a synchronous signal generating circuit 2 generates a synchronous signal T1 shown in FIG. 4(a), and the control circuit 3 operates in synchronization with this synchronous signal T1. It is output from output terminal 4. Synchronization signal TI
is the input terminal 8. of the semiconductor device 7. The synchronizing signal T2 shown in FIG. 4(b) is generated via the buffer 9, and the control circuit 10 is operated. The control circuit 3 of the semiconductor synchronous control device 1 outputs the control signal a to the output terminal 6 at the rising edge of the synchronous signal TI, and the control circuit 10 of the semiconductor device 7 takes in this control signal a at the rising edge of the synchronous signal T2. As shown in Figure 4 (C1), the phase of the synchronizing signal T2 is delayed by the time d compared to the synchronizing signal TI, so the holding time of the control signal a with respect to the synchronizing signal T2 is shorter by the time d than the holding time with respect to the synchronizing signal T1. Become.
従来の半導体同期制御装置は以上のように構成されてい
たので、内部の同期信号Ｔ１と他の半導体装置７の同期
信号Ｔ２との間の位相差により、制御信号ａの保持時間
が短くなり動作余裕が少なくなるという問題点があった
。Since the conventional semiconductor synchronous control device is configured as described above, the holding time of the control signal a is shortened due to the phase difference between the internal synchronizing signal T1 and the synchronizing signal T2 of the other semiconductor device 7, resulting in operation. There was a problem that there was less margin.
本発明はこのような点に鑑みてなされたものであり、そ
の目的とするところは、半導体同期制御装置１の内部同
期信号Ｔ１と他の半導体装置７の同期信号Ｔ２との間に
位相差を生じない半導体同期制御装置を得ることにある
。The present invention has been made in view of these points, and its purpose is to create a phase difference between the internal synchronization signal T1 of the semiconductor synchronous control device 1 and the synchronization signal T2 of the other semiconductor device 7. The object of the present invention is to obtain a semiconductor synchronous control device that does not cause synchronous control.
このような目的を達成するために本発明は、同期信号を
発生する同期信号発生回路と、この同期信号を外部へ出
力する出力手段と、外部へ出力した同期信号を再入力す
る入力手段と、再入力した同期信号に同期した制御信号
を出力する制御回路とを設けるようにしたものである。In order to achieve such an object, the present invention provides a synchronization signal generation circuit that generates a synchronization signal, an output means for outputting this synchronization signal to the outside, an input means for re-inputting the synchronization signal outputted to the outside, A control circuit that outputs a control signal synchronized with the re-input synchronization signal is provided.
本発明においては、半導体同期制御装置の入力端子に再
入力された同期信号と他の半導体装置内部の同期信号と
は同じ位相になる。In the present invention, the synchronization signal re-input to the input terminal of the semiconductor synchronous control device and the synchronization signals inside other semiconductor devices have the same phase.
本発明に係わる半導体同期制御装置の一実施例を第１図
に示す。第１図において、１２は同期信号を再入力する
ための入力手段としての入力端子、１３はバッファ９と
同等の位相差を有するバッファである。第１図において
第３図と同一部分又は相当部分には同一符号が付しであ
る。An embodiment of a semiconductor synchronous control device according to the present invention is shown in FIG. In FIG. 1, 12 is an input terminal as an input means for re-inputting a synchronization signal, and 13 is a buffer having the same phase difference as buffer 9. In FIG. In FIG. 1, the same or equivalent parts as in FIG. 3 are given the same reference numerals.
第２図（ａ）、 （ｂＬ ｔｃ＋および（ｄ）は同期信
号ＴＩ、Ｔ２、Ｔ３および制御信号ａを示す波形図であ
る。FIGS. 2(a), (bL tc+ and d) are waveform diagrams showing synchronization signals TI, T2, T3 and control signal a.
次に動作について第１図、第２図を用いて説明する。半
導体同期制御袋Ｗ１において同期信号発生回路２により
同期信号Ｔｌが発生する。この同期信号Ｔｌは出力端子
４から出力され、半導体装置７に入力されると共に、入
力端子１２から半導体同期制御装置ｌへも再入力され、
第２図（Ｃ）に示すように、制御回路３の同期信号Ｔ３
となる。−カキ導体装置７へ入力された同期信号ＴＩは
入力端子８．バッファ９を経由して制御回路１０を動作
させる同期信号Ｔ２となる。制御回路３は同期信号Ｔ３
の立下がりで制御信号ａを出力端子６へ出力し、制御回
路８はこの制御信号ａを同期信号Ｔ２の立上がりで取込
むが、同期信号Ｔ２．Ｔ３はいずれも同期信号ＴＩから
２段のバッファを介して生成されており、その位相は等
しいので、制御信号ａの同期信号Ｔ２に対する保持時間
は同期信号Ｔ３に対する保持時間りと等しい。Next, the operation will be explained using FIGS. 1 and 2. A synchronization signal Tl is generated by a synchronization signal generation circuit 2 in the semiconductor synchronization control bag W1. This synchronization signal Tl is outputted from the output terminal 4 and inputted to the semiconductor device 7, and is also inputted again to the semiconductor synchronous control device l from the input terminal 12,
As shown in FIG. 2(C), the synchronization signal T3 of the control circuit 3
becomes. - The synchronization signal TI input to the oyster conductor device 7 is input to the input terminal 8. It becomes a synchronizing signal T2 that operates the control circuit 10 via the buffer 9. Control circuit 3 uses synchronization signal T3
The control signal a is output to the output terminal 6 at the falling edge of the synchronizing signal T2, and the control circuit 8 receives this control signal a at the rising edge of the synchronizing signal T2. Both signals T3 are generated from the synchronizing signal TI through two stages of buffers and have the same phase, so the holding time of the control signal a with respect to the synchronizing signal T2 is equal to the holding time with respect to the synchronizing signal T3.
なお本実施例では同期信号が１つの場合について説明し
たが、２つ以上ある場合についてはその数だけ同期信号
の出力端子および入力端子が増えるだけで本実施例と同
様の効果を奏する。Although this embodiment has been described with reference to the case where there is one synchronization signal, in the case where there are two or more synchronization signals, the same effect as in this embodiment can be achieved by simply increasing the number of output terminals and input terminals for the synchronization signal.
以上説明したように本発明は、同期信号を発生する同期
信号発生回路と、この同期信号を外部へ出力する出力手
段と、外部へ出力した同期信号を再入力する入力手段と
、再入力した同期信号に同期した制御信号を出力する制
御回路とを設けることにより、外部に接続された他の半
導体装置の内部同期信号と位相の等しい内部同期信号を
発生できるので、位相に関する動作余裕が大きくなる効
果がある。As explained above, the present invention includes a synchronization signal generation circuit that generates a synchronization signal, an output means that outputs this synchronization signal to the outside, an input means that re-inputs the synchronization signal that has been output to the outside, and a synchronization signal that is re-input. By providing a control circuit that outputs a control signal synchronized with the signal, it is possible to generate an internal synchronization signal that has the same phase as the internal synchronization signal of other externally connected semiconductor devices, which increases the operational margin regarding the phase. There is.
第１図は本発明に係わる半導体同期制御装置の一実施例
を示す系統図、第２図はその動作を説明するための波形
図、第３図は従来の半導体同期制御装置を示す系統図、
第４図はその動作を説明するための波形図である。
１・・・・半導体同期制御装置、２・・・・同期信号発
生回路、３．１０・・・・制御回路、４．６・・・・出
力端子、５，９．１３・・・・バッファ、７・・・・半
導体装置、８，１１．１２・・・・入力端子。FIG. 1 is a system diagram showing an embodiment of a semiconductor synchronous control device according to the present invention, FIG. 2 is a waveform diagram for explaining its operation, and FIG. 3 is a system diagram showing a conventional semiconductor synchronous control device.
FIG. 4 is a waveform diagram for explaining the operation. 1... Semiconductor synchronous control device, 2... Synchronous signal generation circuit, 3.10... Control circuit, 4.6... Output terminal, 5, 9.13... Buffer , 7... semiconductor device, 8, 11.12... input terminal.
Claims (1)
回路と、前記同期信号を外部へ出力する前記同期信号数
分の出力手段と、前記外部へ出力した同期信号を再入力
する前記同期信号数分の入力手段と、前記再入力した同
期信号に同期した制御信号を出力する制御回路とを備え
たことを特徴とする半導体同期制御装置。a synchronization signal generation circuit that generates at least one synchronization signal; output means for the number of synchronization signals that outputs the synchronization signal to the outside; and output means for the number of synchronization signals that re-inputs the synchronization signal output to the outside. A semiconductor synchronous control device comprising: input means; and a control circuit that outputs a control signal synchronized with the re-input synchronization signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60130176A JPS61288218A (en) | 1985-06-14 | 1985-06-14 | Semiconductor synchronous controller |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60130176A JPS61288218A (en) | 1985-06-14 | 1985-06-14 | Semiconductor synchronous controller |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61288218A true JPS61288218A (en) | 1986-12-18 |
Family
ID=15027861
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60130176A Pending JPS61288218A (en) | 1985-06-14 | 1985-06-14 | Semiconductor synchronous controller |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61288218A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0895660A (en) * | 1994-09-26 | 1996-04-12 | Nec Corp | Lsi with built-in clock generator/controller operating with low power consumption |
-
1985
- 1985-06-14 JP JP60130176A patent/JPS61288218A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0895660A (en) * | 1994-09-26 | 1996-04-12 | Nec Corp | Lsi with built-in clock generator/controller operating with low power consumption |
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