JPS61284953A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS61284953A JPS61284953A JP60127672A JP12767285A JPS61284953A JP S61284953 A JPS61284953 A JP S61284953A JP 60127672 A JP60127672 A JP 60127672A JP 12767285 A JP12767285 A JP 12767285A JP S61284953 A JPS61284953 A JP S61284953A
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- circuit
- terminal
- circuits
- ground
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は、ＣＭＯＳロジック回路において、出力回路
のスイッチング時の電源ラインおよび接地ラインに発生
ずるノイズを削減した半導体集積回路装置に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device in which noise generated in a power supply line and a ground line during switching of an output circuit in a CMOS logic circuit is reduced.
第２図は従来のＣＭＯＳロジックＩＣのチップ上のパタ
ーンレイアウト図の概略を示す。この図において、１は
電源供給端子、２は接地端子、３〜５はゲート回路等の
論理回路を示す。なお、この図では３〜５の入力信号供
給端子、出力信号取出し用端子は省略している。６は前
記電源供給端子１から各回路に電源を供給する内部配線
、７は前記接地端子２と各回路を接続する内部配線を示
す。FIG. 2 schematically shows a pattern layout diagram on a chip of a conventional CMOS logic IC. In this figure, 1 is a power supply terminal, 2 is a ground terminal, and 3 to 5 are logic circuits such as gate circuits. In this figure, input signal supply terminals 3 to 5 and output signal extraction terminals are omitted. Reference numeral 6 indicates internal wiring that supplies power from the power supply terminal 1 to each circuit, and 7 indicates an internal wiring that connects the ground terminal 2 and each circuit.
第３図は、第２図の等価回路図を示す。３ａ〜５ａは各
論理回路３〜５の出力回路のみを表１ノている。８ａ〜
８ｃ、９ａ〜９ｃ、１０，１１は前記内部配線６，７に
寄生するインダクタンス、１２ば出力端子に寄生するキ
ャパシタンスを示している。 次に第３図の動作につい
て説明する。各出力回路３ａ〜５ａはそれぞれ独立に動
作し、入力端子に加えられた信号に対し出力端子に内部
で処理された出力信号を出す。FIG. 3 shows an equivalent circuit diagram of FIG. 2. 3a to 5a show only the output circuits of each logic circuit 3 to 5 in Table 1. 8a~
Reference numerals 8c, 9a to 9c, 10, and 11 indicate inductance parasitic to the internal wirings 6 and 7, and reference numeral 12 indicates capacitance parasitic to the output terminal. Next, the operation shown in FIG. 3 will be explained. Each of the output circuits 3a to 5a operates independently, and outputs an internally processed output signal to an output terminal in response to a signal applied to an input terminal.
第３図において、出力回路３ａ〜５ａが“１１”レベル
かう゛Ｌ″レベルまたはＩＩ Ｌ １１レベルから“’
Ｈ”レベルにスイッチングした場合、キャパシタンス
１２の充放電が行われ、インダクタンス８ａ〜８ｃ、９
ａ〜９ｃ、１０，１１と共振が起こリノイズとなる１、
このノイズは出力端子に現われ正常な論理信号に影響を
及ぼずとともに、電源供給端子１および接地端子２にも
影響を与える。In FIG. 3, the output circuits 3a to 5a change from "11" level to "L" level or II L11 level to "'".
When switching to H" level, the capacitance 12 is charged and discharged, and the inductances 8a to 8c, 9
1, which causes resonance with a to 9c, 10, and 11 and causes renoise;
This noise appears at the output terminal and does not affect normal logic signals, but also affects the power supply terminal 1 and the ground terminal 2.
第４図はノイズ発生時の等両回路で、１３ばＭＯＳトラ
ンジスタの導通時抵抗および内部配線の抵抗分を示し、
１４は前記インダクタンス８ａ〜８ｃｐ９ｎ〜９ｃ、１
０，１１をまとめて表（ツなインダクタンス、１５はト
ランジスタが導通、非導通時のスイッチング動作を示す
スイッチである。Figure 4 shows the resistance of the MOS transistor 13 when it is conductive and the resistance of the internal wiring in both circuits when noise occurs.
14 is the inductance 8a to 8cp9n to 9c, 1
0 and 11 are summarized in the table (two inductances), and 15 is a switch that shows the switching operation when the transistor is conductive or non-conductive.
これらの素子はＲＬ Ｃの直列共振回路を形成している
。These elements form an RLC series resonant circuit.
上記で説明したように電源、接地配線を共有ずろ同一チ
ップ上の複数回路においてスイッチング゛を行っている
回路がノイズを発生して接地電位。As explained above, multiple circuits on the same chip that share the power supply and ground wires and perform switching generate noise and lower the ground potential.
電源電位にノイズを重畳させ同一チップ上の他の回路に
まで影響を及ぼす問題点があった。There was a problem in that noise was superimposed on the power supply potential, affecting other circuits on the same chip.
この発明は、上記の問題点を解消するためになされたも
ので、゛内部回路のスイッチング時に発生するノイズを
他の回路に影響を及ぼさないようにすることを目的とし
ている。The present invention has been made to solve the above-mentioned problems, and its purpose is to prevent noise generated during switching of internal circuits from affecting other circuits.
この発明は、電源供給端子および接地端子と各論理回路
を接続するための内部配線を途中から枝分れさせず各論
理回路毎に個別に電源供給端子。This invention provides power supply terminals for each logic circuit individually without branching out the internal wiring for connecting the power supply terminal and the ground terminal to each logic circuit.
接地端子まで専用の内部配線でそれぞれ接続１７たもの
である。Each terminal is connected to the ground terminal using dedicated internal wiring.
この発明においては、各論理回路はそれぞれの個別の内
部配線によって電源供給端子から電源の供給を受け、ま
た個別の内部配線によって接地端子に接続されろ。In this invention, each logic circuit receives power from a power supply terminal through its own internal wiring, and is connected to a ground terminal through its own internal wiring.
第１図はこの発明の一実施例を示すものである。 FIG. 1 shows an embodiment of the present invention.
この図において、第２図と同一符号は同一構成部分を示
し、６ａ、６ｂ、６ｃは個別の電源供給内部配線、７ｎ
、７ｂ、、７ｃは同じく個別の接地接続内部配線である
。図に示すように各論理回路３〜５の電源、接地配線は
各々の供給端子から枝分れすることなしに各々専用の電
源供給および接地接続内部配線６０〜６ｃ、７ｕ〜７Ｃ
で接続したものである。In this figure, the same symbols as in FIG. 2 indicate the same components, 6a, 6b, 6c are individual power supply internal wirings, 7n
, 7b, , 7c are also individual ground connection internal wirings. As shown in the figure, the power supply and ground wiring for each logic circuit 3 to 5 is connected to a dedicated power supply and ground connection internal wiring 60 to 6c, 7u to 7C without branching out from each supply terminal.
It is connected with
上記構成の半導体集積回路装置において、第３図の等両
回路に示すように出力回路５ａが“Ｈ’レベルまたは′
″Ｌ Ｉ＋レベルのいずれかの状態にある時、出力回路
３ａまたは出力回路４ａがスイッチングしても出力回路
５ａはインダクタンス８ａおよびインダクタンス８ｂを
経由せずに電源供給端子１まで接続されているので、出
力回路３ａまたは出力回路４ａの影響を受けない。また
出力回路３ａが’ Ｈ”レベルまたは゛′Ｌ′ルベルの
いずれかの状態にある時出力回路４ａまたは出力回路５
ａがスイッチングしても出力回路３ａの回路はインダク
タンス９ｂおよびインダクタンス９Ｃを経゛山せずに接
地端子２まで接続されているので、出力回路４ａまたは
出力回路３ｕの影響を受けない０
なお、上記実施例ではＣＭＯ３論理回路の例で示したが
、こればバイポーラ論理回路、特に出力のＥｌ）ｆＥ駆
動能力の大きいＴＴＬ （トランジスタ。In the semiconductor integrated circuit device having the above configuration, the output circuit 5a is at "H" level or
When in any state of ``L I+ level, even if the output circuit 3a or the output circuit 4a switches, the output circuit 5a is connected to the power supply terminal 1 without passing through the inductance 8a and the inductance 8b. It is not affected by the output circuit 3a or the output circuit 4a.Also, when the output circuit 3a is at either the 'H' level or the 'L' level, the output circuit 4a or the output circuit 5
Even if a switches, the circuit of the output circuit 3a is connected to the ground terminal 2 without passing through the inductance 9b and the inductance 9C, so it is not affected by the output circuit 4a or the output circuit 3u. In the example, a CMO3 logic circuit was shown as an example, but this is also a bipolar logic circuit, especially a TTL (transistor) with a large output El)fE drive capability.
トランジスタロジック）への応用にも同様の効果が得ら
れる。A similar effect can be obtained when applied to (transistor logic).
また上記実施例では電流供給端子１．接地端子２ともに
専用の内部配線を設けているが、′″Ｌ″′側ノイズが
問題となる時は接地接続内部配線７ａ〜７Ｃのみ、“Ｉ
Ｔ ”側ノイズが問題となる時は電源供給内部配線６ａ
〜６Ｃのみを専用化すればよい。Further, in the above embodiment, the current supply terminal 1. Dedicated internal wiring is provided for both ground terminals 2, but when noise on the ``L'' side becomes a problem, only the ground connection internal wiring 7a to 7C is connected to ``I''.
If noise on the T” side is a problem, connect the power supply internal wiring 6a.
~6C only needs to be dedicated.
この発明は以上説明したとおり電源供給内部配線、接地
接続内部配線を各回路毎に個別に設けたので、同一チッ
プ内の他の回路がスイッチングする時に出すノイズの影
響を別の回路が受けず正常な論理信号を安定に出力する
効果が得られろ。As explained above, in this invention, the power supply internal wiring and the grounding connection internal wiring are individually provided for each circuit, so that the other circuits in the same chip are not affected by the noise generated when switching, and the other circuits operate normally. The effect of stably outputting logic signals can be obtained.
第１図はこの発明の一実施例を示すパターンレイアウト
図の概略図、第２図は従来のパターン１／イアウドを示
ず図、第３図は第２図の等価回路図、第４図は第３図で
形成されるＬＣＲ直列共振回路図である。
図において、１は電源供給端子、２は接地端子、３〜５
は論理回路、６ａ〜６Ｃは個別の電源供給内部配線、７
０〜７Ｃは個別の接地接続内部配線である。
なお、各図中の同一符号は同一または相当部分を示す。
代理人 大 岩 増 雄 （外２名）
第１図
第２図FIG. 1 is a schematic diagram of a pattern layout diagram showing an embodiment of the present invention, FIG. 2 is a diagram without the conventional pattern 1/iaud, FIG. 3 is an equivalent circuit diagram of FIG. 2, and FIG. FIG. 4 is a diagram of the LCR series resonant circuit formed in FIG. 3; In the figure, 1 is a power supply terminal, 2 is a ground terminal, 3 to 5
is a logic circuit, 6a to 6C are individual power supply internal wirings, 7
0-7C are individual ground connection internal wires. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) Figure 1 Figure 2
Claims (1)
電源が供給される集積回路において、前記出力回路から
それぞれの電源供給内部配線により個別に前記電源供給
端子へ接続するか、または前記出力回路からそれぞれの
接地接続内部配線により個別に接地端子まで接続するか
したことを特徴とする半導体集積回路装置。In an integrated circuit that has a plurality of output circuits in the same chip and is supplied with power from a power supply terminal, each of the output circuits is individually connected to the power supply terminal by each power supply internal wiring, or the output circuit is What is claimed is: 1. A semiconductor integrated circuit device characterized in that each ground connection is individually connected to a ground terminal by internal wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60127672A JPS61284953A (en) | 1985-06-11 | 1985-06-11 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60127672A JPS61284953A (en) | 1985-06-11 | 1985-06-11 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61284953A true JPS61284953A (en) | 1986-12-15 |
Family
ID=14965860
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60127672A Pending JPS61284953A (en) | 1985-06-11 | 1985-06-11 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61284953A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01296822A (en) * | 1988-05-25 | 1989-11-30 | Toshiba Corp | Analog-digital converter |
| US5844262A (en) * | 1995-05-25 | 1998-12-01 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device for reducing effects of noise on an internal circuit |
| US5883427A (en) * | 1996-09-10 | 1999-03-16 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device power supply wiring structure |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5593235A (en) * | 1979-01-05 | 1980-07-15 | Nec Corp | Integrated circuit |
-
1985
- 1985-06-11 JP JP60127672A patent/JPS61284953A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5593235A (en) * | 1979-01-05 | 1980-07-15 | Nec Corp | Integrated circuit |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01296822A (en) * | 1988-05-25 | 1989-11-30 | Toshiba Corp | Analog-digital converter |
| US5844262A (en) * | 1995-05-25 | 1998-12-01 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device for reducing effects of noise on an internal circuit |
| US6331719B2 (en) * | 1995-05-25 | 2001-12-18 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device for reducing effects of noise on an internal circuit |
| US5883427A (en) * | 1996-09-10 | 1999-03-16 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device power supply wiring structure |
| US6181005B1 (en) | 1996-09-10 | 2001-01-30 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device wiring structure |
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