JPS61269530A - Complementary type mos inverter circuit - Google Patents

Complementary type mos inverter circuit

Info

Publication number
JPS61269530A
JPS61269530A JP60111616A JP11161685A JPS61269530A JP S61269530 A JPS61269530 A JP S61269530A JP 60111616 A JP60111616 A JP 60111616A JP 11161685 A JP11161685 A JP 11161685A JP S61269530 A JPS61269530 A JP S61269530A
Authority
JP
Japan
Prior art keywords
inverter circuit
complementary
mos transistor
output
temperature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60111616A
Other languages
Japanese (ja)
Inventor
Koji Sanada
真田 孝司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP60111616A priority Critical patent/JPS61269530A/en
Publication of JPS61269530A publication Critical patent/JPS61269530A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003Modifications for increasing the reliability for protection
    • H03K19/00369Modifications for compensating variations of temperature, supply voltage or other physical parameters
    • H03K19/00384Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To obtain a stable operation margin by connecting a resistive element comprising poly crystal silicon having a negative temperature coefficient in series with a source or a drain of a MOS transistor (TR) so as to decrease the temperature dependance of the output response. CONSTITUTION:A p-channel MOSTRQP and an n-channel MOSTRQN constitute a complementary MOS inverter circuit having input 1 and output 2. Resistive elements R1, R2 made of a poly crystal silicon having a negative temperature coefficient are connected in series with the source or drain of the TRs QP, QN. Then the temperature dependency of the output response of the inverter circuit is decreased to obtain a stable operation margin.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は相補型MOSインバータ回路に関するものであ
る。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a complementary MOS inverter circuit.

〔従来の技術〕[Conventional technology]

従来の相補型MOSインバータ回路について第3図を用
いて簡単な構成及び動作を説明する。
A simple configuration and operation of a conventional complementary MOS inverter circuit will be explained with reference to FIG.

第3図の相補型MUSインバータ回路は、Pチャンネル
型MOSトランジスタQPとNチャンネル型MOSトラ
ンジスタQNで構成されている基本的な相補型MOSイ
ンバータ回路である。
The complementary MUS inverter circuit shown in FIG. 3 is a basic complementary MOS inverter circuit composed of a P-channel MOS transistor QP and an N-channel MOS transistor QN.

ここで、入力1にHighレベル(例えばV。。)が印
加されれば、上記QNがオン曝がオフし、出力2にはG
ND(中o V )レベルが出力される。
Here, if a high level (for example, V.
An ND (medium o V ) level is output.

また、入力1にり。Wレベル(例えばGND=Ov)が
印加されれば、上記QPがオン、QNがオフし、出力2
には■。。レベルが出力さ、れるような過渡応答をする
Also, input 1. When W level (for example, GND=Ov) is applied, the above QP turns on, QN turns off, and output 2
■. . Transient response such that the level is output.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の相補型MOSインバータ回路では、MO
Sトランジスタで構成されているため出力応答の温度依
存性が大きく、特に高温となった場合MOSトランジス
タの能力が低下し、出力の応答が遅れるという欠点があ
った。
In the conventional complementary MOS inverter circuit described above, the MO
Since it is composed of S transistors, the output response has a large temperature dependence, and especially when the temperature reaches a high temperature, the performance of the MOS transistor decreases, resulting in a delay in the output response.

本発明の目的は、上記従来の相補型MOSインバータ回
路の欠点を改良し、出力応答の温度依存性が少ない相補
型MO8インバータ回路を提供するととKある。
An object of the present invention is to improve the drawbacks of the conventional complementary MOS inverter circuit and provide a complementary MO8 inverter circuit whose output response is less dependent on temperature.

〔問題点を解決するための手段〕[Means for solving problems]

本発明はPチャンネル型MOSトランジスタ及びNチャ
ンネル型MOSトランジスタから構成される相補型MO
Sインバータ回路において、前記MOSトランジスタの
ドレイン電極側もしくはソース電極側に負の温度係数を
もつ多結晶シリコンからなる抵抗素子を直列接続したこ
とを特徴とする相補型MOSインバータ回路である。
The present invention is a complementary MOS transistor composed of a P-channel type MOS transistor and an N-channel type MOS transistor.
The present invention is a complementary MOS inverter circuit characterized in that a resistance element made of polycrystalline silicon having a negative temperature coefficient is connected in series to the drain electrode side or source electrode side of the MOS transistor.

〔実施例〕〔Example〕

次に本発明の実施例について、第1図を用いて説明する
Next, an embodiment of the present invention will be described using FIG.

第1図は1を入力、2を出力とする相補型MO8インバ
ータ回路であり%QPはPチャンネル型M)Sトランジ
スタ、QN1d′Nチャンネル型MOBトランジスタR
1、R,は負の温度係数をもつ抵抗素子であり、それぞ
れQP QNのドレイン電極に接続され、且つ%”1 
とR2の接点に出力2が接続されている。上記負の温度
係数をもつ抵抗素子は、例えば多結晶ポリシリコンで作
ることにより容易に実現できる。
Figure 1 shows a complementary MO8 inverter circuit with input 1 and output 2, where %QP is a P-channel type M)S transistor, and QN1d' is an N-channel MOB transistor R.
1, R, are resistance elements with negative temperature coefficients, each connected to the drain electrode of QP QN, and %”1
Output 2 is connected to the contacts of R2 and R2. The above-mentioned resistance element having a negative temperature coefficient can be easily realized by making it, for example, from polycrystalline polysilicon.

ここで、通常Pチャンネル型MOSトランジスタ及びN
チャンネル型MO8>−ランジスタのオン抵抗RP、R
Nは正の温度係数をもち、温度が高くなればなる程、オ
ン抵抗は高くなる。−力負の温度係数をもつ抵抗素子”
1.R1は温度が高くなればなる程、抵抗は小さくなる
。し友がって、あらかじめ、 BP(25℃)+R1(25℃)=RP(高温)”R1
(高温) または、 RN(25℃)十R*(25℃)=RN(高温)+R2
(高温) となる様VcMOSトランジスタのサイズ及び負の温度
係数をもつ抵抗素子の抵抗値を決定してやれば、常温(
25℃)のときも高温のときも同じ駆動能力をもつこと
になり、温度依存性の小さい相補型MO8インバータ回
路を実現することができる0 また低温の場合においても、常温に比べてMOSトラン
ジスタのオン抵抗RNRPが小さくなるが、負の温度係
数をもつ抵抗素子R,,R,の抵抗が大きくなるので常
温の場合と出力の応答時間はほぼ同じにできる。
Here, normally a P channel type MOS transistor and an N
Channel type MO8>-on resistance RP, R of transistor
N has a positive temperature coefficient, and the higher the temperature, the higher the on-resistance. −Resistance element with negative temperature coefficient
1. The higher the temperature of R1, the lower the resistance. As a friend, in advance, BP (25℃) + R1 (25℃) = RP (high temperature) "R1
(High temperature) Or, RN (25℃) + R* (25℃) = RN (High temperature) + R2
(High temperature) If we determine the size of the VcMOS transistor and the resistance value of the resistance element with a negative temperature coefficient,
25℃) and high temperature, making it possible to realize a complementary MO8 inverter circuit with small temperature dependence.Also, even at low temperatures, the MOS transistor Although the on-resistance RNRP becomes smaller, the resistance of the resistance elements R, , R, having negative temperature coefficients becomes larger, so the output response time can be made almost the same as that at room temperature.

したがって、この様な相補型MOSインバータ回路構成
にしてやれば、温度依存性の小さい相補型MOSインバ
ータ回路が実現できる。
Therefore, if such a complementary MOS inverter circuit is configured, a complementary MOS inverter circuit with low temperature dependence can be realized.

第2図に本発明の第2の実施例を示すが、これも第1図
と同様な基本動作をするので詳細な説明は省略する。
A second embodiment of the present invention is shown in FIG. 2, but since this basic operation is similar to that in FIG. 1, detailed explanation will be omitted.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明の相補型MUSインバータ回
路は、出力応答の温度依存性が小さいため、種々の回路
に適用すれば、安定した動作マージンを得ることができ
る。
As explained above, since the complementary MUS inverter circuit of the present invention has a small temperature dependence of the output response, it is possible to obtain a stable operating margin when applied to various circuits.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図、第2図は本発明の実施例の相補型インバータ回
路を示す図である。 第3図は従来の相補型インバータ回路を示す図である。 l・・・・・・入力、2・・・・・・出力%QN・・・
出Nチャンネル型MOSトランジスタ、QP曲・・Pチ
ャンネル型MOBトランジスタ、R1、R,・・・・・
・負oiw係数をもつ多結晶シリコンからなる抵抗素子
、RN・・・・・・QNのオン抵抗、RP・・・・・・
QPのオン抵抗。 尋 1 図 を 2 菌 業 3@ C1
1 and 2 are diagrams showing complementary inverter circuits according to embodiments of the present invention. FIG. 3 is a diagram showing a conventional complementary inverter circuit. l...Input, 2...Output%QN...
Output N-channel type MOS transistor, QP song...P-channel type MOB transistor, R1, R,...
・Resistance element made of polycrystalline silicon with negative OIW coefficient, RN...On resistance of QN, RP...
QP on-resistance. Hiro 1 Diagram 2 Fungi industry 3 @ C1

Claims (1)

【特許請求の範囲】[Claims] Pチャンネル型MOSトランジスタ及びNチャンネル型
MOSトランジスタから構成される相補型MOSインバ
ータ回路において、負の温度係数をもつ多結晶シリコン
からなる抵抗素子を前記MOSトランジスタのソース側
電極もしくはドレイン側電極に直列接続したことを特徴
とする相補型インバータ回路。
In a complementary MOS inverter circuit composed of a P-channel MOS transistor and an N-channel MOS transistor, a resistance element made of polycrystalline silicon having a negative temperature coefficient is connected in series to the source side electrode or drain side electrode of the MOS transistor. A complementary inverter circuit characterized by:
JP60111616A 1985-05-24 1985-05-24 Complementary type mos inverter circuit Pending JPS61269530A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60111616A JPS61269530A (en) 1985-05-24 1985-05-24 Complementary type mos inverter circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60111616A JPS61269530A (en) 1985-05-24 1985-05-24 Complementary type mos inverter circuit

Publications (1)

Publication Number Publication Date
JPS61269530A true JPS61269530A (en) 1986-11-28

Family

ID=14565842

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60111616A Pending JPS61269530A (en) 1985-05-24 1985-05-24 Complementary type mos inverter circuit

Country Status (1)

Country Link
JP (1) JPS61269530A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62208657A (en) * 1986-02-04 1987-09-12 バ−・ブラウン・コ−ポレ−シヨン Cmos input level shifting circuit with temperature compensation n-type channel field effect transistor structure
EP0893885A2 (en) * 1997-06-17 1999-01-27 NEC Corporation Small amplitude signal output circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62208657A (en) * 1986-02-04 1987-09-12 バ−・ブラウン・コ−ポレ−シヨン Cmos input level shifting circuit with temperature compensation n-type channel field effect transistor structure
EP0893885A2 (en) * 1997-06-17 1999-01-27 NEC Corporation Small amplitude signal output circuit
EP0893885A3 (en) * 1997-06-17 1999-03-31 NEC Corporation Small amplitude signal output circuit

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