JPS61263308A - Mis circuit device - Google Patents

Mis circuit device

Info

Publication number
JPS61263308A
JPS61263308A JP60105515A JP10551585A JPS61263308A JP S61263308 A JPS61263308 A JP S61263308A JP 60105515 A JP60105515 A JP 60105515A JP 10551585 A JP10551585 A JP 10551585A JP S61263308 A JPS61263308 A JP S61263308A
Authority
JP
Japan
Prior art keywords
circuit
output
stage
bistable circuit
drain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60105515A
Other languages
Japanese (ja)
Other versions
JPH0368567B2 (en
Inventor
Fumito Kawamura
川村　文人
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP60105515A priority Critical patent/JPS61263308A/en
Priority to US06/864,652 priority patent/US4771187A/en
Priority to DE86106808T priority patent/DE3689291D1/en
Priority to EP86106808A priority patent/EP0203491B1/en
Publication of JPS61263308A publication Critical patent/JPS61263308A/en
Publication of JPH0368567B2 publication Critical patent/JPH0368567B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H03K3/0375—Bistable circuits provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails

Landscapes

  • Logic Circuits (AREA)

Abstract

PURPOSE:To obtain a circuit not affecting malfunction to the post-stage circuits even when an output of an FF of the pre-stage reaches an intermediate level by an asynchronous input by using an activated signal of the post-stage so as to binary-code an output of the pre-stage bistable circuit (FF). CONSTITUTION:When an input changes at the trailing of an activated signal F1 of the FF 1 of the pre-stage and the activation is finished on the way of change, the output of the FF 1 of the pre-stage goes to an intermediate potential. The output is subject to level shift by MISFETs Q1, Q2 and the result is inputted to an inverter INV. The output of the inverter INV is inputted to one of MISFETs Q3, Q4 of NAND logic. Since an activation signal F2 for the circuit 2 of the next stage is inputted to the other, when the signal F2 is inputted, the level of an output OUT2 of the FF 1 of the pre-stage 1 is fixed to the level inverting the output of the inverter INV, then a clear logic level is fed to the circuit 2 of the next stage.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はＭＩＳトランジスタを用いて構成される双安定
回路を含むＭＩＳ回路装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an MIS circuit device including a bistable circuit configured using MIS transistors.

〔従来の技術〕[Conventional technology]

従来、双安定回路においては、二つの結合回路は直流結
合であって、安定状態は二つある。一方の安定状態を定
める入力が与えられると、次に他方の安定状態を定める
入力が与えられるまでその状態を保持する。二つの安定
状態をそれぞれ２進情報０，１に対応させることができ
る。この故Ｋ。Conventionally, in a bistable circuit, two coupled circuits are DC coupled, and there are two stable states. When an input that defines one stable state is given, that state is maintained until the next input that defines the other stable state is given. Two stable states can be associated with binary information 0 and 1, respectively. This late K.

ティジタル量を扱う回路に双安定回路が多く用いられる
ようになってきた。Bistable circuits are increasingly being used in circuits that handle digital quantities.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

双安定回路を含むＭＩＳ回路装置において、双安定回路
の入力がこの双安定回路を活性化する場合、この入力が
入いるタイミングによってこの双安定回路の出力が、中
間電位点に留シ、この双安定回路の次段の回路に誤動作
を引起すという欠点がある。In a MIS circuit device that includes a bistable circuit, when the input of the bistable circuit activates this bistable circuit, the output of this bistable circuit stays at the intermediate potential point depending on the timing of this input, and the output of this bistable circuit remains at the intermediate potential point. This has the disadvantage that it causes malfunction in the circuit next to the stabilizing circuit.

本発明の目的は、双安定回路の人力か、とのＭＩｓ双安
定回路を活性化する信号に対して、非同期に入力される
場合においても、このＭＩＳ双安定回路の次段に誤動作
を引起させないＭ’Ｉ８回路装置を提供することにある
。The object of the present invention is to prevent malfunctions in the next stage of the MIS bistable circuit even when input asynchronously to a signal that activates the MIS bistable circuit. An object of the present invention is to provide an M'I8 circuit device.

〔問題点を解決するための手段〕[Means for solving problems]

本発明のＭＩＳ回路回路装置及１双安定ンバータと、該
インバータの入力端と第１の電位供給端との間にソース
とドレインが接続され前記双安定回路の第１の出力端に
ゲートが接続する第１のＭＩＳトランジスタと、前記イ
ンバータの入力端と第２の電位供給端との間にソースと
ドレインとが接続され前記双安定回路の第２の出力端に
ゲートが接続する第２０Ｍ工Ｓトランジスタと、前記双
安定回路の第２の出力端にドレイン（またはソース）が
接続され前記インバータの出力端にゲートが接続される
第３のＭＩＳトランジスタと、該第３のＭＩＳトランジ
スタのソース（またはドレイン）と前記第１の電位供給
端との間にドレインとソースとが接続されゲートが次段
の回路の活性化信号入力端に接続する第４のＭＩＳトラ
ンジスタを含んで構成される。A MIS circuit circuit device and a bistable inverter of the present invention, a source and a drain are connected between an input terminal and a first potential supply terminal of the inverter, and a gate is connected to a first output terminal of the bistable circuit. a first MIS transistor, a source and a drain connected between the input terminal of the inverter and a second potential supply terminal, and a gate connected to the second output terminal of the bistable circuit; a third MIS transistor whose drain (or source) is connected to the second output terminal of the bistable circuit and whose gate is connected to the output terminal of the inverter; and the source (or The fourth MIS transistor includes a fourth MIS transistor whose drain and source are connected between the drain (drain) and the first potential supply end, and whose gate is connected to the activation signal input end of the next stage circuit.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.

第１図は本発明の一実施例の回路図である。FIG. 1 is a circuit diagram of an embodiment of the present invention.

この実施例は、双安定回路１と、インバータエＮＶと、
このインバータＩＮＶの入力端（節点Ｎ）と第１の電位
供給端Ｖｓｓとの間にソースとドレインが接続され双安
定回路１の第１の出方端ＯＵＴ。This embodiment includes a bistable circuit 1, an inverter NV,
A first output end OUT of the bistable circuit 1 has a source and a drain connected between the input end (node N) of the inverter INV and the first potential supply end Vss.

にゲートが接続する第１のＭ工ＳトランジスタＱｔと、
インバータＩＮＶの入力端と第２の電位供給端ＶＤＤと
の間にソースとドレインとが接続され双安定回路ｌの第
２の出力端ＯＵＴ，にゲートが接続する第２のＭＩＳト
ランジスタＱ！と、双安定回路１の第２の出力端ＯＵＴ
，にドレイン（またはソース）が接続されインバータＩ
ＮＶの出力端にゲートが接続される第３のＭＩＳトラン
ジスタＱ，と、この第３のＭＩＳトランジスタＱ３のソ
ース（またはドレイン）と第１の電位供給端Ｖｓｓとの
間にドレインとソースとが接続されゲートが次段の回路
２の活性化信号ｐ雪の入力端に接続する第４のＭ工Ｓト
ランジスタＱ４とを含んで構成される。a first M-S transistor Qt whose gate is connected to;
A second MIS transistor Q! has its source and drain connected between the input end of the inverter INV and the second potential supply end VDD, and has its gate connected to the second output end OUT of the bistable circuit l. and the second output terminal OUT of the bistable circuit 1
, the drain (or source) is connected to the inverter I
A third MIS transistor Q, whose gate is connected to the output terminal of NV, and whose drain and source are connected between the source (or drain) of this third MIS transistor Q3 and the first potential supply terminal Vss. and a fourth M/S transistor Q4 whose gate is connected to the input terminal of the activation signal p of the circuit 2 at the next stage.

尚、次段の回路２として，この実施例では双安定回路を
用いたか、これは双安定回路に限定されす、ラッチ回路
インバータ、フリップフロップ等り の回路であっても良い。In this embodiment, a bistable circuit is used as the next stage circuit 2, but this is not limited to a bistable circuit, but a circuit such as a latch circuit inverter or a flip-flop may be used.

次に、この実施例の動作について説明する。Next, the operation of this embodiment will be explained.

第２図は第１図に示す実施例の動作時における信号のタ
イミング図である。FIG. 2 is a timing diagram of signals during operation of the embodiment shown in FIG.

Ｆｌは双安定回路１の活性化信号，Ｆ２は次段の回路２
の活性化信号，Ａ，Ｂ，Ｃはデータ信号であって、信号
Ａは活性化信号Ｆ１とは非同期に入力される。信号Ｂと
Ｃとは互いに反転か、またはどちらも共に論理１０１の
信号である。この実施例では、互いに反転関係の信号と
した。Fl is the activation signal of bistable circuit 1, F2 is the next stage circuit 2
The activation signals A, B, and C are data signals, and the signal A is input asynchronously with the activation signal F1. Signals B and C are either inverses of each other or both are logic 101 signals. In this embodiment, the signals are inverted to each other.

第２図に示すように，活性化信号ＦＩ＋データ信号Ａ，
Ｂ，Ｃが入力されると、双安定回路１の出力端ＯＵＴ，
、ＯＵＴ．における出力信号は高レベルと低レベルの中
間の電位点となる。このように、双安定回路１の出力が
中間電位点に留る状態であっても、出力端２の中間電位
を節点Ｎに対して、Ｎチャネル型ＭＩＳト５ンジスタＱ
．がレベルシフトを行い、次段の回路２が活性状態とな
る時、次段の回路２を活性化させる信号Ｆ，と節点Ｎを
入力とするインバータＩＮＶの出力によシ、Ｎチャネル
型ＭＩＳトランジスタＱ３とＱ４がそれぞれ導通状態に
なシ、双安定回路１の第２の出力端ＯＵＴ，の電位をＶ
ｓｓに引き下げる。次段の回路２には出力端ＯＵＴ，と
節点Ｎが接続されておシ、次段の回路２Ｆｉｉ１４動作
を起さない。As shown in FIG. 2, activation signal FI+data signal A,
When B and C are input, the output terminal OUT of bistable circuit 1,
, OUT. The output signal at is at a potential point between the high level and the low level. In this way, even if the output of the bistable circuit 1 remains at the intermediate potential point, the intermediate potential of the output terminal 2 is connected to the node N by the N-channel MIST transistor Q.
．． performs a level shift and when the next stage circuit 2 becomes active, the N-channel MIS transistor Q3 and Q4 are each in a conductive state, and the potential of the second output terminal OUT of the bistable circuit 1 is set to V.
Lower it to ss. The output terminal OUT and the node N are connected to the next stage circuit 2, so that the next stage circuit 2Fii14 does not operate.

〔発明の効果〕〔Effect of the invention〕

以上説明したように１本発明によれば、双安定回路の人
力が、この双安定回路を活性化する信号に対して非同期
に入力される場合においても、この双安定回路の次段の
回路ＫＴｈ動作を引起さない双安定回路を含んだＭＩＳ
回路装置が得られる。As explained above, according to the present invention, even when the human power of a bistable circuit is input asynchronously to the signal that activates this bistable circuit, the circuit KTh of the next stage of this bistable circuit MIS containing bistable circuits that do not cause motion
A circuit device is obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

８１図は本発明の一実施例を示す回路図、第２図は第１
図に示す実施例の動作時における信号のタイミング図で
ある。 １・・・・・・双安定回路、２・・・・・・次段の回路
、Ａ、Ｂ。 Ｃ・・・・・・データ信号ｓＦ’１ｍＦ！・・・・・・
活性化信号、ＩＮＶ・・・・・・インバータ、Ｎ・・・
・・・節点、ＯＵＴ、、ＯＵＴ。 ・・・・・・双安定回路の出力端％Ｑ１〜Ｑ４・・・・
・・ＭＩＳトランジスタ。 東１図 Ｆ２：■−−寸一　軒図Figure 81 is a circuit diagram showing one embodiment of the present invention, and Figure 2 is a circuit diagram showing one embodiment of the present invention.
FIG. 3 is a timing diagram of signals during operation of the embodiment shown in the figure. 1...Bistable circuit, 2...Next stage circuit, A, B. C...Data signal sF'1mF!・・・・・・
Activation signal, INV...Inverter, N...
... Node, OUT,, OUT. ...Bistable circuit output terminal %Q1~Q4...
...MIS transistor. East 1 map F2: ■--Size one eave map

Claims (1)

【特許請求の範囲】[Claims] 双安定回路と、インバータと、該インバータの入力端と
第１の電位供給端との間にソースとドレインが接続され
前記双安定回路の第１の出力端にゲートが接続する第１
のＭＩＳトランジスタと、前記インバータの入力端と第
２の電位供給端との間にソースとドレインとが接続され
前記双安定回路の第２の出力端にゲートが接続する第２
のＭＩＳトランジスタと、前記双安定回路の第２の出力
端にドレイン（またはソース）が接続され前記インバー
タの出力端にゲートが接続される第３のＭＩＳトランジ
スタと、該第３のＭＩＳトランジスタのソース（または
ドレイン）と前記第１の電位供給端との間にドレインと
ソースとが接続されゲートが次段の回路の活性化信号入
力端に接続する第４のＭＩＳトランジスタを含むことを
特徴とするＭＩＳ回路装置。a bistable circuit, an inverter, and a first circuit whose source and drain are connected between the input terminal of the inverter and a first potential supply terminal, and whose gate is connected to the first output terminal of the bistable circuit.
a second MIS transistor having a source and a drain connected between the input end of the inverter and a second potential supply end, and a gate connected to the second output end of the bistable circuit;
a third MIS transistor whose drain (or source) is connected to the second output terminal of the bistable circuit and whose gate is connected to the output terminal of the inverter; and the source of the third MIS transistor. (or drain) and the first potential supply end, the fourth MIS transistor has a drain and a source connected to each other, and a gate connected to an activation signal input end of the next stage circuit. MIS circuit device.
JP60105515A 1985-05-17 1985-05-17 Mis circuit device Granted JPS61263308A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP60105515A JPS61263308A (en) 1985-05-17 1985-05-17 Mis circuit device
US06/864,652 US4771187A (en) 1985-05-17 1986-05-19 Bistable circuit
DE86106808T DE3689291D1 (en) 1985-05-17 1986-05-20 Bistable circuit.
EP86106808A EP0203491B1 (en) 1985-05-17 1986-05-20 Bistable circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60105515A JPS61263308A (en) 1985-05-17 1985-05-17 Mis circuit device

Publications (2)

Publication Number Publication Date
JPS61263308A true JPS61263308A (en) 1986-11-21
JPH0368567B2 JPH0368567B2 (en) 1991-10-29

Family

ID=14409735

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60105515A Granted JPS61263308A (en) 1985-05-17 1985-05-17 Mis circuit device

Country Status (1)

Country Link
JP (1) JPS61263308A (en)

Also Published As

Publication number Publication date
JPH0368567B2 (en) 1991-10-29

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