JPS61259560A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS61259560A
JPS61259560A JP60101908A JP10190885A JPS61259560A JP S61259560 A JPS61259560 A JP S61259560A JP 60101908 A JP60101908 A JP 60101908A JP 10190885 A JP10190885 A JP 10190885A JP S61259560 A JPS61259560 A JP S61259560A
Authority
JP
Japan
Prior art keywords
capacitor
metal
semiconductor integrated
integrated circuit
pelletizing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60101908A
Other languages
Japanese (ja)
Inventor
Kazuyoshi Ueda
植田　和良
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP60101908A priority Critical patent/JPS61259560A/en
Publication of JPS61259560A publication Critical patent/JPS61259560A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/162—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/10—Using electric, magnetic and electromagnetic fields; Using laser light
    • H05K2203/107—Using laser light
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/17—Post-manufacturing processes
    • H05K2203/171—Tuning, e.g. by trimming of printed components or high frequency circuits

Landscapes

  • Parts Printed On Printed Circuit Boards (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To enable the adjustment of the capacity value after pelletizing or assembling by dividing the top metal of an MIM capacitor into a plurality on a capacitor region, thereby connecting arbitrary number of component parts. CONSTITUTION:The surface of a substrate 10 is coated with an insulating film 209, and a capacitor primary metal 1 is formed on the film 20. A capacitor insulating film 2 is formed on the metal 1, and capacitor top metals 3-1-3-5 divided into a plurality are formed thereon. They are gathered to one through upper metal leading electrodes 4-1-4-5. Any of the electrodes 4-1-4-5 is cut by a laser trimmer to readily regulate the capacitor capacity value after pelletizing or assembling.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積回路、特に高周波用途のキャパシタ
によるマツチング回路を有する半導体集積回路に関する
。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit having a matching circuit using a capacitor for high frequency applications.

〔従来の技術〕[Conventional technology]

従来、この種の半導体集積回路は所定の大きさのＭＩＭ
（金属−絶縁物−金属）構造キャパシタを有していて、
絶縁膜の厚さが決まればその容量値は一定になり、後工
程での容量値の調整は難しかった。Conventionally, this type of semiconductor integrated circuit has a MIM of a predetermined size.
It has a (metal-insulator-metal) structure capacitor,
Once the thickness of the insulating film is determined, its capacitance value remains constant, making it difficult to adjust the capacitance value in post-processing.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

マツチング回路を有する高周波用半導体集積回路におい
ては、設計値通りの特性を実現することは必すしも容易
でなく、設計性の不確定さや製造プロセスの不安定さか
ら周波数特性のずれが認められる場合が多い。In high-frequency semiconductor integrated circuits with matching circuits, it is not always easy to achieve characteristics as designed, and deviations in frequency characteristics may be observed due to uncertainty in design or instability in the manufacturing process. There are many.

しかしながら従来の構造のキャパシタを使用した場合、
容量値を後工程ないしベレソタイズ後に変更することは
、不可能であり高歩留が期待出来なかった。However, when using a capacitor with a conventional structure,
It is impossible to change the capacitance value in a post-process or after veresotization, and a high yield cannot be expected.

本発明の目的は、上記従来構造の欠点をなくし後工程な
いし、ベレッタイズ後にキャパシタ容量値をある程度の
範囲に渡り調整することが可能なＭＩＭキャパシタ構造
を提供する。An object of the present invention is to provide an MIM capacitor structure that eliminates the drawbacks of the conventional structure and allows the capacitance value of the capacitor to be adjusted over a certain range in a post-process or after pelletizing.

〔問題点を解決するための手段〕[Means for solving problems]

本発明のべ４　Ｉ　Ｍキャパシタの構造は、上部メタル
がキャパシタ領域上では、複数個に分割されていて、キ
ャパシタ外部領域で接続されている。かかる本発明の構
造のＭＩＭキャパシタの場合は、各々分割されている上
部メタルの引出し電極部をレーザートリマー等の装置を
用いて切断することで任意の個数の上部分割メタルの接
続が可能で、ペレッタイズ後や組立後に容量値の調整に
よるマツチング回路の最適化が可能となる。In the structure of the 4IM capacitor of the present invention, the upper metal is divided into a plurality of parts on the capacitor region and connected in the region outside the capacitor. In the case of the MIM capacitor having the structure of the present invention, it is possible to connect any number of upper metal parts by cutting the lead electrode part of each divided upper metal part using a device such as a laser trimmer, and pelletizing. It is possible to optimize the matching circuit by adjusting the capacitance value afterwards or after assembly.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図は本発明の一実施例の平面図である。第２図は第
１図におけるＡ−Ａ’線断面図である。FIG. 1 is a plan view of one embodiment of the present invention. FIG. 2 is a sectional view taken along the line AA' in FIG. 1.

１０は半導体基板であり、これに少なくとも一つの素子
が形成される。基板１００表面は絶縁膜２０で覆われ、
膜２０上には、キャパシタ下地メタル（例えば、す）１
が形成されている。メタル１上にはキャパシタ絶縁膜（
例えば、５ｉＯｚ）２が形成され、さらにその上に、複
数に分割されたキャパシタ上部メタル（例えばＡ−ｅ）
３−１乃至３−５が形成されている。これらは上部メタ
ル引出し電極４−１乃至４−５を介して一つにまとめら
れている。10 is a semiconductor substrate on which at least one element is formed. The surface of the substrate 100 is covered with an insulating film 20,
On the film 20, a capacitor base metal (for example, metal) 1 is provided.
is formed. A capacitor insulating film (
For example, 5iOz)2 is formed, and on top of that, a capacitor upper metal divided into a plurality of parts (e.g. A-e) is formed.
3-1 to 3-5 are formed. These are integrated into one via upper metal lead electrodes 4-1 to 4-5.

第３図は、トリミング後の平面図を示す。第３図に図示
した様に引出し電極部（実施例では、４−４および４−
５）をレーザートリマー等で切断することで、キャパシ
タ容量値を調整することが出来る。FIG. 3 shows a plan view after trimming. As shown in FIG.
By cutting 5) with a laser trimmer or the like, the capacitance value of the capacitor can be adjusted.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明の半導体集積回路は、マツ
チング用のＭＩＭのキャパシタの容量値をベレッタイズ
後や組立後に調整することが容易に出来る為、マツチン
グ回路の最適化が可能となる為、歩留の著しい向上が期
待出来る。As explained above, in the semiconductor integrated circuit of the present invention, the capacitance value of the MIM capacitor for matching can be easily adjusted after pelletizing or assembly, so the matching circuit can be optimized. A significant improvement in retention can be expected.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例の平面図、第２図は第１図の
Ａ−Ａ’線断面図、第３図は第１図のもののトリミング
後の平面図である。 代理人　弁理士　　内　原　　　皿・′−′艷・・・１
．１、　　゛ ワ　　　・ ＼−′・・FIG. 1 is a plan view of an embodiment of the present invention, FIG. 2 is a sectional view taken along the line AA' in FIG. 1, and FIG. 3 is a plan view of the structure shown in FIG. 1 after trimming. Agent Patent Attorney Uchihara Sara・'-'艷...1
．． 1. ゛wa・＼−′・・

Claims (1)

【特許請求の範囲】[Claims] 　金属−絶縁層−金属構造キャパシターを有する半導体
集積回路において、該キャパシタの上部金属が複数個に
分割されていて、夫々は引き出し電極を介してキャパシ
タ領域外部に導出されて一つにまとめられ、該引き出し
電極を切断出来ることを特徴とする半導体集積回路。In a semiconductor integrated circuit having a metal-insulating layer-metal structure capacitor, the upper metal of the capacitor is divided into a plurality of parts, each of which is led out to the outside of the capacitor region via an extraction electrode and brought together into one. A semiconductor integrated circuit characterized in that the extraction electrode can be cut.
JP60101908A 1985-05-14 1985-05-14 Semiconductor integrated circuit Pending JPS61259560A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60101908A JPS61259560A (en) 1985-05-14 1985-05-14 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60101908A JPS61259560A (en) 1985-05-14 1985-05-14 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS61259560A true JPS61259560A (en) 1986-11-17

Family

ID=14313005

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60101908A Pending JPS61259560A (en) 1985-05-14 1985-05-14 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS61259560A (en)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6425452A (en) * 1987-07-21 1989-01-27 Mitsubishi Electric Corp Semiconductor device
US5233310A (en) * 1991-09-24 1993-08-03 Mitsubishi Denki Kabushiki Kaisha Microwave integrated circuit
US5583359A (en) * 1995-03-03 1996-12-10 Northern Telecom Limited Capacitor structure for an integrated circuit
EP1517596A2 (en) * 2003-09-18 2005-03-23 E.I. du Pont de Nemours and Company High tollerance embedded capacitors
US6974744B1 (en) 2000-09-05 2005-12-13 Marvell International Ltd. Fringing capacitor structure
US6980414B1 (en) 2004-06-16 2005-12-27 Marvell International, Ltd. Capacitor structure in a semiconductor device
US7906424B2 (en) 2007-08-01 2011-03-15 Advanced Micro Devices, Inc. Conductor bump method and apparatus
US8314474B2 (en) 2008-07-25 2012-11-20 Ati Technologies Ulc Under bump metallization for on-die capacitor
US8941974B2 (en) 2011-09-09 2015-01-27 Xilinx, Inc. Interdigitated capacitor having digits of varying width
US9270247B2 (en) 2013-11-27 2016-02-23 Xilinx, Inc. High quality factor inductive and capacitive circuit structure
US9524964B2 (en) 2014-08-14 2016-12-20 Xilinx, Inc. Capacitor structure in an integrated circuit
EP2012421A4 (en) * 2006-04-25 2017-02-22 Sumida Corporation Inverter circuit

Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6425452A (en) * 1987-07-21 1989-01-27 Mitsubishi Electric Corp Semiconductor device
US5233310A (en) * 1991-09-24 1993-08-03 Mitsubishi Denki Kabushiki Kaisha Microwave integrated circuit
US5583359A (en) * 1995-03-03 1996-12-10 Northern Telecom Limited Capacitor structure for an integrated circuit
US6974744B1 (en) 2000-09-05 2005-12-13 Marvell International Ltd. Fringing capacitor structure
US9017427B1 (en) 2001-01-18 2015-04-28 Marvell International Ltd. Method of creating capacitor structure in a semiconductor device
EP1517596A3 (en) * 2003-09-18 2006-11-02 E.I. du Pont de Nemours and Company High tollerance embedded capacitors
EP1517596A2 (en) * 2003-09-18 2005-03-23 E.I. du Pont de Nemours and Company High tollerance embedded capacitors
US7578858B1 (en) 2004-06-16 2009-08-25 Marvell International Ltd. Making capacitor structure in a semiconductor device
US7116544B1 (en) 2004-06-16 2006-10-03 Marvell International, Ltd. Capacitor structure in a semiconductor device
US7988744B1 (en) 2004-06-16 2011-08-02 Marvell International Ltd. Method of producing capacitor structure in a semiconductor device
US8537524B1 (en) 2004-06-16 2013-09-17 Marvell International Ltd. Capacitor structure in a semiconductor device
US6980414B1 (en) 2004-06-16 2005-12-27 Marvell International, Ltd. Capacitor structure in a semiconductor device
EP2012421A4 (en) * 2006-04-25 2017-02-22 Sumida Corporation Inverter circuit
US7906424B2 (en) 2007-08-01 2011-03-15 Advanced Micro Devices, Inc. Conductor bump method and apparatus
US8294266B2 (en) 2007-08-01 2012-10-23 Advanced Micro Devices, Inc. Conductor bump method and apparatus
US8314474B2 (en) 2008-07-25 2012-11-20 Ati Technologies Ulc Under bump metallization for on-die capacitor
US8941974B2 (en) 2011-09-09 2015-01-27 Xilinx, Inc. Interdigitated capacitor having digits of varying width
US9270247B2 (en) 2013-11-27 2016-02-23 Xilinx, Inc. High quality factor inductive and capacitive circuit structure
US9524964B2 (en) 2014-08-14 2016-12-20 Xilinx, Inc. Capacitor structure in an integrated circuit

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