JPS61248450A - Package sealing structure of semiconductor device - Google Patents
Package sealing structure of semiconductor deviceInfo
- Publication number
- JPS61248450A JPS61248450A JP8862185A JP8862185A JPS61248450A JP S61248450 A JPS61248450 A JP S61248450A JP 8862185 A JP8862185 A JP 8862185A JP 8862185 A JP8862185 A JP 8862185A JP S61248450 A JPS61248450 A JP S61248450A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- housing
- semiconductor device
- solder
- sealing structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は半導体デバイスを実装したパッケージの封止構
造に係シ、特に半導体デバイスを搭載する基板と、半導
体デバイスｔａって基板上に設置されるハウジングとの
接合に関する。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a sealing structure for a package mounted with a semiconductor device, and particularly relates to a substrate on which a semiconductor device is mounted and a semiconductor device installed on the substrate. Regarding connection with the housing.
半導体デバイスを実装したパッケージの封止構造につい
ては、例えば特開昭５２−５３５４７号に示されている
。この封止構造は、半導体デバイスを搭載したセラミッ
クス基板（以下、単に基板という）、額ぶちの如く形成
された７ランジおよびキャップを主な燐酸とし、基板の
外周部と７ランジの内周部とを銀ろう付けする一方、７
ランジの外周部とキャンプとの対向面間に環状ガスケン
トを配置し、かつフランジとキャンプとの保合状態をク
ランプ部材によシ維持して封止全行っている。A sealing structure for a package in which a semiconductor device is mounted is disclosed in, for example, Japanese Patent Laid-Open No. 52-53547. This sealing structure consists of a ceramic substrate (hereinafter simply referred to as a substrate) on which a semiconductor device is mounted, a 7-lunge formed like a frame, and a cap using phosphoric acid as the main component, and an outer periphery of the substrate and an inner periphery of the 7-lunge. While silver soldering, 7
An annular gasket is disposed between the facing surface of the outer circumference of the flange and the camp, and the flange and the camp are maintained in a secured state by a clamp member for complete sealing.
また、半導体デバイスからの熱の除去は、前記キャップ
に取付けた冷却手段により行っている。Further, heat is removed from the semiconductor device by a cooling means attached to the cap.
前記の封止構造においては、基板とキャンプが機械的に
係合されていることから、半導体デバイスの通電時の発
熱によるパッケージの温度変化に対して、該保合部の熱
応力（熱膨張差）の軽減のために基板とキャンプの線膨
脹係数の整合をとる必要がない。従って、キャップ材料
として、例えばアルミニウムのような高い熱伝導率を有
する材料が使用でき、半導体デバイスの冷却上有利であ
る。しかし、前述の封止構造では、封止のための７ラン
ジ、クランプ部分が基板の外に張シ出すため、パッケー
ジ相互間の配線距離が長くなる。このため、複数のパッ
ケージからなるシステム全体の信号遅延が増大するとい
う欠点が委った。In the above-mentioned sealing structure, since the substrate and the camp are mechanically engaged, the thermal stress (thermal expansion difference) of the retaining portion is reduced against the temperature change of the package due to heat generated when the semiconductor device is energized. ) There is no need to match the linear expansion coefficients of the substrate and the camp to reduce this. Therefore, a material having high thermal conductivity, such as aluminum, can be used as the cap material, which is advantageous for cooling the semiconductor device. However, in the above-described sealing structure, the seven flange and clamp portions for sealing protrude outside the substrate, resulting in a long wiring distance between the packages. As a result, the signal delay of the entire system consisting of a plurality of packages increases.
また、他の従来の封止構造として、例えば特開昭５８−
２２５６５９号に示されたものがある。この封止構造は
、基板（セラミックス）にコバール製フランジをはんだ
接合する一方、該７う／ジの端面と、キャップとしての
ハウジング枠の端面とを対向させ、はんだによシ突き合
せ接着して封止２行っている。この封止構造においては
、キャップと基板とを機械的に係合させるに必要な大き
なクランプ部がなく、小形化できる利点を有する。In addition, as other conventional sealing structures, for example, JP-A-58-
There is one shown in No. 225659. In this sealing structure, a Kovar flange is soldered to a substrate (ceramics), and the end face of the 7/J is opposed to the end face of a housing frame serving as a cap, and they are butt-bonded together with solder. Sealing 2 is in progress. This sealing structure does not have a large clamp part necessary for mechanically engaging the cap and the substrate, and has the advantage of being compact.
しかし、半導体デバイスの発熱あるいは接合時の加熱に
よシ、基板とハウジング枠との間で熱変形差が生じ、は
んだの接合力がこの変形に十分に抗しきれず、はんだの
割れなどにより封止が不十分となる恐れがある。さらに
詳しく説明すると、前記の熱変形差は基板とハウジング
枠とが接合されているための変形拘束から、接合部に大
きな応力およびひずみをもたらす。そして、これらの応
力、ひずみは接合材でおるはんだがボイドや巣を含んで
いる場合に増大し、接合部に割れや亀裂の発生全便す。However, due to heat generated by the semiconductor device or heating during bonding, a difference in thermal deformation occurs between the board and the housing frame, and the solder bonding force cannot sufficiently resist this deformation, resulting in cracks in the solder, etc. may be insufficient. More specifically, the difference in thermal deformation causes large stress and strain at the joint due to deformation restraint due to the bonding of the substrate and housing frame. These stresses and strains increase when the solder coated with the bonding material contains voids or cavities, leading to the occurrence of cracks and cracks in the bonded portion.
本発明の目的は、封止部の基板外への張り出しをなくし
、かつ接合部に割れ、亀裂が生ずることなく封止性能の
向上を図れる半導体デバイスのパッケージ封止構造を提
供することにある。An object of the present invention is to provide a package sealing structure for a semiconductor device that eliminates the protrusion of the sealing part to the outside of the substrate and improves the sealing performance without causing cracks or cracks in the joint part.
本発明は、１個または複数個の半導体デバイスを搭載す
る基板と、その基板と線膨脹係数の異なる材料で形成さ
れ、かつ箱形形状をなすハウジングとを備え、前記ハウ
ジングを半導体デバイスを覆った状態で基板上に設置し
、該ハウジングの下端面と基板の表面とを接合材を介し
て接合して両者の当接面を封止して成る半導体デバイス
のパッケージにおいて、ハウジング下端面と基板表面と
の接合後に、該ハウジングの基板への押圧を行うように
し、かつ前記の接合および押圧を真空または大気圧以下
の低圧雰囲気中にて行うようにして、封止部の基板外へ
の張シ出しをなくすと共に、封止性能の向上を図ったも
のである。即ち、本発明は、ハウジングの下端面と基板
の表面とを接合材を介して接合することによシ、封上部
を基板の外へ張り出さないようにして、パッケージ相互
間の配線距離の短縮化を図り、また接合を真空中または
低圧雰囲気中で行うことにより、接合材内へのボイドの
発生を防ぎ、かつ接合材の加熱に伴なって該接合材内部
で発生するガスを真空中または低圧雰囲気中に飛散させ
、さらにハウジングを押圧することによシ、接合材内部
に残留するボイドや巣を潰して局所的な応力集中を抑え
、基板とハウジングの熱変形差による接合部への応力、
ひずみを軽減して、該接合部の割れ５亀裂をなくシ、封
止性能の向上を図ったものでちる。The present invention includes a substrate on which one or more semiconductor devices are mounted, and a box-shaped housing made of a material having a coefficient of linear expansion different from that of the substrate, and the housing covers the semiconductor device. In a semiconductor device package, the lower end surface of the housing and the surface of the substrate are bonded to each other via a bonding material to seal the abutting surfaces of the two. After bonding with the housing, the housing is pressed against the substrate, and the bonding and pressing are performed in a vacuum or a low-pressure atmosphere below atmospheric pressure, thereby preventing the sealing portion from being stretched to the outside of the substrate. This aims to eliminate protrusion and improve sealing performance. That is, the present invention reduces the wiring distance between packages by bonding the lower end surface of the housing and the surface of the substrate via a bonding material, thereby preventing the sealing portion from protruding outside the substrate. In addition, by performing the bonding in a vacuum or in a low-pressure atmosphere, the generation of voids in the bonding material can be prevented, and the gas generated inside the bonding material as it is heated can be removed in a vacuum or in a low-pressure atmosphere. By scattering it in a low-pressure atmosphere and further pressing the housing, it collapses the voids and nests that remain inside the bonding material, suppressing local stress concentration, and reducing the stress on the bonded part due to the difference in thermal deformation between the board and the housing. ,
This material reduces strain, eliminates cracks in the joint, and improves sealing performance.
以下、本発明の一実施例を図面に基づいて説明する。第
１図は本発明による半導体デバイスのパッケージ封止構
造を一部断面して示す斜視図で。Hereinafter, one embodiment of the present invention will be described based on the drawings. FIG. 1 is a partially sectional perspective view showing a package sealing structure for a semiconductor device according to the present invention.
ハウジング全治具にて押圧している状態を示す。Shows the housing being pressed with all jigs.
図において、半導体デバイス２は、セラミックス基板（
以下、単に基板という）１の表面上において電気的に接
続されている複数個のはんだボール３上に取付けられて
いる。半導体デバイス２を覆うハウジング４は、基板１
０表面に当接する枠４Ａと、この枠４人の上方開口を塞
ぐ天井板４Ｂとから成る箱形の形状に形成されていると
共に、基板（セラミックス）１と線膨脹係数の異表る材
料（ｊｉｂ、アルミニウムなど）で一体成形されている
。また、ハウジング４の天井板４ＢＩＣは、該天井板４
Ｂ内面と半導体デバイス２との間に置かれて、半導体デ
バイス２の発熱を天井板４Ｂに伝える冷却手段５が設け
られている。そして、前記ハウジング４０枠４人と基板
１との当接面が接合されて封止されている。この封止は
１次のような工程で行われている。まず、枠４人の下端
面と、該下端面が当接する基板１の表面との間にはんだ
シート６を介在させ、高温にてリフローして枠４人と基
板１の接合を行う。冷却によるはんだの固化後に、図示
の如く、ハウジング４の天井板４Ｂ上面に治具７ｆ、当
接させ、かつパッケージをテーブル８上に設置し、前記
治具７に接合面に垂直方向の押圧力Ｐを与えて接合部の
はんだを加工硬化させる。前記の接合および押圧は、真
空中ｔたは大気圧以下の低圧雰囲気中にて行われる。ま
た、接合面の押圧時には、治具７による押圧力Ｐが接合
面全域に効率よく伝達されるように、該治具７の形状＊
、 ′Ｄ、合部と対応するハウジング４の天井板４Ｂ上
面を押圧できる箱形形状としておる。また、接合面の押
圧に際してに、ハウジング４が押圧された時基板１が割
れないように、該基板１を設置しているテーブル８とし
て、設置面が平面のテーブルを使用する。前記治具７へ
の押圧力Ｐの付与は１例えば油圧シリンダにて行われる
。In the figure, the semiconductor device 2 includes a ceramic substrate (
It is mounted on a plurality of solder balls 3 electrically connected on the surface of a substrate 1 (hereinafter simply referred to as a substrate). A housing 4 that covers the semiconductor device 2 includes a substrate 1
It is formed into a box shape consisting of a frame 4A that contacts the surface of the frame 4A and a ceiling plate 4B that closes the upper opening of the four frames. jib, aluminum, etc.). Moreover, the ceiling plate 4BIC of the housing 4 is
A cooling means 5 is provided between the inner surface of B and the semiconductor device 2 to transmit heat generated by the semiconductor device 2 to the ceiling plate 4B. Then, the contact surfaces of the four frames of the housing 40 and the substrate 1 are joined and sealed. This sealing is performed in the following steps. First, a solder sheet 6 is interposed between the lower end surfaces of the four members of the frame and the surface of the substrate 1 with which the lower end surfaces come into contact, and the four members and the board 1 are joined by reflowing at a high temperature. After the solder is solidified by cooling, the jig 7f is brought into contact with the upper surface of the ceiling plate 4B of the housing 4, and the package is placed on the table 8, as shown in the figure, and the jig 7 is applied with a pressing force in a direction perpendicular to the bonding surface. P is applied to work harden the solder at the joint. The above bonding and pressing are performed in a vacuum or in a low pressure atmosphere below atmospheric pressure. In addition, when pressing the joint surface, the shape of the jig 7 *
, 'D, has a box-like shape that can press against the upper surface of the ceiling plate 4B of the housing 4 corresponding to the joint part. Further, in order to prevent the substrate 1 from breaking when the housing 4 is pressed when pressing the joint surface, a table with a flat installation surface is used as the table 8 on which the substrate 1 is installed. The pressing force P is applied to the jig 7 using, for example, a hydraulic cylinder.
ＦＪｇ２図は治具を押圧する油圧シリンダおよびその操
作回路を示し、治具７は油圧クリ／ダ９のロッド９ａの
先端に取付けられていて、該油圧シリンダ９のロッド９
ａの伸縮によシ押圧と押圧解除が行われるようになって
いる。油圧シリンダ９の伸縮動作は操作回路に具えた電
磁式の方向切換弁１０にて行い、また治具７への押圧力
の設定はレデューシング弁１１にて、押圧力の検出は圧
力計１２にて、かつ、押圧力の過負荷防止はリリーフ弁
１３にてそれぞれ行うようになっている。尚、１４は油
圧ポンプを示す。Figure FJg2 shows a hydraulic cylinder that presses a jig and its operating circuit.
Pressure and release of the pressure are performed by the expansion and contraction of a. The expansion and contraction of the hydraulic cylinder 9 is performed by an electromagnetic directional valve 10 provided in the operation circuit, the pressing force on the jig 7 is set by a reducing valve 11, and the pressing force is detected by a pressure gauge 12. , and overload of the pressing force is prevented by a relief valve 13. Note that 14 indicates a hydraulic pump.
この操作回路において、方向切換弁１０を′図示の位置
に切換えると、油圧シリンダ９０ロンド９ａが伸長して
治具７に押圧力を与える。りまシ治具７ｆｅ介してハウ
ジング４を基板１側へ押圧することができる。In this operation circuit, when the directional control valve 10 is switched to the illustrated position, the hydraulic cylinder 90 and the cylinder 9a extend to apply a pressing force to the jig 7. The housing 4 can be pressed toward the substrate 1 via the reshaping jig 7fe.
前記の如き構成としたパッケージ封止構造においては、
ハウジング４の枠４人下端面を基板１の表面に接合させ
て封止を行っているので、該封止部に基板１外へ張シ出
すものが存在せず、パッケージ相互間の配線距離を短縮
できる。その結果。In the package sealing structure configured as described above,
Since the lower end surfaces of the four frames of the housing 4 are joined to the surface of the board 1 for sealing, there is no part of the seal that extends outside the board 1, and the wiring distance between the packages can be reduced. Can be shortened. the result.
複数のパッケージからなるシステム全体の信号遅延の増
大を防止できる。It is possible to prevent an increase in signal delay in the entire system consisting of multiple packages.
また、封正に際しての接合を真空中または低圧雰囲気中
で行っているので、・はんだシート６内へのボイドの発
生を防ぐことができ、かつはんだシート６の加熱の際に
該はんだシート６内部で発生するガスが真空中または低
圧雰囲気中に飛散し。In addition, since the bonding during sealing is performed in a vacuum or in a low-pressure atmosphere, it is possible to prevent voids from forming inside the solder sheet 6, and when the solder sheet 6 is heated, the inside of the solder sheet 6 is The gas generated is scattered into a vacuum or low pressure atmosphere.
さらにはんだ固化後の治具７の押圧によシ、はんだ内部
に残留するボイドや巣が潰されて局所的な応力集中が抑
えられるので、基板１とハウジング４の熱変形差による
接合部への応力、ひずみが軽減１６．舷増介郁の創Ｉｆ
′Ｌ、、亀ｚづ；訪ｒμ代れ六−その結果、封止部の性
能が向上する。Furthermore, by pressing the jig 7 after the solder has solidified, voids and nests remaining inside the solder are crushed and localized stress concentration is suppressed. Reduced stress and strain16. Iku no Sosuke's Creation If
As a result, the performance of the sealing part is improved.
尚、完成品としてのパッケージにおいては、ハウジング
４の天井板４Ｂ上面に、半導体デバイス２の冷却を促進
する流体を通す冷却ジャケットが、かつ基板１の裏面に
、半導体デバイス２を外部回路に接続するためのピンが
それぞれ設けられる。In addition, in the package as a completed product, a cooling jacket for passing a fluid that promotes cooling of the semiconductor device 2 is provided on the top surface of the ceiling plate 4B of the housing 4, and a cooling jacket for connecting the semiconductor device 2 to an external circuit is provided on the back surface of the substrate 1. A pin is provided for each.
以上の如く、本発明によれば、封止部の基板外への張り
出しをなくせるので、パッケージ相互間の配線距離を短
縮化でき、また接合部の割れ、亀裂を防止できるので、
封止性能の向上を図れる。As described above, according to the present invention, it is possible to eliminate the protrusion of the sealing part to the outside of the substrate, so that the wiring distance between packages can be shortened, and cracks and cracks in the joint part can be prevented.
Sealing performance can be improved.
第１図、＄２図は本発明の一実施例を示し、第１図は本
発明によるパッケージ封止構造を一部断面して示す斜視
図で、ハウジング全治具にて押圧している状態を示す。
第２図は第１図の治具を押圧するための油圧シリンダお
よびその操作回路図である。
１・・・セラミックス基板、２・・・半導体デバイス、
４・・・ハウジング、４Ａ・・・枠、４Ｂ・・・天井板
、６・・・はんだシート、７・・・治具、８・・・油圧
シリンダ。Figures 1 and 2 show an embodiment of the present invention. Figure 1 is a perspective view, partially in section, of the package sealing structure according to the present invention, showing a state in which the entire housing is pressed with a jig. show. FIG. 2 is a diagram of a hydraulic cylinder for pressing the jig shown in FIG. 1 and its operation circuit. 1... Ceramic substrate, 2... Semiconductor device,
4...Housing, 4A...Frame, 4B...Ceiling plate, 6...Solder sheet, 7...Jig, 8...Hydraulic cylinder.
Claims (1)
と、その基板と線膨脹係数の異なる材料で形成され、か
つ箱形形状をなすハウジングとを備え、前記ハウジング
を半導体デバイスを覆つた状態で基板上に設置し、該ハ
ウジングの下端面と基板の表面とを接合材を介して接合
して両者の当接面を封止して成る半導体デバイスのパッ
ケージにおいて、ハウジング下端面と基板表面との接合
後に、該ハウジングの基板への押圧を行うようにし、か
つ前記の接合および押圧を真空または大気圧以下の低圧
雰囲中にて行うようにしたことを特徴とする半導体デバ
イスのパッケージ封止構造。 ２、特許請求の範囲第１項において、前記接合材が、は
んだシートであることを特徴とする半導体デバイスのパ
ッケージ封止構造。 ３、特許請求の範囲第１項において、前記ハウジングの
基板への押圧を油圧シリンダにて行うことを特徴とする
半導体デバイスのパッケージ封止構造。[Scope of Claims] 1. A substrate on which one or more semiconductor devices are mounted, and a box-shaped housing made of a material having a coefficient of linear expansion different from that of the substrate; In a semiconductor device package, the lower end surface of the housing is placed on a substrate with the device covered, and the lower end surface of the housing is bonded to the surface of the substrate via a bonding material to seal the abutting surfaces of the two. A semiconductor characterized in that after the end face and the substrate surface are bonded, the housing is pressed against the substrate, and the bonding and pressing are performed in a vacuum or in a low pressure atmosphere below atmospheric pressure. Device package sealing structure. 2. The package sealing structure for a semiconductor device according to claim 1, wherein the bonding material is a solder sheet. 3. The package sealing structure for a semiconductor device according to claim 1, wherein the housing is pressed against the substrate by a hydraulic cylinder.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8862185A JPS61248450A (en) | 1985-04-26 | 1985-04-26 | Package sealing structure of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8862185A JPS61248450A (en) | 1985-04-26 | 1985-04-26 | Package sealing structure of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61248450A true JPS61248450A (en) | 1986-11-05 |
Family
ID=13947875
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8862185A Pending JPS61248450A (en) | 1985-04-26 | 1985-04-26 | Package sealing structure of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61248450A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010134369A1 (en) * | 2009-05-22 | 2010-11-25 | 国際計測器株式会社 | Hydraulic system and general-purpose test device |
| CN103262235A (en) * | 2010-12-16 | 2013-08-21 | 株式会社村田制作所 | Method for manufacturing electronic component |
-
1985
- 1985-04-26 JP JP8862185A patent/JPS61248450A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010134369A1 (en) * | 2009-05-22 | 2010-11-25 | 国際計測器株式会社 | Hydraulic system and general-purpose test device |
| JP2011007781A (en) * | 2009-05-22 | 2011-01-13 | Kokusai Keisokki Kk | Hydraulic system and universal testing device |
| KR101362115B1 (en) * | 2009-05-22 | 2014-02-21 | 고쿠사이 게이소쿠키 가부시키가이샤 | Hydraulic system and general-purpose test device |
| CN103262235A (en) * | 2010-12-16 | 2013-08-21 | 株式会社村田制作所 | Method for manufacturing electronic component |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6173489B1 (en) | Organic substrate (PCB) slip plane “stress deflector” for flip chip devices | |
| US6326679B1 (en) | Low cost heat sink for packaged semiconductor device | |
| JPS61248450A (en) | Package sealing structure of semiconductor device | |
| JP4380442B2 (en) | Manufacturing method of semiconductor device | |
| JPH03228339A (en) | Bonding tool | |
| JPH0316159A (en) | Electronic device | |
| JPS61248451A (en) | Package sealing structure of semiconductor device | |
| JPH01309343A (en) | Mounting of semiconductor device | |
| JPH0969618A (en) | Ccd solid-state image pickup device chip package and its packaging method | |
| JPS61248449A (en) | Package sealing structure of semiconductor device | |
| JPH11204693A (en) | Semiconductor device | |
| JP7415486B2 (en) | Insulated circuit board with heat sink and method for manufacturing the same | |
| JPH02130864A (en) | Die pad structure for lead frame | |
| JP3056159B2 (en) | Hermetic sealing method for semiconductor package and resistance welding apparatus to which the method is applied | |
| JPH0680750B2 (en) | Semiconductor device | |
| JP2870366B2 (en) | Film sticking device for lead frame | |
| JP2740430B2 (en) | Sealing method | |
| JPH1140607A (en) | Manufacture of semiconductor device and sealing member | |
| JPH0629418A (en) | Package for electronic component | |
| JP2842854B2 (en) | Method for manufacturing semiconductor device | |
| JPS63248155A (en) | Semiconductor device | |
| JP2006173509A (en) | Semiconductor device and manufacturing method therefor | |
| JP2796401B2 (en) | Semiconductor integrated circuit device | |
| JP2001230367A (en) | Semiconductor device | |
| JPH06244335A (en) | Resin-sealed semiconductor device |