JPS61248427A - Formation of multilayer interconnection - Google Patents
Formation of multilayer interconnectionInfo
- Publication number
- JPS61248427A JPS61248427A JP60089315A JP8931585A JPS61248427A JP S61248427 A JPS61248427 A JP S61248427A JP 60089315 A JP60089315 A JP 60089315A JP 8931585 A JP8931585 A JP 8931585A JP S61248427 A JPS61248427 A JP S61248427A
- Authority
- JP
- Japan
- Prior art keywords
- film
- wiring
- photoresist
- alignment
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000015572 biosynthetic process Effects 0.000 title abstract description 3
- 238000000034 method Methods 0.000 claims abstract description 17
- 239000004065 semiconductor Substances 0.000 claims description 5
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 21
- 239000000758 substrate Substances 0.000 abstract description 7
- 229910052751 metal Inorganic materials 0.000 abstract description 5
- 239000002184 metal Substances 0.000 abstract description 5
- 238000009413 insulation Methods 0.000 abstract 3
- 239000011347 resin Substances 0.000 abstract 1
- 229920005989 resin Polymers 0.000 abstract 1
- 229910052782 aluminium Inorganic materials 0.000 description 26
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 26
- 239000010410 layer Substances 0.000 description 24
- 229920001721 polyimide Polymers 0.000 description 12
- 239000009719 polyimide resin Substances 0.000 description 12
- 239000011229 interlayer Substances 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 230000007257 malfunction Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 235000006732 Torreya nucifera Nutrition 0.000 description 1
- 244000111306 Torreya nucifera Species 0.000 description 1
- 206010047513 Vision blurred Diseases 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229920006268 silicone film Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は多層配線の形成方法に関し、特に金属配線間に
絶縁膜を設けて形成される半導体集積回路の多層配線の
形成方法に関するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for forming multilayer wiring, and more particularly to a method for forming multilayer wiring in a semiconductor integrated circuit formed by providing an insulating film between metal wirings. .
従来、集積回路等の半導体素子の多層配線において、目
合せ露光方法として縮小投影露光法を用いる場合、レー
サ゛＝光によりウェノ〜の位置を検出し、マスクの投影
像とウニへ〇目合せを行うため、ウェハ上に位置合せ用
マークを形成するが、そのマークとしては、シリコン基
板、多結晶シリコン。Conventionally, when using the reduction projection exposure method as an alignment exposure method in multilayer wiring of semiconductor devices such as integrated circuits, the position of the mask is detected by laser light, and the projected image of the mask is aligned with the mask. Therefore, alignment marks are formed on the wafer, and these marks are made of silicon substrates and polycrystalline silicon.
アルミニウム等が使われていた。Aluminum was used.
第２図（ａ）〜（ｄ）は従来の多層配線の形成方法の一
例を説明するために工程順に示した断面図である。FIGS. 2(a) to 2(d) are cross-sectional views shown in order of steps to explain an example of a conventional method for forming multilayer wiring.
第２図（ａ）〜（ｄ＋においては、眉間絶＠膜にポリイ
ミド樹脂を利用したアルミニウム二層配線の形成方法に
つき説明する。In FIGS. 2(a) to 2(d+), a method for forming a two-layer aluminum wiring using polyimide resin for the glabellar membrane will be described.
まず、第２図＜ａ＞に示すように、表面がシリコン酸化
膜２２で覆われたシリコン基板２１上に第一層アルミニ
ウム電極配線２３を形成すると同時に位置合せ用マーク
２４を形成する。次いでポリイミド樹脂２５に所望の開
孔部を設けるためにフォトレジスト膜２６でポリイミド
樹脂２５を覆いレーザー光２７ｔ−位置合せ用マーク部
２４に照射し、アルミニウムにより形成されたマークの
段部で乱反射されたレーザー光のうら、るる一定の角度
、たとえば４５°の角度で反射されたレーザー光２８を
フォトダイオード２９で検出し、強度がピークとなる位
置をマスクの投影像とウェハとの目合せ位置として露光
を行う。First, as shown in FIG. 2<a>, a first layer of aluminum electrode wiring 23 is formed on a silicon substrate 21 whose surface is covered with a silicon oxide film 22, and alignment marks 24 are formed at the same time. Next, in order to form a desired opening in the polyimide resin 25, the polyimide resin 25 is covered with a photoresist film 26, and a laser beam 27t is irradiated onto the alignment mark portion 24, and is diffusely reflected by the stepped portion of the mark formed of aluminum. A photodiode 29 detects the laser beam 28 reflected at a constant angle, for example, at a 45° angle, and the position where the intensity peaks is determined as the alignment position between the projected image of the mask and the wafer. Perform exposure.
次に、第２図（１））に示すように、フォトレジスト膜
２６を現像し、第一層アルミニウムを惚配線領域上の７
オトレジスト膜２６に開孔部を設ける。Next, as shown in FIG. 2(1)), the photoresist film 26 is developed, and the first layer aluminum is coated in the 7 regions above the exposed wiring area.
Openings are provided in the photoresist film 26.
次に、第２図（Ｃ）に示すように、上記フォトレジスト
膜２６ｔ−マスクにしてポリイミド樹脂膜２５に第一層
アルミニウム［他配線２３に遅する開孔部３０ｔ−設け
、その後フォトレジスト膜２６を除去する。Next, as shown in FIG. 2C, the photoresist film 26t is used as a mask to form a first layer of aluminum on the polyimide resin film 25 (an opening 30t for the other wiring 23), and then the photoresist film is 26 is removed.
次に、第２図け）に示すようＶＣ、シリコン基板全面に
スパッタリング法によりアルミニウム膜３１を被着した
のら、フォトレジスト膜３２で覆い第二層アルミニウム
電極配線を設けるため目合せ露光を行い、現像後エンチ
ングにより第二層目配線を形成する。Next, as shown in Figure 2, an aluminum film 31 is deposited on the entire surface of the VC and silicon substrate by sputtering, and then covered with a photoresist film 32 and aligned exposure is performed to provide a second layer of aluminum electrode wiring. , a second layer wiring is formed by etching after development.
しかしながら第２図（ａ）〜（ｄｌの方法において、第
二層アルミニウムを樵配線を設けるための目合せ露光に
おいて、この時、位置合せ用のマーク部２４がポリイミ
ド樹脂により平坦化されているためアルミニウム膜３２
はマーク段部がなく、位置合せ用レーザー光２７は伝導
体を通り抜けることができず平坦なアルミニウム膜３１
０表面で乱反射されるのみで位置合せが不可能となると
いう欠点を生ずる。また、完全に平坦化されていなくて
も、シリカフィルム塗布などにより一層目アルミニウム
配線段部をなめらかにする場合にも段部がなめらかなた
め反射光のピークを判断することが困難となり目すれが
多発するという欠点がおる。However, in the method shown in FIGS. 2(a) to (dl), during the alignment exposure for forming the second layer aluminum to provide the wiring, the alignment mark portion 24 is flattened by the polyimide resin. Aluminum film 32
There is no mark step, and the alignment laser beam 27 cannot pass through the conductor, so the aluminum film 31 is flat.
This results in the disadvantage that positioning is impossible due to only diffuse reflection from the 0 surface. Furthermore, even if the stepped portions of the first layer of aluminum wiring are smoothed by coating with silica film, even if they are not completely flattened, the stepped portions are smooth, making it difficult to judge the peak of the reflected light, resulting in blurred vision. It has the disadvantage that it occurs frequently.
また層間絶縁膜としてバイアススパッタ酸化膜を用いて
も表面が平坦化されるので上記したと同様にレーザ光に
よるマークの位置検出が困難になる。Furthermore, even if a bias sputtered oxide film is used as the interlayer insulating film, the surface is flattened, making it difficult to detect the position of the mark using laser light, as described above.
本発明は、従来の上記欠点を除去し、眉間絶縁膜の段部
をなめらかにしても位置合せ狙差を小さくすることがで
き、たとえ完全に平坦化しても上層の金属配線をｎ度よ
く形成することができ、微細配線の形成が容易にできる
多層配線の形成方法を提供することを目的とする。The present invention eliminates the above-mentioned drawbacks of the conventional method, makes it possible to reduce the alignment difference even if the stepped part of the glabella insulating film is made smooth, and even if it is completely flattened, the upper layer metal wiring can be formed with n degree of accuracy. It is an object of the present invention to provide a method for forming multilayer wiring that can easily form fine wiring.
ｃ問題点を解決するだめの手段〕
本発明の多層配線の形成方法は、配線層間に絶縁膜を設
けて形成される半導体集積回路の多層配線の形成を縮小
投影露光法により目合せ露光を行う際、絶縁膜に選択的
に開孔部を設ける工程において、該絶縁膜に同時に新た
な位置合せ用マークを形成し、該位置合せ用７−りを使
用し前記絶縁膜上Ｖこ形成された次の層の電極配線の目
合せ露光を行うことにより構成される。[Means for Solving Problem c] The method for forming multilayer wiring of the present invention involves aligning exposure using a reduction projection exposure method to form multilayer wiring of a semiconductor integrated circuit formed by providing an insulating film between wiring layers. At this time, in the step of selectively forming openings in the insulating film, new alignment marks are simultaneously formed in the insulating film, and V marks are formed on the insulating film using the alignment tool. It is constructed by aligning and exposing the electrode wiring of the next layer.
次に、本発明について図面１ｆｒ：参照して説明する。 Next, the present invention will be described with reference to drawing 1fr.
第１図（ａ）〜（ｅ）は本発明の一実施例を説明するた
めに工程順に示した断面図でおる。本実施例では層間絶
縁膜にポリイミド樹脂を用いた場合のアルミニウム二層
配線の形成方法について説明する。FIGS. 1(a) to 1(e) are cross-sectional views shown in the order of steps for explaining an embodiment of the present invention. In this embodiment, a method for forming a two-layer aluminum wiring when polyimide resin is used for the interlayer insulating film will be described.
まず、第１図（ａ）に示すように、表面がシリコン販化
膜２で覆われたシリコン基板１上に一層目アルミニウム
電億配線３を形成する。その際同時にアルミニウムによ
）縮小投影露光の位置合せ用マーク４を設ける。次にポ
リイミド樹脂５により層間絶縁膜を形成した後、このポ
リイミド樹脂膜５に、第１層目アルミニウム３に運する
所望の開孔部を設けるために７オトレジスト６で稜いレ
ーザー光７をマーク部４に照射しアルミニウムにより形
成された７−り４の段部で乱反射されたレーザー光のう
らある一定の角度、たとえは４５″の角度で反射された
レーザー光８だけをフォトダイオード９で検出する。ウ
ェーハを水平方向に移動させ、フォトダイオード９で検
出したレーザー光８０強度がピークとなる位置をマスク
の投影像とつ工−ハの目合せ位置として露光を行なう。First, as shown in FIG. 1(a), a first layer of aluminum wiring 3 is formed on a silicon substrate 1 whose surface is covered with a silicone film 2. As shown in FIG. At the same time, alignment marks 4 (made of aluminum) for reduction projection exposure are provided. Next, after forming an interlayer insulating film with polyimide resin 5, a ridged laser beam 7 is marked on the polyimide resin film 5 with a photoresist 6 in order to provide a desired opening leading to the first layer aluminum 3. The photodiode 9 detects only the laser beam 8 reflected at a certain angle, for example, at an angle of 45'', behind the laser beam irradiated onto the part 4 and diffusely reflected by the stepped portion of the 7-line 4 formed of aluminum. The wafer is moved in the horizontal direction, and exposure is performed with the position where the intensity of the laser beam 80 detected by the photodiode 9 reaches its peak as the alignment position between the projected image of the mask and the wafer.
次に、第１図（ｂ）に示すように、フォトレジスト膜６
を現像し、フォトレジスト開孔部１０を設ける。この際
同時に新たな位置合せ用マークパターン１１を設ける。Next, as shown in FIG. 1(b), the photoresist film 6
is developed, and photoresist openings 10 are provided. At this time, a new alignment mark pattern 11 is provided at the same time.
このマーク１１を設ける位置としては今まで設置してき
た位置合せ用マーク４とは別の位置が望ましい。It is desirable that this mark 11 be provided at a different position from the alignment mark 4 that has been set up until now.
次に、第１図（Ｃ）に示すように、このフォトレジスト
膜６ｆ：マスクにしてポリイミド樹脂層５に第一層アル
ミニウム電極配線３に達する層間絶縁膜開孔部１２ｔ−
設けるが、その際同時に新しい位置合せ用マーク１３が
形成される。次いでフォトレジスト膜６を除去する。Next, as shown in FIG. 1C, this photoresist film 6f is used as a mask to form an opening 12t in the interlayer insulating film that reaches the first layer aluminum electrode wiring 3 in the polyimide resin layer 5.
At the same time, new alignment marks 13 are formed. Next, photoresist film 6 is removed.
次に、第１図（ｄ）に示すように、シリコン基板全面に
スパッタリング法によシアルミニウム膜１４を被着し、
さらにフォトレジスト膜ｔｓｔ被着する。そして、新た
にポリイミド樹脂Ｍ５に設けた位置合せ用マーク部１３
にレーザ光１６１に照射し位置合せを行うが、この時ア
ルミニウム膜１４０表面にもポリイミド樹脂の段部に対
応した同様の段部が有り、この段部によりレーザー光１
６は乱反射され、そのうち４５′の角度で乱反射される
レーザー光１７だけをフォトダイオード９で検出し、強
度がピークとなる位置を、マスクの投影像とウェーハの
目合せ位置として露光を行う。Next, as shown in FIG. 1(d), a sialuminum film 14 is deposited on the entire surface of the silicon substrate by sputtering,
Furthermore, a photoresist film tst is deposited. Then, the alignment mark part 13 newly provided on the polyimide resin M5
At this time, the surface of the aluminum film 140 also has a similar step corresponding to the step of the polyimide resin, and this step allows the laser beam 161 to be applied to the surface of the aluminum film 140.
The laser beam 6 is diffusely reflected, and only the laser beam 17 diffusely reflected at an angle of 45' is detected by the photodiode 9, and exposure is performed using the position where the intensity peaks as the alignment position between the projected image of the mask and the wafer.
次に、第１図（ｅ）に示すように、現像後フォトレジス
ト＆１５ｔ−マスクとし、アルミニウム膜１５のエツチ
ングを行い、フォトレジスト膜１５を除去し、第二ｌ−
アルミニウム電極配線１８を形成することを９よシ、ア
ルミニウム二層配！ｓｔ−完成する。Next, as shown in FIG. 1(e), the aluminum film 15 is etched using a photoresist and a 15t-mask after development, and the photoresist film 15 is removed.
In order to form the aluminum electrode wiring 18, two layers of aluminum are used! st- complete.
以上説明したように、本発明は半導体素子の多層配線形
成において、目合せ露光全縮小投影露光法を用いて行な
う場合、層間絶縁膜に下層の金属配線に達する開孔部を
選択的に設ける工程において同時に位置合せ用マーク金
形成することによりたとえ層間絶＃ｌ膜を完全に平坦化
しても上層の金属配線金′Ｎ度良く形成することができ
るという効果がある。As explained above, the present invention provides a process for selectively forming an opening in an interlayer insulating film that reaches the underlying metal wiring when the alignment exposure full reduction projection exposure method is used to form multilayer wiring for semiconductor devices. By forming the alignment marks at the same time, even if the interlayer #l film is completely flattened, the upper layer metal wiring can be formed with good accuracy.
また、層間絶縁膜は完全に平坦化された場合に限らず、
段部をなめらかにし、ン一り部が不明瞭となる場合は、
位置合せにおいて誤動作の原因となるが、この発明を使
用することにょシ誤動作を無くすことができる。In addition, the interlayer insulating film is not limited to being completely flattened.
Smooth the stepped part, and if the uneven part becomes unclear,
This causes malfunctions during alignment, but malfunctions can be eliminated by using the present invention.
さらに、上層の電極配線形成を下層の！他配線に遅する
開孔部に対して位置合せをするため、この開孔部と上層
１を極配線との余裕を小さくすることができ微細配線の
形成が容易になるという利点も有する。Furthermore, the upper layer electrode wiring is formed on the lower layer! Since alignment is performed with respect to the opening that lags behind other wiring, the margin between the opening and the upper layer 1 and the pole wiring can be reduced, which also has the advantage of facilitating the formation of fine wiring.
第１図（ａ）〜（ｅ）は本発明の一実施例を説明するた
めに工程順に示した断面図、第２図＜ａ＞〜（ｄ）は従
来の多層配縁の形成方法を説明するために工程順にボし
た断面図である。
１．２１・・・・・・シリコン基板、２．２２・・・・
・・シリコン酸化膜、３．２３・・・・・・第一層アル
ミニウム戒悼配純、４．２４・・・・・・位置合せ用ン
一り、５゜２５・・・・・・ポリイミド樹脂、６． １
５． ２６． ３２・・・・・・フォトレジストＭ、７
，１６．２７・・・・・・位置合せ用レーザー光、８，
１７．２８・・・・・・４５°の角度に反射されたレー
ザー光、９．２９・・・・・・フォトダイオード、１０
．１１・・・・・・フォトレジスト開孔部、１２．３０
・・・・・・層間絶縁膜開孔部、１３・・・・・・層間
絶縁膜位置合せ用マーク、１４．３１・・・・・・・・
・・・・アルミニウム膜、１８・山・・第二層アルミニ
ウム電極配線。
代理人 弁理士 内 原 晋 ゛１茅１訂
）２回Figures 1 (a) to (e) are cross-sectional views shown in order of steps to explain an embodiment of the present invention, and Figures 2 (a) to (d) illustrate a conventional method for forming a multilayer interconnection. FIG. 1.21...Silicon substrate, 2.22...
・・Silicon oxide film, 3.23・・・First layer aluminum layer, 4.24・・・Positioning alignment, 5°25・・・Polyimide resin, 6. 1
5. 26. 32...Photoresist M, 7
,16.27... Laser light for positioning, 8,
17.28...Laser light reflected at an angle of 45°, 9.29...Photodiode, 10
．． 11...Photoresist opening, 12.30
...Interlayer insulating film opening, 13...Interlayer insulating film alignment mark, 14.31...
...Aluminum film, 18. Mountain...Second layer aluminum electrode wiring. Agent: Patent Attorney Susumu Uchihara ゛1 Kaya 1st edition) 2 times
Claims (2)
回路の多層配線の形成を縮小投影露光法により目合せ露
光を行なう際、絶縁膜に選択的に開孔部を設ける工程に
おいて、同時に新たな位置合せ用マークを形成し、該位
置合せ用マークを使用し前記絶縁膜上に形成された次の
層の電極配線の目合せ露光を行うことを特徴とする多層
配線の形成方法。(1) When performing alignment exposure using the reduction projection exposure method to form multilayer interconnects in a semiconductor integrated circuit that is formed by providing an insulating film between interconnect layers, at the same time in the process of selectively forming openings in the insulating film, A method for forming a multilayer wiring, comprising forming a new alignment mark, and using the alignment mark to align and expose the next layer of electrode wiring formed on the insulating film.
囲第（１）項記載の多層配線の形成方法。(2) The method for forming a multilayer wiring according to claim (1), wherein the insulating film is a planarized insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60089315A JPS61248427A (en) | 1985-04-25 | 1985-04-25 | Formation of multilayer interconnection |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60089315A JPS61248427A (en) | 1985-04-25 | 1985-04-25 | Formation of multilayer interconnection |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61248427A true JPS61248427A (en) | 1986-11-05 |
| JPH0513372B2 JPH0513372B2 (en) | 1993-02-22 |
Family
ID=13967231
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60089315A Granted JPS61248427A (en) | 1985-04-25 | 1985-04-25 | Formation of multilayer interconnection |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61248427A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63237520A (en) * | 1987-03-26 | 1988-10-04 | Nec Corp | Manufacture of semiconductor element |
| JPS63307736A (en) * | 1987-06-10 | 1988-12-15 | Hitachi Ltd | Method of processing by using ion beam |
| JPH01103834A (en) * | 1987-10-16 | 1989-04-20 | Sanyo Electric Co Ltd | Manufacture of semiconductor device |
| JPH03174728A (en) * | 1989-12-04 | 1991-07-29 | Matsushita Electron Corp | Manufacture of semiconductor device |
| US7355675B2 (en) | 2004-12-29 | 2008-04-08 | Asml Netherlands B.V. | Method for measuring information about a substrate, and a substrate for use in a lithographic apparatus |
| JP2013102161A (en) * | 2011-11-07 | 2013-05-23 | Voltafield Technology Corp | Method for manufacturing magnetoresistance component structure |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6035515A (en) * | 1983-08-08 | 1985-02-23 | Hitachi Micro Comput Eng Ltd | Manufacture of semiconductor device |
-
1985
- 1985-04-25 JP JP60089315A patent/JPS61248427A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6035515A (en) * | 1983-08-08 | 1985-02-23 | Hitachi Micro Comput Eng Ltd | Manufacture of semiconductor device |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63237520A (en) * | 1987-03-26 | 1988-10-04 | Nec Corp | Manufacture of semiconductor element |
| JPS63307736A (en) * | 1987-06-10 | 1988-12-15 | Hitachi Ltd | Method of processing by using ion beam |
| JPH01103834A (en) * | 1987-10-16 | 1989-04-20 | Sanyo Electric Co Ltd | Manufacture of semiconductor device |
| JPH0553296B2 (en) * | 1987-10-16 | 1993-08-09 | Sanyo Electric Co | |
| JPH03174728A (en) * | 1989-12-04 | 1991-07-29 | Matsushita Electron Corp | Manufacture of semiconductor device |
| US7355675B2 (en) | 2004-12-29 | 2008-04-08 | Asml Netherlands B.V. | Method for measuring information about a substrate, and a substrate for use in a lithographic apparatus |
| JP2013102161A (en) * | 2011-11-07 | 2013-05-23 | Voltafield Technology Corp | Method for manufacturing magnetoresistance component structure |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0513372B2 (en) | 1993-02-22 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |