JPS61242406A - Agc system - Google Patents
Agc systemInfo
- Publication number
- JPS61242406A JPS61242406A JP8361585A JP8361585A JPS61242406A JP S61242406 A JPS61242406 A JP S61242406A JP 8361585 A JP8361585 A JP 8361585A JP 8361585 A JP8361585 A JP 8361585A JP S61242406 A JPS61242406 A JP S61242406A
- Authority
- JP
- Japan
- Prior art keywords
- output
- rom
- circuit
- adder
- agc
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- Control Of Amplification And Gain Control (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は受信入力変化にかかわらず出力を一定にするＡ
ＧＣ回路の改良に関する。[Detailed Description of the Invention] [Industrial Field of Application] The present invention provides an A
Concerning improvements in GC circuits.
一般に、中継器に於ては受信電界が時間的に変化する事
が多いので、受信電界の変化にかかわらず出力を一定と
するためのＡＧＣ方式が用いられる。第６図は従来の中
継器における送受信装置内のＡＧＣ回路を示す。１は可
変減衰器、２は増幅器、３は検波器、４は低域ろ波器（
以下。Generally, in a repeater, the received electric field often changes over time, so an AGC method is used to keep the output constant regardless of changes in the received electric field. FIG. 6 shows an AGC circuit within a transmitting/receiving device in a conventional repeater. 1 is a variable attenuator, 2 is an amplifier, 3 is a detector, 4 is a low-pass filter (
below.
ＬＰＦと呼ぶ）、５は基準電圧発生器、６はＡＧＯ増幅
器である。5 is a reference voltage generator, and 6 is an AGO amplifier.
以下、 ＡＧＣ動作を第７図の等何回路を用いて説明す
る。第７図に於て、第６図の可変減衰器１は乗算器７．
第６図のＡＧＣ増幅器６は比較器８と増幅器９とから構
成されるものとみなすことができる。ここで、出力ｅ０
は検波された後ＬＰＦ ｉ介して比較器８に入力され、
基準電圧Ｅと比較される。更に、その差電圧は増幅器９
で増幅され、入力にフィードバックされる。この時の関
係式は次式で与えられる。The AGC operation will be explained below using the circuit shown in FIG. In FIG. 7, the variable attenuator 1 of FIG. 6 is replaced by a multiplier 7.
The AGC amplifier 6 in FIG. 6 can be considered to be composed of a comparator 8 and an amplifier 9. Here, the output e0
is detected and then input to the comparator 8 via the LPF i,
It is compared with a reference voltage E. Furthermore, the differential voltage is applied to the amplifier 9
is amplified and fed back to the input. The relational expression at this time is given by the following expression.
Ｇ−ＨＨ
ｅｌＱ ＝ □ Ｅ＋ □ ｅｉ（１）Ｇ
＋ＨＧ＋Ｈ
ここで、ＧＵＡＧＣ増幅器９の利得。G-HH elQ = □ E+ □ ei(1)G
+HG+H Here, the gain of the GUAGC amplifier 9.
Ｈは増幅器２の利得である。H is the gain of amplifier 2.
従って入力ｅｉの変化にかかわらず出力ｅ。を一定とす
る為には。Therefore, the output e regardless of the change in the input ei. In order to keep it constant.
Ｇ＞）ｌとすればよい。この時 ｅ（１＊Ｅとなシ、出
力ｅ。一定となる。G>)l. At this time, e(1*E), the output e becomes constant.
第８図は入力Ｊ−出力ｅ。特性を示す。FIG. 8 shows input J-output e. Show characteristics.
従来のＡＧＣ増幅器では、入力レベルに対する出力レベ
ル特性は可変抵抗器を構成するピンダイオード等の制御
電圧によって決定される。ところが、この制御電圧を得
るための検波電圧特性は非直線であるため、■任意の利
得設定が難しい、■温度変動等によシ影響を受は易い。In a conventional AGC amplifier, the output level characteristics relative to the input level are determined by a control voltage of a pin diode or the like that constitutes a variable resistor. However, since the detection voltage characteristic for obtaining this control voltage is non-linear, (1) it is difficult to set an arbitrary gain, and (2) it is easily affected by temperature fluctuations.
■外部雑音に弱い２等の欠点があった。■It had the disadvantage of being weak against external noise.
更に、上記式（１）のＡＧＣ増幅器の利得は限界がある
ため、ｅ（１’ｙＥとなり、出力は完全に一定とはなら
ず、入力の変化に対応してわずかであるが変動するとい
う問題があった。Furthermore, since the gain of the AGC amplifier in equation (1) above has a limit, it becomes e(1'yE, which causes the problem that the output is not completely constant and varies slightly in response to changes in the input. was there.
本発明は上記欠点を除去しようとするもので。The present invention seeks to eliminate the above drawbacks.
利得設定が安定であり、かつ任意に利得を設定出来、温
度変動や外部雑音に強いという特長を有するＡＧＣ方式
を提供する事を目的とする。It is an object of the present invention to provide an AGC method that has stable gain settings, can set the gain arbitrarily, and is resistant to temperature fluctuations and external noise.
本発明は、受信信号を検波する回路と、該検波出力をサ
ンプルホールドする回路と、該サンプルホールド回路の
出力ｔ Ａ／Ｄ変換する手段と。The present invention includes a circuit that detects a received signal, a circuit that samples and holds the detection output, and means for A/D converting the output t of the sample and hold circuit.
＃Ａ／Ｄ変換出力をあらかじめ定められたＡＧＣ時定数
に相当する一定期間平均化する手段と、該平均化された
出力とあらかじめＲＯＭに蓄えられた記憶内容とを比較
演算する手段とを備え、該演算出力によって受信回路に
挿入された可変減衰益金制御する事により、受信入力変
動にかかわらず出力を一定に保つＡＧＣ方式であって、
前記検波回路の特性に応じた制御内容を前記ＲＯＭに書
込んだ事を特徴とする。#Equipped with means for averaging the A/D conversion output for a certain period corresponding to a predetermined AGC time constant, and means for comparing and calculating the averaged output with the memory content stored in the ROM in advance, An AGC method that maintains the output constant regardless of fluctuations in the reception input by controlling a variable attenuation gain inserted in the reception circuit using the calculation output,
The present invention is characterized in that control contents corresponding to the characteristics of the detection circuit are written in the ROM.
第１図は本発明による送受信装置内のＡＧＣ回路を示し
、ディジタル的に構成されている。FIG. 1 shows an AGC circuit in a transmitter/receiver according to the present invention, which is constructed digitally.
図において、１０はサンプルホールド回路であり。In the figure, 10 is a sample and hold circuit.
送信、受信同期用のクロックによりこのりａツクに同期
してレベルを保持する機能を有する。It has a function of holding the level in synchronization with the clock using the clock for synchronizing transmission and reception.
１１はＡＤＤ変換器である。１２はＡ／Ｄ変換器１１の
出力を加算する加算器で、ｌサンプル（ｉは正の整数）
の加算を行って除算器１３により除算を行う。この機能
はｌサンプルの平均をとっている事と等価であり、ＡＧ
Ｃループの時定数を決定ｔ６゜（”ｊ； ｆ（ｉ） ）
次ＬＩＣ，ＲＯＭ１４にオイｆｅｏの平均出力に相
当する検波電圧と比較を行う。11 is an ADD converter. 12 is an adder that adds the output of the A/D converter 11, and has l samples (i is a positive integer).
Then, the divider 13 performs division. This function is equivalent to taking the average of l samples, and AG
Determine the time constant of C loop t6゜(”j; f(i))
Next, a comparison is made with the detected voltage in the LIC and ROM 14 corresponding to the average output of the oi-feo.
検波器３の検波電圧特性を第２図に示す。第２図に示す
如く、出力ｅ０がＯｄＢｍの時、検波電圧１ｖとし、＋
１ｄＢｍの時１．ＩＶ、 −１ｄＢｍの時。FIG. 2 shows the detected voltage characteristics of the detector 3. As shown in Figure 2, when the output e0 is OdBm, the detection voltage is 1v, +
At 1dBm 1. IV, at -1dBm.
０．９ｖのようになる特性とする。The characteristic is assumed to be 0.9v.
一方、ＲＯＭ１４には第３図に示すように、 ＲＯＭ人
力１ｖの時０．入力１．ＩＶ１７）時＋１ ｄＢ、 入
力０．９Ｖの時−１ｄＢ・・・という結果が得られるよ
うに入力に対応して読出される各位が格納されている。On the other hand, as shown in Fig. 3, the ROM 14 has a value of 0.0 when the ROM human power is 1V. Input 1. The various positions to be read out corresponding to the inputs are stored so that results such as +1 dB at IV17), -1 dB at input 0.9V, etc. are obtained.
加算器１５はＲＯＭ出力と一定電圧入力ＶＧとの加算を
行い、との加算出力で１ｄＢステップｍビットのディジ
タル減衰器１７を制御する。従って。The adder 15 adds the ROM output and the constant voltage input VG, and controls the m-bit digital attenuator 17 in 1 dB steps with the added output. Therefore.
入力がＪでＲＯＭ人力１ｖの時、加算器１５の出力はＶ
Ｃ、入力がｅｉ＋１ｄＢでＲＯＭ入力＋１．１ｖの時Ｖ
Ｃ＋ １ 、入力がｅｉ−１ｄＢでＲＯＭ入力０．９ｖ
の時ＶＣ−１ｄ Ｂとなシ、出力ｅ。は常に一定に保た
れる。但し、出力ｅ。＝１〜１．ＩＶ、 ０．９〜１ｖ
・・・の区間は可変減衰器１７は一定の為、出力ｅ。は
入力ｅｉに比例して変化する。可変減衰器１７のダイナ
ミックレンジ金ＬｄＢとした時、入力ｅｉが減少し可変
減衰器１７が全てＯｄＢとなれば、入力ｅ・に比例して
出力ｅ０は減少し、逆に入力８１が増加して可変減衰器
１７がＬｄＢとなれば、可変減衰器１７の増加はないの
で入力ｅｉに比例して出力ｅ０は増加する。このように
して、 ＡＧＣ特性は第４図に示す如く、ダイナミック
レンジＬｄＢの区間で＋１ｄＢの範囲内で一定となる。When the input is J and the ROM power is 1V, the output of the adder 15 is V
C, V when the input is ei + 1 dB and ROM input + 1.1 V
C+ 1, input is ei-1dB and ROM input 0.9V
When VC-1d B and output e. is always kept constant. However, the output e. =1~1. IV, 0.9~1v
Since the variable attenuator 17 is constant in the section..., the output is e. changes in proportion to the input ei. When the dynamic range of the variable attenuator 17 is set to gold LdB, if the input ei decreases and the variable attenuator 17 becomes all OdB, the output e0 decreases in proportion to the input e, and conversely the input 81 increases. If the variable attenuator 17 becomes LdB, there is no increase in the variable attenuator 17, so the output e0 increases in proportion to the input ei. In this way, the AGC characteristic becomes constant within a range of +1 dB in the dynamic range L dB section, as shown in FIG.
なお１６はマー−アル／オートの切替スイッチであり、
必要に応じてＡＧＣループを切離し、マニエアルで任意
に利得を設定出来る様にしている。Note that 16 is a mar-al/auto selector switch,
The AGC loop is disconnected if necessary, and the gain can be set manually.
この様な回路になっている為１本ディジタルＡＧＣ方式
は外来雑音や温度変動等による影響を受は難く、利得設
定が容易である等の特長を有している。Because of this circuit structure, the single-wire digital AGC system is less susceptible to external noise, temperature fluctuations, etc., and has the advantage of being easy to set gain.
なお、第１図に於て加算器１５に加える設定値ＶＧ ｆ
変える事によシ、動作点を容易に変え得ることは明らか
である。また、ＲＯＭ１４に書込む内容を変える事によ
り、一定出力の設定点を変える事も出来る。即ち、第５
図に示す如く。In addition, in FIG. 1, the set value VG f added to the adder 15
It is clear that the operating point can be easily changed by changing. Furthermore, by changing the contents written in the ROM 14, the set point of the constant output can be changed. That is, the fifth
As shown in the figure.
ＲＯＭ１４の記憶内容を第２図の検波特性データをもと
にアドレス０に対し、出力ＯｄＢｍ一定とする内容とし
、アドレス１に対し出力＋１０ｄＢｍ一定とする書込内
容とする事により、アドレスを指定する事で任意に出力
を設定する事が出来る。Specify the address by setting the stored contents of the ROM 14 as the content that makes the output OdBm constant for address 0 and the output +10 dBm constant for address 1 based on the detection characteristic data in Figure 2. You can set the output as you like.
以上説明してきたように１本発明によれば外来雑音や温
度変動等による影響を受けに＜＜。As explained above, according to the present invention, there is no influence from external noise, temperature fluctuations, etc.
利得設定が容易なＡＧＣ方式が提供される。 しかも、
ＡＧＣ回路を全てディジタル回路で構成している為、
ＩＣ等を用いて小型、軽量化が可能であるという効
果をも有する。An AGC method with easy gain setting is provided. Moreover,
Since the AGC circuit is entirely composed of digital circuits,
It also has the effect of being able to be made smaller and lighter by using ICs and the like.
第１図は本発明によるＡＧＣ回路の一実施例を示し、第
２図は第１図の検波器の検波特性を示し、第３図は第１
図のＲＯＭの記憶内容の一例を示し、第４図は第１図の
実施例によるＡＧＣ特性を示し、第５図は本発明の変形
例として設定出力を変える場合のＲＯＭの内容を示し、
第６図は従来のＡＧＣ方式を示す図、第７図はその等価
回路図、第８図はその人力−出力特性図。
１は可変減衰器、２は増幅器、３は検波器。
４は低域ろ波器、５は基準電圧発生器、 ６はＡＧＣ増
幅器、７，８は加算器、９は増幅器、 １０はサンプル
ホールド回路、 １１はＡ／Ｄ変換器、１２は加算器、
１３は除算器、１４はＲＯＭ、 １５は加算器。
１６はマニュアル／オート切替スイッチ、１７は可変減
衰器。
第２図
アドレス メ丑す内容
第３図
第５図
第８図 いヵ′ＬFIG. 1 shows an embodiment of the AGC circuit according to the present invention, FIG. 2 shows the detection characteristics of the detector shown in FIG. 1, and FIG. 3 shows the detection characteristics of the detector shown in FIG.
An example of the storage contents of the ROM shown in the figure is shown, FIG. 4 shows the AGC characteristics according to the embodiment of FIG. 1, and FIG. 5 shows the contents of the ROM when changing the setting output as a modification of the present invention.
FIG. 6 is a diagram showing the conventional AGC system, FIG. 7 is its equivalent circuit diagram, and FIG. 8 is its human power-output characteristic diagram. 1 is a variable attenuator, 2 is an amplifier, and 3 is a detector. 4 is a low-pass filter, 5 is a reference voltage generator, 6 is an AGC amplifier, 7 and 8 are adders, 9 is an amplifier, 10 is a sample and hold circuit, 11 is an A/D converter, 12 is an adder,
13 is a divider, 14 is a ROM, and 15 is an adder. 16 is a manual/auto selector switch, and 17 is a variable attenuator. Figure 2 Address Contents Figure 3 Figure 5 Figure 8
Claims (1)
ホールドする回路と、該サンプルホールド回路の出力を
Ａ／Ｄ変換する手段と、該Ａ／Ｄ変換出力をあらかじめ
定められたＡＧＣ時定数に相当する一定期間平均化する
手段と、該平均化された出力とあらかじめＲＯＭに蓄え
られた記憶内容とを比較演算する手段とを備え、該演算
出力によつて受信回路に挿入された可変減衰器を制御す
る事により、受信入力変動にかかわらず出力を一定に保
つＡＧＣ方式であつて、前記検波回路の特性に応じた制
御内容を前記ＲＯＭに書込んだ事を特徴とするＡＧＣ方
式。1. A circuit for detecting a received signal, a circuit for sampling and holding the detection output, a means for A/D converting the output of the sample and holding circuit, and a means for converting the A/D conversion output into a predetermined AGC time constant. A variable attenuator is provided with means for averaging over a corresponding fixed period, and means for performing a comparison operation between the averaged output and memory contents stored in a ROM in advance, and is inserted into a receiving circuit according to the operation output. An AGC method that maintains an output constant regardless of fluctuations in received input by controlling the detection circuit, the AGC method being characterized in that control contents according to characteristics of the detection circuit are written in the ROM.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8361585A JPS61242406A (en) | 1985-04-20 | 1985-04-20 | Agc system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8361585A JPS61242406A (en) | 1985-04-20 | 1985-04-20 | Agc system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61242406A true JPS61242406A (en) | 1986-10-28 |
Family
ID=13807390
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8361585A Pending JPS61242406A (en) | 1985-04-20 | 1985-04-20 | Agc system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61242406A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0638998A1 (en) * | 1993-08-11 | 1995-02-15 | Plessey Semiconductors Limited | Fast-acting automatic gain control arrangement |
| EP0708527A1 (en) * | 1994-10-21 | 1996-04-24 | Nec Corporation | Method and device for controlling output power of a power amplifier |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59123303A (en) * | 1982-12-29 | 1984-07-17 | Fujitsu Ltd | Agc control system in receiver for receiving burst wave |
-
1985
- 1985-04-20 JP JP8361585A patent/JPS61242406A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59123303A (en) * | 1982-12-29 | 1984-07-17 | Fujitsu Ltd | Agc control system in receiver for receiving burst wave |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0638998A1 (en) * | 1993-08-11 | 1995-02-15 | Plessey Semiconductors Limited | Fast-acting automatic gain control arrangement |
| EP0708527A1 (en) * | 1994-10-21 | 1996-04-24 | Nec Corporation | Method and device for controlling output power of a power amplifier |
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