JPS612356A - Cmos type semiconductor device - Google Patents
Cmos type semiconductor deviceInfo
- Publication number
- JPS612356A JPS612356A JP59122278A JP12227884A JPS612356A JP S612356 A JPS612356 A JP S612356A JP 59122278 A JP59122278 A JP 59122278A JP 12227884 A JP12227884 A JP 12227884A JP S612356 A JPS612356 A JP S612356A
- Authority
- JP
- Japan
- Prior art keywords
- well region
- type
- potential
- epitaxial layer
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 230000012010 growth Effects 0.000 claims abstract description 9
- 230000010354 integration Effects 0.000 abstract description 3
- 230000001052 transient effect Effects 0.000 abstract description 3
- 239000012535 impurity Substances 0.000 description 23
- 239000010410 layer Substances 0.000 description 20
- 239000002184 metal Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 241000134884 Ericales Species 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000010261 cell growth Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- KSCFJBIXMNOVSH-UHFFFAOYSA-N dyphylline Chemical compound O=C1N(C)C(=O)N(C)C2=C1N(CC(O)CO)C=N2 KSCFJBIXMNOVSH-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0925—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising an N-well only in the substrate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は、CMOS型半導体装置に関するもので、特
にエピタキシャル成長基板を用いた場合のウェル領域の
形成に係わる。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a CMOS type semiconductor device, and particularly to the formation of a well region when an epitaxial growth substrate is used.
従来、CMOS型半導体装置、たとえば第3−夕は、第
4図に示すように構成されている。Conventionally, a CMOS type semiconductor device, for example, a third type semiconductor device is configured as shown in FIG.
第4図において、11はr型の半導体基板で、この半導
体基板l1の一方の表面上にはP一型のエピタキシャル
層l2が形成される。上記エピタキシャル層l2内には
N型のウェル領域13が形成され、このウェル領域13
にはPチャネル型MOSFBTQpのソース、ドレイン
領域としてのP 型不純物領域14,,14。In FIG. 4, reference numeral 11 denotes an r-type semiconductor substrate, and a P-type epitaxial layer l2 is formed on one surface of this semiconductor substrate l1. An N-type well region 13 is formed in the epitaxial layer l2, and this well region 13
P-type impurity regions 14, 14 serve as source and drain regions of the P-channel MOSFBTQp.
が所定間隔に離間して形成される。上記不純物領域14
,、l4,間のウェル領域l3上には、ダート酸化膜z
5を介してダート電極16が形成される。また、上記ウ
ェル領域13には,上記不純物領域14,に接触した状
態でN 型の不純物領域17が形成される。この不純物
領域17は,上記ウェル領域13に電源電圧Vccを印
加するためのコンタクト用で、上記不純物領域(ソース
領域)14,とともに金属配線層1B,によって電源電
圧Vccが印加される電源端子19に接続される。are formed at predetermined intervals. The impurity region 14
A dirt oxide film z is formed on the well region l3 between ,, l4,
A dart electrode 16 is formed through the electrode 5 . Further, an N type impurity region 17 is formed in the well region 13 in contact with the impurity region 14 . This impurity region 17 is for a contact for applying the power supply voltage Vcc to the well region 13, and is connected to the power supply terminal 19 to which the power supply voltage Vcc is applied by the impurity region (source region) 14 and the metal wiring layer 1B. Connected.
一方、上記エピタキシャル層I2には、NチャネルW
M O S F E T Q nのドレイン,ソース領
域としてのN 型不純物領域20,,20。On the other hand, the epitaxial layer I2 includes an N-channel W
N type impurity regions 20, 20 as drain and source regions of MOSFET Qn.
が所定間隔に離間して形成される。また、このエピタキ
シャル層12には、上記不純物領域20、に接触した状
態でP 型の不純物領域21が形成される。この不純物
領域21は上記エピタキシャル層22(基板)に接地電
位Vssを印加するためのコンタクト用で、上記不純物
領域(ソース領域)2o、とともに金属配線層1B、に
よって接地電位Vssが印加される電源端子22に接続
される。上記不純物領域2o1゜20、間の上記エピタ
キシャル層Z2上には、ダート酸化膜23を介してダー
ト電極24が形成され、このデート電極24と前記デー
ト電極16とはそれぞれ、入力信号INが供給される入
力端子25に接続される。そして、前記不純物領域(ド
レイン領域)14!と不純物領域(ドレイン領域)、?
0. とか、金属配線ZS。are formed at predetermined intervals. Further, a P type impurity region 21 is formed in this epitaxial layer 12 in contact with the impurity region 20 described above. This impurity region 21 is for a contact for applying the ground potential Vss to the epitaxial layer 22 (substrate), and is a power supply terminal to which the ground potential Vss is applied by the impurity region (source region) 2o and the metal wiring layer 1B. 22. A dirt electrode 24 is formed on the epitaxial layer Z2 between the impurity regions 2o1°20 through a dirt oxide film 23, and the date electrode 24 and the date electrode 16 are each supplied with an input signal IN. The input terminal 25 is connected to the input terminal 25. And the impurity region (drain region) 14! and impurity region (drain region),?
0. Or metal wiring ZS.
ニヨっテ出力信号OUTを得る出力端子26に接続され
る。なお、27は素子分離領域、28は層間絶縁膜であ
る。It is connected to the output terminal 26 from which the output signal OUT is obtained. Note that 27 is an element isolation region, and 28 is an interlayer insulating film.
上記P 型の半導体基板11は、比抵抗0.10・α、
不純物濃度4X10”α−3程度。The P type semiconductor substrate 11 has a specific resistance of 0.10·α,
Impurity concentration is about 4×10”α-3.
P−型のエピタキシャル層Z2は、比抵抗10Ω・α、
不純物濃度” ×10 ”3−”程度とする。The P-type epitaxial layer Z2 has a specific resistance of 10Ω·α,
The impurity concentration is approximately 3-1.times.10.
このように低抵抗の半導体基板11を使用することによ
り、基板電位なVssに確実に固定でき、ラッチアップ
耐量を向上できる。また、基板電位をチップ裏面からの
み取ることも可能であり、このように構成すればチップ
表面にP 型の不純物領域21を設けてVss電位を与
える必要がなく、チップ面積を縮小できる。By using the semiconductor substrate 11 with low resistance in this manner, it is possible to reliably fix the substrate potential to Vss and improve the latch-up resistance. It is also possible to take the substrate potential only from the back surface of the chip, and with this configuration, there is no need to provide a P type impurity region 21 on the chip surface to apply a Vss potential, and the chip area can be reduced.
上述したように、工ぎタキシセル成長基板を用いること
により、基板電位は確実に固定できるが、N型のウェル
領域13の電位は、N+型の不純物領域17を設けてV
cc電位を与える必要がある。このウェル領域Z3の不
純物濃度は、−トランノスタ特性の妾請上から通常は2
X10′6cm1程度に設定されるため、そのシート抵
抗はI KQ/g程度と高くなり、上記のような不純物
領域I7を複数カ所設けてウェル電位を取る必要がある
。As mentioned above, by using an engineered taxi cell growth substrate, the substrate potential can be reliably fixed, but the potential of the N-type well region 13 can be adjusted to V
It is necessary to apply a cc potential. The impurity concentration of this well region Z3 is usually 2 due to the trannosta characteristic.
Since it is set to about X10'6 cm1, its sheet resistance becomes as high as about IKQ/g, and it is necessary to provide a plurality of impurity regions I7 as described above to obtain a well potential.
特に、メモリセル等のアレイをウェル領域内に形成する
場合には、上記電位固定用の「型不純物領域(接合領域
)によりチップ面積が増大する欠点がある。In particular, when an array of memory cells or the like is formed in a well region, there is a drawback that the chip area increases due to the potential fixing "type impurity region (junction region)".
この発明は上記のような事情に鑑みてなされたもので、
その目的とするところは、電位固定用の接合領域が少な
くともウェル電位を安定に保持でき、ウェル電位の安定
化と高集積化とを図れるCMO,S型半導体装置を提供
することである。This invention was made in view of the above circumstances,
The object is to provide a CMO, S-type semiconductor device in which a potential fixing junction region can stably hold at least a well potential, and which can stabilize the well potential and achieve high integration.
すなわち、この発明においては、上記の目的を達成する
ために、エピタキシャル成長基板を用いたCMOS型半
導体装置において、上記エピタキシャル成長基板に形成
するウェル領域の深さを、エピタキシャル成長層より深
く形成したもので、これによってウェル領域と半導体基
板間に大きな接合容量を形成し、この接合容量によって
ウェル領域に発生する過渡的な電位変動を吸収させるよ
うにしたものである。That is, in order to achieve the above object, in the present invention, in a CMOS type semiconductor device using an epitaxial growth substrate, the depth of the well region formed in the epitaxial growth substrate is formed deeper than the epitaxial growth layer. A large junction capacitance is formed between the well region and the semiconductor substrate, and transient potential fluctuations occurring in the well region are absorbed by this junction capacitance.
以下、この発明の一実施例について図面を参照して説明
する。第1図において29はP 型の半導体基板で、こ
のP 型の半導体基板29上にはP−型のエピタキシャ
ル層3oが形成される。このエピタキシャル層30には
、へ型のウェル領域3zがこのエピタキシャル層3oよ
り深く形成される。そして、上記エビタキシャ層30内
およびウェル領域31内にそれぞれ種々の半導体装置が
形成される。An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, reference numeral 29 denotes a P type semiconductor substrate, and a P- type epitaxial layer 3o is formed on this P type semiconductor substrate 29. In this epitaxial layer 30, a square well region 3z is formed deeper than this epitaxial layer 3o. Various semiconductor devices are formed in the epitaxial layer 30 and the well region 31, respectively.
なお、各領域の不純物濃度はそれぞれ、半導体基板29
が4×1O17cIIL−3、エピタキシャル層30が
I X 10”Cm”−” 、ウェル領域3ノが2 X
10+6cIIL−3程度テアル。今、P−fJiエ
ヒ9キシャル層とN型ウェル領域との間の容量をCJ。Note that the impurity concentration of each region is different from that of the semiconductor substrate 29.
is 4×1O17cIIL-3, epitaxial layer 30 is I×10"Cm"-", well region 3 is 2X
Theal about 10+6cIIL-3. Now, the capacitance between the P-fJi 9x layer and the N-type well region is CJ.
とすると、この容量Cj、はP−型エピタキシャル層に
おける不純物濃度の平方根に比例する。一方P 型半導
体基板とN型ウェル領域間の容量なCjtとすると、こ
の容量Cj、はN型ウェル領域における不純物濃度の平
方根に比例する。従つて、第1図に示したようにエピタ
キシャル層よりも深くN型ウェル領域31を形成した場
合の容量Cj、は、次式に示すように、
となり、前記第4図に示したようにN型ウェル領域の深
さをP−型エピタキシャル層より浅く形成した場合の容
量に比べ、単位面積あたり約4.5倍に増大できる。こ
の容量によってウェル領域の電位の過渡的な変動を吸収
し、ウェル電位を安定に保持できる。Then, this capacitance Cj is proportional to the square root of the impurity concentration in the P-type epitaxial layer. On the other hand, assuming that the capacitance between the P-type semiconductor substrate and the N-type well region is Cjt, this capacitance Cj is proportional to the square root of the impurity concentration in the N-type well region. Therefore, when the N-type well region 31 is formed deeper than the epitaxial layer as shown in FIG. 1, the capacitance Cj is as shown in the following equation, and as shown in FIG. Compared to the case where the depth of the type well region is formed to be shallower than the P- type epitaxial layer, the capacitance can be increased approximately 4.5 times per unit area. This capacitance can absorb transient fluctuations in the potential of the well region and maintain the well potential stably.
第2図は、上記第1図の構成の・等価回路を示している
。図において、32..32.はN型ウェル領域31の
等価抵抗、331,332゜33、はN型ウェル領域3
1とP型の半導体基板29との接合容量、34はN型ウ
ェル領域3Iと内部ノードとの間の寄生容量である。図
示するようにウェル領域31と半導体基板29との間の
接合容量33□、33□、33sが大きいので、ウェル
抵抗32..32□が大きい(つまり電位固定用のN
接合領域が少ない)場合でも、内部ノードとの容量結合
による電位変動を小さくおさえることができる。従って
、チップ面積を縮小することも可能である。FIG. 2 shows an equivalent circuit of the configuration shown in FIG. 1 above. In the figure, 32. .. 32. is the equivalent resistance of the N-type well region 31, 331, 332°33 is the equivalent resistance of the N-type well region 3
1 is a junction capacitance between P-type semiconductor substrate 29, and 34 is a parasitic capacitance between N-type well region 3I and an internal node. As shown in the figure, since the junction capacitances 33□, 33□, 33s between the well region 31 and the semiconductor substrate 29 are large, the well resistance 32. .. 32□ is large (that is, N for potential fixing
Even if the number of junction regions is small, potential fluctuations due to capacitive coupling with internal nodes can be suppressed to a small level. Therefore, it is also possible to reduce the chip area.
また、電位固定用のN 接合領域の数を充分多く設けれ
ば、前記第2図に示したウェル領域31の等価抵抗32
□、322を無視でき、チップ全体としてはVccとV
ss端子間に大きな容量を形成することができる。この
容量は、半導体回路自身が発生する電流ピークを吸収す
るのに有効である。さらに、半導体基板がVss電位で
はなく、自己基板電位発生回路を内蔵している場合には
、基板電位の安定化が図れる。Furthermore, if a sufficiently large number of N junction regions for potential fixing is provided, the equivalent resistance 32 of the well region 31 shown in FIG.
□, 322 can be ignored, and as a whole chip, Vcc and V
A large capacitance can be formed between the ss terminals. This capacitance is effective in absorbing current peaks generated by the semiconductor circuit itself. Furthermore, if the semiconductor substrate has a built-in self-substrate potential generation circuit instead of the Vss potential, the substrate potential can be stabilized.
以上説明したよう(二この発明によれば、電位固定用の
接合領域が少なくともウェル電位を安定に保持でき、ウ
ェル電位の安定化と高集積化とを図れるCMOS型半導
体装置が得られる。As described above (2) According to the present invention, a CMOS type semiconductor device is obtained in which the potential fixing junction region can stably hold at least the well potential, and the well potential can be stabilized and the integration can be increased.
第1因はこの発明の一実施例に係るCMOS型半導体装
置を説明するための断面構成図、第2図は上記第1図の
等価回路、第3図および第4図はそれぞれ従来のCMO
8型半導体装置を説明するための図である。
29・・・半導体基板、30・・・エピタキシャル層、
3I・・・ウェル領域。
出願人代理人 弁理士 鈴 江 武 豚箱1図
第2図
ssThe first factor is a cross-sectional configuration diagram for explaining a CMOS type semiconductor device according to an embodiment of the present invention, FIG. 2 is an equivalent circuit of the above-mentioned FIG. 1, and FIGS.
FIG. 3 is a diagram for explaining an 8-type semiconductor device. 29... Semiconductor substrate, 30... Epitaxial layer,
3I...well area. Applicant's representative Patent attorney Takeshi Suzue Pig box Figure 1 Figure 2 ss
Claims (1)
において、上記エピタキシャル成長基板に形成するウェ
ル領域の深さを、エピタキシャル成長層より深く形成し
たことを特徴とするCMOS型半導体装置。A CMOS type semiconductor device using an epitaxial growth substrate, characterized in that a well region formed in the epitaxial growth substrate is formed deeper than an epitaxial growth layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59122278A JPS612356A (en) | 1984-06-14 | 1984-06-14 | Cmos type semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59122278A JPS612356A (en) | 1984-06-14 | 1984-06-14 | Cmos type semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS612356A true JPS612356A (en) | 1986-01-08 |
Family
ID=14832001
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59122278A Pending JPS612356A (en) | 1984-06-14 | 1984-06-14 | Cmos type semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS612356A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0696062A3 (en) * | 1994-07-28 | 1996-12-11 | Hitachi Ltd | CMOS semiconductor device and manufacturing method thereof |
-
1984
- 1984-06-14 JP JP59122278A patent/JPS612356A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0696062A3 (en) * | 1994-07-28 | 1996-12-11 | Hitachi Ltd | CMOS semiconductor device and manufacturing method thereof |
US6368905B1 (en) | 1994-07-28 | 2002-04-09 | Hitachi, Ltd. | Process for manufacturing a semiconductor wafer, a semiconductor wafer, process for manufacturing a semiconductor integrated circuit device, and semiconductor integrated circuit device |
US6630375B2 (en) | 1994-07-28 | 2003-10-07 | Hitachi, Ltd. | Process for manufacturing a semiconductor wafer, a semiconductor wafer, process for manufacturing a semiconductor integrated circuit device, and semiconductor integrated circuit device |
US6806130B2 (en) | 1994-07-28 | 2004-10-19 | Renesas Technology Corp. | Process for manufacturing a semiconductor wafer, a semiconductor wafer, process for manufacturing a semiconductor integrated circuit device, and semiconductor integrated circuit device |
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