JPS61231768A - Mis type field effect transistor - Google Patents
Mis type field effect transistorInfo
- Publication number
- JPS61231768A JPS61231768A JP60073902A JP7390285A JPS61231768A JP S61231768 A JPS61231768 A JP S61231768A JP 60073902 A JP60073902 A JP 60073902A JP 7390285 A JP7390285 A JP 7390285A JP S61231768 A JPS61231768 A JP S61231768A
- Authority
- JP
- Japan
- Prior art keywords
- drain
- type
- oxide film
- layer
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims description 8
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 239000004065 semiconductor Substances 0.000 claims abstract description 6
- 239000012535 impurity Substances 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 abstract description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052710 silicon Inorganic materials 0.000 abstract description 6
- 239000010703 silicon Substances 0.000 abstract description 6
- 230000006866 deterioration Effects 0.000 abstract description 2
- 238000005468 ion implantation Methods 0.000 abstract description 2
- 230000015556 catabolic process Effects 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はＭＩＳ型電界効果トランジスタに関し、社Ｖ恵
ト＝錫浩冬友寸入ＭＴＱ柑ｊ宙界鮪里トラソジスタＶｃ
関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an MIS field effect transistor,
related.
ＭＩＳ型電界効果トランジスタ（以後ＭＩＳＦＥＴと記
す）の最も一般的なもの［ＭＯ８型電界効果トランジス
タ（以後ＭＯ８ＦＥＴと記す）であるのでＭＯ８ＦＥＴ
Ｋ）いて説明する。一般ＫＭ０８ＦＥＴのドレイン耐圧
は、ドレイン−ソース間およびドレイン−ゲート間の電
界集中によるドレイン近傍のアバランシェ破壊で決まっ
ている。そこで従来の方法では、ゲートをドレイン領域
にのばしたフィールドプレート法、あるいはゲート電極
で反転しきれない領域を電極で反転させ長いドリフトチ
ャネル領域を形成して電圧効果をはかるスタックド・ゲ
ート法によ、り７ＭＯ８ＦＥＴの耐圧を向上している。The most common MIS type field effect transistor (hereinafter referred to as MISFET) [MO8 type field effect transistor (hereinafter referred to as MO8FET), so MO8FET
K) Explain. The drain breakdown voltage of a general KM08FET is determined by avalanche breakdown near the drain due to electric field concentration between the drain and the source and between the drain and the gate. Therefore, conventional methods use the field plate method, in which the gate extends into the drain region, or the stacked gate method, in which the region that cannot be inverted by the gate electrode is inverted by the electrode, forming a long drift channel region to measure the voltage effect. , the withstand voltage of the 7MO8FET has been improved.
しかしながら、フィールドプレート法では、ドリフト領
域を長くとる必要がありこのため、ＭＯＳＦＥＴの万ン
抵抗Ｒｅｖは大きくなシ、相互コンダクタンスｇ１は小
さいという欠点がある。スタックド・ゲート法でも、ド
リフチャネル領域を長〈とる必要があυ、オン抵抗ＲＯ
Ｎ及び相互コンダクタンスｇ、は改善されない。そこで
、ゲートとドレイン間の距離を比較的短かくし、オン抵
抗を下げる方法としてドレイン側のゲート酸化膜を厚く
して、ゲート−ドレイン間の電界集中を抑える方法がと
られている。この方法を第２図を用いて説明する。ドレ
イン側の厚いゲート酸化膜３は工程の簡単化のためシリ
コンゲート型ＭＯＳ Ｆ ＥＴのフィールド酸化膜を形
成するＬＯＣＯ８法で同時に形成する。Ｐｆｉ不純物基
板１とフィールド酸化膜２．３の間には、比較的高濃度
のＰ型不純物層７，１０がチャネルストッパーとして設
けられる。However, in the field plate method, it is necessary to make the drift region long, and therefore the MOSFET has the drawbacks of a large resistance Rev and a small mutual conductance g1. Even in the stacked gate method, it is necessary to make the drift channel region long, and the on-resistance RO
N and transconductance g, are not improved. Therefore, in order to reduce the on-resistance by making the distance between the gate and the drain relatively short, a method has been adopted in which the gate oxide film on the drain side is made thicker to suppress the electric field concentration between the gate and the drain. This method will be explained using FIG. 2. The thick gate oxide film 3 on the drain side is formed at the same time by the LOCO8 method, which is used to form a field oxide film of a silicon gate type MOSFET, in order to simplify the process. Between the Pfi impurity substrate 1 and the field oxide film 2.3, relatively high concentration P type impurity layers 7 and 10 are provided as channel stoppers.
上述した従来のＭＩＳＦＥＴは、ＬＯＣＯ８法によシ形
成したフィールド酸化膜の下に基板と同じ導’ｉｔ型の
高濃度チャネルストッパーが存在するため、厚いゲート
酸化膜の下のチャネルストッパーは、ＭＩＳＦＥＴのド
レインピンチ抵抗として相互フンダクタンスｇ１を下げ
、電流−電圧特性を劣化させる。また、ドレイン側のチ
ャネルストッパーは、ドレインと接しているため接合耐
圧が弱（、ＭＩＳＦＥＴの高耐圧化に適していないとい
う欠点がある。In the conventional MISFET described above, a high concentration channel stopper of the same conductivity type as the substrate exists under the field oxide film formed by the LOCO8 method, so the channel stopper under the thick gate oxide film is As a drain pinch resistance, it lowers the mutual fundance g1 and deteriorates the current-voltage characteristics. Further, since the channel stopper on the drain side is in contact with the drain, the junction breakdown voltage is weak (and is not suitable for increasing the breakdown voltage of MISFETs).
本発明は、上記欠点を除去し、ドレイン側のピンチ抵抗
を小さくしそれによシミ波電圧特性を改善し、またしき
い電圧ＶＴの不安定性をなくシ、かつ、ドレイン−基板
間耐圧を改善したＭＩＳ型電界効果トランジスタを提供
することを目的とする。The present invention eliminates the above drawbacks, reduces pinch resistance on the drain side, thereby improving stain wave voltage characteristics, eliminates instability of threshold voltage VT, and improves drain-substrate breakdown voltage. An object of the present invention is to provide a MIS type field effect transistor.
本発明のＭＩＳ型電界効果トランジスタは、−導電型を
有する半導体基板の一主表面にドレイン近傍のゲート絶
縁膜が厚く形成されたＭＩＳ型電界効果トランジスタに
おいて、前記厚い絶縁膜下の半導体基板表面には反対導
電型層を有し、反対導電型を有するドレイン領域は前記
反対導電型層に接し、かつ前記半導体基板よシ高い不純
物濃度を有する一導電型領域とは＃Ｉ間されていること
を特徴として構成される。The MIS field effect transistor of the present invention has a thick gate insulating film near the drain formed on one main surface of a semiconductor substrate having a -conductivity type, wherein has an opposite conductivity type layer, and the drain region having the opposite conductivity type is in contact with the opposite conductivity type layer and is separated from the one conductivity type region having a higher impurity concentration than the semiconductor substrate. Constructed as a feature.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の断面図である。本実施例で
はＭＩＳＦＥＴＫつき説明する。FIG. 1 is a sectional view of an embodiment of the present invention. In this embodiment, MISFETK will be explained.
まず、第１図に示すように、Ｐ型シリコン基板に、ＬＯ
ＣＯ８法で形成した厚いゲートｍ化膜３の直下にイオン
注入法にてＮ型低濃度膚８を、Ｎ型高漉度のドレイン拡
散膚５と接するように形成する。また、シリコン基板と
同導ル、形のＰ型窩濃度層チャネルストッパー７Ｌソー
ス側のフィールド酸化膜の下に形成し、ドレイン側には
形成しない。First, as shown in FIG. 1, LO
An N-type low concentration layer 8 is formed by ion implantation directly under the thick gate m-concentration layer 3 formed by the CO8 method so as to be in contact with the N-type high concentration drain diffusion layer 5. Further, a P-type hole concentration layer channel stopper 7L having the same conductivity as the silicon substrate is formed under the field oxide film on the source side, but not on the drain side.
このように形成された高耐圧ＭＯ８ＦＥＴはドレイン側
の厚いゲー）［化膜３の下に低濃度のＮ型導電層を設け
ているため、ピンチ抵抗が小さくなる。The high breakdown voltage MO8FET formed in this manner has a thick gate on the drain side and has a low concentration N-type conductive layer under the dielectric film 3, so that the pinch resistance is reduced.
また、ゲートとドレイン低濃度層が、オーバーラツプし
ているため、反転しない領域が存在しなくなり、ＭＯＳ
ＦＥＴの電流−電圧特性が改善されるとともに、しきい
電圧ＶＴの不安定性が改善される。また、ドレイン側の
フィールド領域下には、千七未ルストッパー９語Ｈ％Ｉ
ハので ト０１／インのチャネルストッパー側での耐圧
の劣化がなくなる。In addition, since the gate and drain low concentration layers overlap, there is no region that does not invert, and the MOS
The current-voltage characteristics of the FET are improved, as well as the instability of the threshold voltage VT. In addition, under the field area on the drain side, there is a 9-word stopper H%I.
Therefore, there is no deterioration in the withstand voltage on the channel stopper side of the 01/in.
なお、本実施例ではＮチャネル型のＭＯＳＦＥＴについ
て説明したがＰチャネル型のＭＯＳＦＥＴにも適用でき
ることは説明するまでもなく、またＭＩＳＦＥＴ全般に
適用できる。In this embodiment, an N-channel type MOSFET has been described, but it goes without saying that the present invention can also be applied to a P-channel type MOSFET, and can also be applied to MISFETs in general.
以上説明したように本発明は、ＭＩＳＦＥＴのドレイン
側の厚いゲート絶縁膜の下にシリコン基板と逆導電型の
低濃度層を形成することによシ、ドレイン側で生じるピ
ンチ抵抗を小さくすることができる。As explained above, the present invention makes it possible to reduce the pinch resistance occurring on the drain side by forming a low concentration layer of the opposite conductivity type to the silicon substrate under the thick gate insulating film on the drain side of the MISFET. can.
また、このためＭＩＳＦＥＴの電流−電圧特性も改善さ
れる。また、ゲー１［造がオフセットでなくなるためＭ
ＩＳＦＥＴのしきい電圧ＶＴの不安定性がなくなる。Furthermore, the current-voltage characteristics of the MISFET are also improved. Also, since game 1 [structure is no longer offset, M
The instability of the threshold voltage VT of the ISFET is eliminated.
さらに、フィールド酸化膜の下は、ソース側では基板と
ｈ導電型のチャネルストッパーを設はフィールドの反転
防止を行ない、ドレイン側は、チャネルストッパーを設
けないことによシトレイン−基板間耐圧は、向上できる
。Furthermore, under the field oxide film, a channel stopper of h-conductivity type is provided with the substrate on the source side to prevent field reversal, and no channel stopper is provided on the drain side, thereby improving the breakdown voltage between the cell line and the substrate. can.
第１図は本発明の一実施例の断面図、第２図は従来の高
耐圧ＭＯ８ＦＥＴの断面図である。
ｌ・・・・・・Ｐ型シリコン基板、２・・・・・・フィ
ールド酸化膜、３・・・・・・ドレイン側の厚いゲー）
＆化膜、４・・・・・・Ｎ型ソース拡散層、５・・・・
・・Ｎ型ドレイン拡散層、６・・・・・・多結晶シリコ
ンケート、７・・・・・・Ｐ型高濃度のチャネルストッ
パー、８・・・・・・Ｎ型低濃度層、９・・・・・・ソ
ース側の薄いゲート酸化膜、１０・・・・・・Ｐ型高濃
度層。
第１図
第２図FIG. 1 is a sectional view of an embodiment of the present invention, and FIG. 2 is a sectional view of a conventional high voltage MO8FET. 1... P-type silicon substrate, 2... Field oxide film, 3... Thick gate on drain side)
& chemical film, 4...N-type source diffusion layer, 5...
...N-type drain diffusion layer, 6...Polycrystalline silicone layer, 7...P-type high concentration channel stopper, 8...N-type low concentration layer, 9. ... Thin gate oxide film on the source side, 10 ... P-type high concentration layer. Figure 1 Figure 2
Claims (1)
のゲート絶縁膜が厚く形成されたＭＩＳ型電界効果トラ
ンジスタにおいて、前記厚いゲート絶縁膜下の半導体基
板表面には反対導電型層を有し、反対導電型を有するド
レイン領域は前記反対導電型層に接し、かつ前記半導体
基板より高い不純物濃度を有する一導電型領域とは離間
されていることを特徴とするＭＩＳ型電界効果トランジ
スタ。In a MIS field effect transistor in which a thick gate insulating film near the drain is formed on one main surface of a semiconductor substrate having one conductivity type, a layer of an opposite conductivity type is provided on the surface of the semiconductor substrate under the thick gate insulating film, A MIS type field effect transistor characterized in that a drain region having an opposite conductivity type is in contact with the opposite conductivity type layer and is separated from a one conductivity type region having an impurity concentration higher than that of the semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60073902A JPS61231768A (en) | 1985-04-08 | 1985-04-08 | Mis type field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60073902A JPS61231768A (en) | 1985-04-08 | 1985-04-08 | Mis type field effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61231768A true JPS61231768A (en) | 1986-10-16 |
Family
ID=13531586
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60073902A Pending JPS61231768A (en) | 1985-04-08 | 1985-04-08 | Mis type field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61231768A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63164258A (en) * | 1986-12-25 | 1988-07-07 | Fujitsu Ltd | Input/output circuit characterized by high breakdown strength |
| US5598021A (en) * | 1995-01-18 | 1997-01-28 | Lsi Logic Corporation | MOS structure with hot carrier reduction |
-
1985
- 1985-04-08 JP JP60073902A patent/JPS61231768A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63164258A (en) * | 1986-12-25 | 1988-07-07 | Fujitsu Ltd | Input/output circuit characterized by high breakdown strength |
| US5598021A (en) * | 1995-01-18 | 1997-01-28 | Lsi Logic Corporation | MOS structure with hot carrier reduction |
| US5663083A (en) * | 1995-01-18 | 1997-09-02 | Lsi Logic Corporation | Process for making improved MOS structure with hot carrier reduction |
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