JPS61230123A - Optical series parallel/parallel series converting circuit - Google Patents
Optical series parallel/parallel series converting circuitInfo
- Publication number
- JPS61230123A JPS61230123A JP60071760A JP7176085A JPS61230123A JP S61230123 A JPS61230123 A JP S61230123A JP 60071760 A JP60071760 A JP 60071760A JP 7176085 A JP7176085 A JP 7176085A JP S61230123 A JPS61230123 A JP S61230123A
- Authority
- JP
- Japan
- Prior art keywords
- signals
- optical
- parallel
- serial
- bit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
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- Light Guides In General And Applications Therefor (AREA)
- Communication Control (AREA)
- Optical Communication System (AREA)
Abstract
Description
〔産業上の利用分野〕
本発明は光直並列/並直列変換回路に関し、特に複数の
入力光ハイウェイと複数の出力光ハイウェイの間におい
て直列信号を並列信号に、それと同時に同時入力の並列
信号を直列信号に変換する光直並列/並直列変換回路に
関するものである。
〔発明の概要〕
この発明は、光直並列/並直列変換回路において、n本
の光ハイウェイから直列状に信号を受信すると、その受
信4号を光遅延回路により各光ハイウェイに対応させて
遅延した後、光スイッチと光結合器により同時刻受信の
n個の並列信号を直列状とするようにビット単位で通過
路を振分け。
その振分けた直列信号を再び光遅延回路で各光ハイウェ
イに対応させて遅延することにより、直列信号を並列信
号に、それと同時番;並列信号を直列信号に変換するよ
うにしたものである。
〔従来の技術〕
光ハイウェイを用いた情報の通信は、従来の通信方式に
比べて、広帯域、低損失、電磁誘導障害がない、などの
優れた特長を持っているので、CPU間通信など広く実
用化が進められている。
光通信の実用化に際しては、光ハイウェイ上において光
信号のままで処理することができると有利なことから各
機能を持つ光処理回路が検討されている。その中の1つ
である光交換機、すなわち時分割多重による光通信が行
われている複数の光ハイウェイの相互に渡り、ハイウェ
イ信号の交換を行うことのできる処理回路にも種々の処
理機能が要求されている。特に、n本の光ハイウェイか
ら各々入力した直列状のハイウェイ信号をnビットの単
位で並列状の信号に変換し、n本の光ハイウェイに同時
に出力する機能、すなわち光信号の直並列/並直列変換
機能が求められている。
(発明が解決しようとする問題点〕
しかし、光通信における光論理素子自体が未だ成熟して
ないこと、AND、ORなどの論理ゲート類やフリップ
・プロップなどの基本的な回路素子についてのみ検討・
報告がなされている程度であることから、上記光面並列
/並直列変換機能を持つ処理口w11=関する検討・報
告は未だなされてない。
本発明はこのような点にかんがみて創案されたもので、
簡単な構成により、複数の入力光ハイウェイと複数の出
力光ハイウェイの間において直列信号を並列信号に、そ
れと同時に同時刻受信の並列信号を直列信号に変換する
ことのできる光面並列/並直列変換回路を提供すること
にある。[Industrial Application Field] The present invention relates to an optical serial-parallel/parallel-serial conversion circuit, and in particular, it converts serial signals into parallel signals between a plurality of input optical highways and a plurality of output optical highways, and simultaneously converts simultaneously input parallel signals. This invention relates to an optical serial-parallel/parallel-serial conversion circuit that converts into serial signals. [Summary of the Invention] This invention provides an optical serial-parallel/parallel-serial conversion circuit that, when receiving signals in series from n optical highways, delays the received signal No. 4 by using an optical delay circuit to correspond to each optical highway. After that, an optical switch and an optical coupler are used to distribute the paths in bit units so that the n parallel signals received at the same time are serialized. By delaying the distributed serial signals again in accordance with each optical highway using an optical delay circuit, the serial signals are converted into parallel signals, and the parallel signals are converted into serial signals. [Prior art] Information communication using optical highways has superior features compared to conventional communication methods, such as broadband, low loss, and no electromagnetic induction interference, so it is widely used for communication between CPUs, etc. Practical implementation is underway. When putting optical communications into practical use, optical processing circuits with various functions are being considered because it would be advantageous to be able to process optical signals as they are on optical highways. Various processing functions are also required for optical switching equipment, which is one of these systems, which is a processing circuit that can exchange highway signals between multiple optical highways where optical communication is performed using time division multiplexing. has been done. In particular, the function is to convert serial highway signals input from n optical highways into parallel signals in units of n bits, and simultaneously output them to n optical highways, that is, serial parallel/parallel serial optical signals. Conversion functionality is required. (Problems to be solved by the invention) However, the optical logic elements themselves in optical communications are not yet mature, and only basic circuit elements such as logic gates such as AND and OR and flip-flops have been studied.
Since only a few reports have been made, no study or report has been made regarding the processing port w11= having the above-mentioned optical surface parallel/parallel-serial conversion function. The present invention was devised in view of these points.
Optical surface parallel/parallel-serial conversion that can convert serial signals to parallel signals between multiple input optical highways and multiple output optical highways, and simultaneously convert parallel signals received at the same time to serial signals with a simple configuration. The purpose is to provide circuits.
第1図は本発明の光面並列/並直列変換回路の構成ブロ
ック図であって、第1図において、Al〜Anはハイウ
ェイ信号a l ”” a nを入力する端子、Bl”
Bnは入力ハイウェイ信号a1〜anを[(k−1)・
T】秒間遅延する第1の光遅延回路、G1=Gnは選択
信号g1〜gnを入力する端子、 CI ”Cnは選択
信号g1〜gnにより入力と出力光ハイウェイをT(秒
)ごとに切換え・接続するIXnの光スイッチ、DI”
Dnは光スイッチ01〜Cnからのn個の信号を1本の
光ハイウェイに光結合する光結合器、El”Enは光結
合器の出力d 1” d nを[(n−k)・Tl (
秒)遅延する第2の光遅延回路であって、光面並列/並
直列に変換された出力ハイウェイ信号をそれぞれ出力端
子F 1 ” F nに得る。
〔作 用〕
入力ハイウェイ信号a 1 ” a nを第1の光遅延
回路により光ハイウェイに対応させて時間軸方向に移動
し、その遅延させた信号b 1 ” b nを光スイッ
チおよび光結合器により同時刻受信のn個のハイウェイ
信号が直列状となるように配列して、その直列状の信号
d1〜dnを第2の光遅延回路により光ハイウェイに対
応させて時間軸方向に移動し時間的な補正を行うので、
第1図の構成により、n個のハイウェイ信号の光面並列
/並直列変換が可能となる。
〔実 施 例〕
第1図は本発明による光面並列/並直列変換回路の一実
施例であり、第2図は第1図の回路動作を説明するため
のタイミングチャートである。なお、本実施例における
入/出力の光ハイウェイは4本(n = 4 )である
、また、第2図中の(at)〜(a4)−(bt )〜
(b4)−(gt )〜(g4)、(dt )〜(d
4 )−(a t )=(e 4 )はそれぞれ第1図
においてn=4としたときの同一アルファベットの小文
字記号に対応し、一方のX1j(ただし、1ej=1〜
4)はハイウェイ信号におけるビット単位の信号であり
、1番目の入力光ハイウェイにおける1番目の(変換単
位4ビツト中の)ビット値であることを示す。
今、4本の光ハイウェイから第2図の(ax)〜(a4
)に示すような入力ハイウェイ信号を受信し牟場合、先
ず、光遅延回路B1−84が同時刻に並列状に入力した
4個のビット信号を出力光ハイウェイにおいて時間軸上
直列の状態となるように。
[(k−1)・T】秒間(ただし、k=1,2,3゜4
、Tは1ビツト当たりの時間)遅延して、第2図の(b
u)〜(b4)に示すような1ビツトずつ位相をずらし
た信号にする。すなわち、l、2,3゜4本目の各ハイ
ウェイ信号はそれぞれ# OH、II I II。
”2#l、03”ビット遅延される。なお、遅延は例え
ば光ハイウェイの憂さを変えて行う。
次に、光スイッチC1−C4が第2図の(gl)〜(g
4)に示す選択信号により光ハイウェイの接続を切換え
て1位相のずれた徊号bt−b4の中からXll#X4
1y X12NX42+ xta7X49sXiφ〜X
44のビット信号をそれぞれ光結合$DI、D2.D3
.D4に振分ける。なお(gl)〜(g4)の■は入力
信号b1〜b4を第1図の光スイッチの■端に振分けて
光結合器D1に送ることを表わす、■〜■も同様である
。また、光スイッチとしては光導波路型のスイッチを使
用する。
続いて、光結合1lD1〜D4が光スイッチC1〜C4
から送られた4個のビット信号を光結合して、上記で振
分けられた4個のビット信号を第2図の(dl)〜(d
4)に示すように再構成する。なお、光結合器としては
光の分配量を使用する。
続いて、光遅延回路E1〜E4が光結合器の出力d1−
d4を[(n−k)−T1秒間遅延して第2図の(el
)〜(B4)に示すような時間ズレを補正した出力ハイ
ウェイ信号にする。すなわち、1゜2.3.4本目の各
ハイウェイ信号はそれぞれ′3〃。
“2” 111″ II Q IIビット遅延される。
このように、4本の入力光ハイウェイから受信した第2
図の(al)〜(a4)に示す直列・並列信号を上述し
た方法により第2図の(el)〜(B4)に示すような
並列・直列信号に変換し、出力光ハイウェイに送出する
ことができる。すなわち、入力光ハイウェイから受信し
九゛’ X x jItの各ビット信号を行lと列jと
を入れ換えた” X j i”のビット信号に変換しく
行列の転置に相当)、出力光ハイウェイに送出すること
が可能である。
(発明の効果〕
以上説明したように1本発明によれば、n本の光ハイウ
ェイから受信したハイウェイ信号を光遅延回路で[(k
−1)・T】秒間遅延し、その信号を同時刻に受信した
ハイウェイ信号のビット単位の信号が直列状となるよう
に光スイッチでハイウェイを切換えて、光結合器で光結
合し、それを再び光遅延回路で[(n−k)・T】秒間
遅延し補正するので、簡単な回路構成で複数の入力光ハ
イウェイと複数の出力光ハイウェイ間における光直並列
/並直列変換、すなわち直列ハイウェイ信号を並列ハイ
ウェイ信号に、それと同時に同時刻受信の並列ハイウェ
イ信号を直列ハイウェイ信号に変換することができる。FIG. 1 is a block diagram of the configuration of an optical surface parallel/parallel-serial conversion circuit according to the present invention. In FIG. 1, Al to An are terminals for inputting the highway signal a l"" a
Bn converts the input highway signals a1 to an to [(k-1)・
G1=Gn is a terminal to which selection signals g1 to gn are input; CI "Cn is a terminal that switches input and output optical highways every T (seconds) by selection signals g1 to gn. IXn optical switch to connect, DI”
Dn is an optical coupler that optically couples n signals from optical switches 01 to Cn into one optical highway, and El"En is an optical coupler that optically couples the output d1"dn of the optical coupler with (
Second optical delay circuit which delays the optical plane parallel/parallel/serial output highway signals to output terminals F 1 ” F n respectively. [Function] Input highway signal a 1 ” a n is moved in the time axis direction by a first optical delay circuit in correspondence with the optical highway, and the delayed signal b 1 '' b n is converted into n highway signals received at the same time by an optical switch and an optical coupler. They are arranged in series, and the serial signals d1 to dn are moved in the time axis direction by a second optical delay circuit in correspondence with the optical highway to perform temporal correction.
The configuration shown in FIG. 1 enables optical plane parallel/parallel-serial conversion of n highway signals. [Embodiment] FIG. 1 shows an embodiment of the optical surface parallel/parallel-serial conversion circuit according to the present invention, and FIG. 2 is a timing chart for explaining the operation of the circuit shown in FIG. 1. In addition, the number of input/output optical highways in this embodiment is four (n = 4), and (at) to (a4) - (bt) to
(b4) - (gt) ~ (g4), (dt) ~ (d
4)-(a t )=(e 4 ) correspond to the lowercase letters of the same alphabet when n=4 in Figure 1, and one X1j (however, 1ej=1~
4) is a bit-by-bit signal in the highway signal, and indicates the first bit value (of the conversion unit of 4 bits) in the first input optical highway. Now, from the four optical highways (ax) to (a4) in Figure 2,
), first, the optical delay circuit B1-84 inputs four bit signals in parallel at the same time so that they become serial on the time axis on the output optical highway. To. [(k-1)・T] seconds (k=1, 2, 3°4
, T is the time per bit), and (b
The signals shown in u) to (b4) are made with the phase shifted one bit at a time. That is, the 4th highway signals of 1, 2, and 3 degrees are #OH, II II II, respectively. Delayed by "2#l, 03" bits. In addition, the delay is carried out by changing the severity of the optical highway, for example. Next, the optical switches C1-C4 switch from (gl) to (g) in FIG.
The connection of the optical highway is switched by the selection signal shown in 4), and Xll #
1y X12NX42+ xta7X49sXiφ~X
44 bit signals are optically coupled $DI, D2 . D3
.. Assign to D4. In (gl) to (g4), ``■'' indicates that the input signals b1 to b4 are distributed to the ``terminal'' of the optical switch in FIG. Furthermore, an optical waveguide type switch is used as the optical switch. Subsequently, the optical couplings 11D1 to D4 are connected to the optical switches C1 to C4.
By optically coupling the four bit signals sent from the
Reconfigure as shown in 4). Note that the light distribution amount is used as the optical coupler. Subsequently, the optical delay circuits E1 to E4 output the output d1- of the optical coupler.
d4 is delayed for [(n-k)-T1 seconds to obtain (el
) to (B4), the time lag is corrected to produce an output highway signal. In other words, the 1st, 2nd, 3rd, and 4th highway signals are each '3'. "2"111" II Q II bit delayed. In this way, the second
Converting the serial/parallel signals shown in (al) to (a4) in the figure into parallel/serial signals shown in (el) to (B4) in Fig. 2 using the method described above, and sending them to the output optical highway. I can do it. In other words, each bit signal of 9' X x jIt received from the input optical highway is converted into a bit signal of "X It is possible to send out. (Effects of the Invention) As explained above, according to the present invention, highway signals received from n optical highways are processed by optical delay circuits [(k
−1)・T] seconds, the highway signal is switched by an optical switch so that the bit-by-bit signal of the highway signal received at the same time becomes serial, and the optical coupler optically couples the signals. Again, the optical delay circuit delays and compensates for [(n-k)・T] seconds, so a simple circuit configuration can perform optical serial-parallel/parallel-serial conversion between multiple input optical highways and multiple output optical highways, that is, serial highway. It is possible to convert signals into parallel highway signals and simultaneously convert parallel highway signals received at the same time into serial highway signals.
第1図は本発明の一実施例を示す光直並列/並直列変換
回路の構成ブロック図、第2図は第1図の回路動作を説
明するためのタイミング・チャートである。
A 1〜A n # G L 〜Q n :入力端子、
B1”Bn。
El”En:光遅延回路、’C!−Cn:光スイッチ、
DI”DnS光結合器、Fl〜Fn:出力端子。FIG. 1 is a block diagram of the configuration of an optical serial-parallel/parallel-serial conversion circuit showing an embodiment of the present invention, and FIG. 2 is a timing chart for explaining the operation of the circuit shown in FIG. A1~An#GL~Qn: Input terminal,
B1"Bn. El"En: Optical delay circuit, 'C! -Cn: optical switch,
DI”DnS optical coupler, Fl to Fn: output terminals.
Claims (1)
号(若しくは並列信号)をビット単位で並列信号(若し
くは直列信号)に変換してn本の出力光ハイウェイに送
出する光直並列/並直列変換回路において、上記直列信
号を遅延する第1の光遅延回路と、該光遅延回路の出力
の導波路を上記T(秒)ごとにn本に切換える光スイッ
チと、該光スイッチが出力するn個のビット単位の信号
を1本の光ハイウェイに送り込む光結合器と、該光結合
器の出力信号を遅延する第2の光遅延回路とを備え、上
記入力光ハイウェイと上記出力光ハイウェイの間におい
て直列のビット信号を並列に、同時に同時刻受信の並列
のビット信号を直列に変換することを特徴とする光直並
列/並直列変換回路。(1) Optical serial-parallel/parallel-serial system that converts the serial signals (or parallel signals) received from n input optical highways into parallel signals (or serial signals) bit by bit and sends them to n output optical highways. The conversion circuit includes a first optical delay circuit that delays the serial signal, an optical switch that switches the output waveguide of the optical delay circuit into n waveguides every T (seconds), and a first optical delay circuit that delays the serial signal. an optical coupler that sends a signal in units of bits to one optical highway, and a second optical delay circuit that delays the output signal of the optical coupler, between the input optical highway and the output optical highway. 1. An optical serial-parallel/parallel-serial conversion circuit characterized in that it converts serial bit signals into parallel signals and simultaneously converts parallel bit signals received at the same time into serial signals.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60071760A JPH0750283B2 (en) | 1985-04-04 | 1985-04-04 | Light series parallel / parallel series batch conversion circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60071760A JPH0750283B2 (en) | 1985-04-04 | 1985-04-04 | Light series parallel / parallel series batch conversion circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS61230123A true JPS61230123A (en) | 1986-10-14 |
JPH0750283B2 JPH0750283B2 (en) | 1995-05-31 |
Family
ID=13469816
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60071760A Expired - Lifetime JPH0750283B2 (en) | 1985-04-04 | 1985-04-04 | Light series parallel / parallel series batch conversion circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0750283B2 (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58187912A (en) * | 1982-04-28 | 1983-11-02 | Matsushita Electric Ind Co Ltd | Series-parallel converting device of optical signal |
-
1985
- 1985-04-04 JP JP60071760A patent/JPH0750283B2/en not_active Expired - Lifetime
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58187912A (en) * | 1982-04-28 | 1983-11-02 | Matsushita Electric Ind Co Ltd | Series-parallel converting device of optical signal |
Also Published As
Publication number | Publication date |
---|---|
JPH0750283B2 (en) | 1995-05-31 |
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